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Fri, 20 Feb 2026 19:44:21 -0800 (PST) From: Rosen Penev To: stable@vger.kernel.org Cc: Kenneth Feng , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , amd-gfx@lists.freedesktop.org (open list:AMD POWERPLAY AND SWSMU), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/2] Revert "drm/amd/pm: Disable MCLK switching on SI at high pixel clocks" Date: Fri, 20 Feb 2026 19:44:01 -0800 Message-ID: <20260221034402.69537-2-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260221034402.69537-1-rosenp@gmail.com> References: <20260221034402.69537-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This reverts commit d033e8cf4e8f6395102cdbc3cb00dc7cb9542f53. Cc: Timur Krist=C3=B3f Cc: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/a= md/pm/legacy-dpm/si_dpm.c index 29cecfab0704..05eaa06dfa34 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3486,11 +3486,6 @@ static void si_apply_state_adjust_rules(struct amdgp= u_device *adev, * for these GPUs to calculate bandwidth requirements. */ if (high_pixelclock_count) { - /* Work around flickering lines at the bottom edge - * of the screen when using a single 4K 60Hz monitor. - */ - disable_mclk_switching =3D true; - /* On Oland, we observe some flickering when two 4K 60Hz * displays are connected, possibly because voltage is too low. * Raise the voltage by requiring a higher SCLK. --=20 2.53.0 From nobody Fri Apr 17 09:30:28 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B6CB327C0F for ; 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Fri, 20 Feb 2026 19:44:23 -0800 (PST) Received: from ryzen ([2601:644:8000:56f5::8bd]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ba11bsm714951b3a.50.2026.02.20.19.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Feb 2026 19:44:23 -0800 (PST) From: Rosen Penev To: stable@vger.kernel.org Cc: Kenneth Feng , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , amd-gfx@lists.freedesktop.org (open list:AMD POWERPLAY AND SWSMU), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] Revert "drm/amd/pm: Disable SCLK switching on Oland with high pixel clocks (v3)" Date: Fri, 20 Feb 2026 19:44:02 -0800 Message-ID: <20260221034402.69537-3-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260221034402.69537-1-rosenp@gmail.com> References: <20260221034402.69537-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This reverts commit 0bb91bed82d414447f2e56030d918def6383c026. This commit breaks stable kernels older than 6.18 that are booted with radeon.si_support=3D0 amdgpu.si_support=3D1 amdgpu.dc=3D1 In 6.17, threre are further commits that are needed to get the DC codepath in amdgpu for Southern Islands GPUs working but they seem to be too much of a hastle to backport cleanly. The simplest solution is to revert this problematic commit Cc: Timur Krist=C3=B3f Cc: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 31 ---------------------- 1 file changed, 31 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/a= md/pm/legacy-dpm/si_dpm.c index 05eaa06dfa34..c4386c86153b 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3426,14 +3426,12 @@ static void si_apply_state_adjust_rules(struct amdg= pu_device *adev, { struct si_ps *ps =3D si_get_ps(rps); struct amdgpu_clock_and_voltage_limits *max_limits; - struct amdgpu_connector *conn; bool disable_mclk_switching =3D false; bool disable_sclk_switching =3D false; u32 mclk, sclk; u16 vddc, vddci, min_vce_voltage =3D 0; u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; u32 max_sclk =3D 0, max_mclk =3D 0; - u32 high_pixelclock_count =3D 0; int i; =20 if (adev->asic_type =3D=3D CHIP_HAINAN) { @@ -3466,35 +3464,6 @@ static void si_apply_state_adjust_rules(struct amdgp= u_device *adev, } } =20 - /* We define "high pixelclock" for SI as higher than necessary for 4K 30H= z. - * For example, 4K 60Hz and 1080p 144Hz fall into this category. - * Find number of such displays connected. - */ - for (i =3D 0; i < adev->mode_info.num_crtc; i++) { - if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) || - !adev->mode_info.crtcs[i]->enabled) - continue; - - conn =3D to_amdgpu_connector(adev->mode_info.crtcs[i]->connector); - - if (conn->pixelclock_for_modeset > 297000) - high_pixelclock_count++; - } - - /* These are some ad-hoc fixes to some issues observed with SI GPUs. - * They are necessary because we don't have something like dce_calcs - * for these GPUs to calculate bandwidth requirements. - */ - if (high_pixelclock_count) { - /* On Oland, we observe some flickering when two 4K 60Hz - * displays are connected, possibly because voltage is too low. - * Raise the voltage by requiring a higher SCLK. - * (Voltage cannot be adjusted independently without also SCLK.) - */ - if (high_pixelclock_count > 1 && adev->asic_type =3D=3D CHIP_OLAND) - disable_sclk_switching =3D true; - } - if (rps->vce_active) { rps->evclk =3D adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; rps->ecclk =3D adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; --=20 2.53.0