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Fri, 20 Feb 2026 15:31:10 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] ARM: dts: imx6ul/imx6ull: add boot phase properties Date: Fri, 20 Feb 2026 15:31:02 +0100 Message-ID: <20260220143107.186956-2-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260220143107.186956-1-Max.Merchel@ew.tq-group.com> References: <20260220143107.186956-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay48-hz3.antispameurope.com with 4fHXjq10Y0z1kNt3l X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: b31b8f68e1352bc9e8374fc850558ebc X-cloud-security: scantime:1.849 DKIM-Signature: a=rsa-sha256; bh=8Wg8hhuphaDA1KXI4FRar5JXbbzUBqxPKxV6zXxqMdA=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771597887; v=1; b=S7BOVjOojodC8yDYZDSMJOevo/UgZ2HnBIue9KfQgDLyNp/5DVbrg2G9WBAIW8fAuNHCFl07 VRALvem21+EnmocrhHUVQkdsb2A/0a8LxMlbrQYB/GEwqQ/hQlpKaUaJLzQ9mo/n2gRJUvdQ4cF TenJN4DYizHMRvAmsS42yxQlA2nwMkh/MejsaQ7labSpIqt2EXNayBARxoG3U/Zez503IqGEGNl imRakIrv/8icPofvm8/ny9uyvb3J4Is4iqSArEYMPLQTJY+7FeeszSRxLXMFc0f9sfRwcJSJMsj rz5KlcDn3SqTvIosKCJbci+4ySvCshbqZNdvEoPTTe3QQ== Content-Type: text/plain; charset="utf-8" dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. All SoCs require buses (aips and spba), clock, iomuxc and SOC access during boot process. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6ul.dtsi | 7 +++++++ arch/arm/boot/dts/nxp/imx/imx6ull.dtsi | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/= imx/imx6ul.dtsi index 6eb80f867f50..24541fdf49ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -115,6 +115,7 @@ osc: clock-osc { #clock-cells =3D <0>; clock-frequency =3D <24000000>; clock-output-names =3D "osc"; + bootph-pre-ram; }; =20 ipp_di0: clock-di0 { @@ -143,6 +144,7 @@ soc: soc { compatible =3D "simple-bus"; interrupt-parent =3D <&gpc>; ranges; + bootph-pre-ram; =20 ocram: sram@900000 { compatible =3D "mmio-sram"; @@ -202,6 +204,7 @@ aips1: bus@2000000 { #size-cells =3D <1>; reg =3D <0x02000000 0x100000>; ranges; + bootph-pre-ram; =20 spba-bus@2000000 { compatible =3D "fsl,spba-bus", "simple-bus"; @@ -209,6 +212,7 @@ spba-bus@2000000 { #size-cells =3D <1>; reg =3D <0x02000000 0x40000>; ranges; + bootph-pre-ram; =20 ecspi1: spi@2008000 { #address-cells =3D <1>; @@ -580,6 +584,7 @@ clks: clock-controller@20c4000 { #clock-cells =3D <1>; clocks =3D <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; clock-names =3D "ckil", "osc", "ipp_di0", "ipp_di1"; + bootph-pre-ram; }; =20 anatop: anatop@20c8000 { @@ -745,6 +750,7 @@ power-domain@0 { iomuxc: pinctrl@20e0000 { compatible =3D "fsl,imx6ul-iomuxc"; reg =3D <0x020e0000 0x4000>; + bootph-pre-ram; }; =20 gpr: iomuxc-gpr@20e4000 { @@ -826,6 +832,7 @@ aips2: bus@2100000 { #size-cells =3D <1>; reg =3D <0x02100000 0x100000>; ranges; + bootph-pre-ram; =20 crypto: crypto@2140000 { compatible =3D "fsl,imx6ul-caam", "fsl,sec-v4.0"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi b/arch/arm/boot/dts/nxp= /imx/imx6ull.dtsi index db0c339022ac..ba0ea10c7b74 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi @@ -57,6 +57,7 @@ aips3: bus@2200000 { #size-cells =3D <1>; reg =3D <0x02200000 0x100000>; ranges; + bootph-pre-ram; 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Fri, 20 Feb 2026 15:31:28 +0100 Received: from merchelm-W2.tq-net.de (host-82-135-125-110.customer.m-online.net [82.135.125.110]) (Authenticated sender: max.merchel@ew.tq-group.com) by hmail-p-smtp01-out04-hz1.hornetsecurity.com (Postfix) with ESMTPSA id 18AB4220CB6; Fri, 20 Feb 2026 15:31:11 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties Date: Fri, 20 Feb 2026 15:31:03 +0100 Message-ID: <20260220143107.186956-3-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260220143107.186956-1-Max.Merchel@ew.tq-group.com> References: <20260220143107.186956-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay68-hz1.antispameurope.com with 4fHXjq5LdBz2QYhL X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 39bf467f7897a36c62318cbf4ba7f61d X-cloud-security: scantime:2.185 DKIM-Signature: a=rsa-sha256; bh=603U3ROzybwhiSlbS4OAQhgc3+1jl0bt89ybh3NF/Nc=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771597888; v=1; b=dNaiMKJGzMxV+2oJo3p7gnqFut2u/hs9iGgbDuaYw29OSnq5mezGoMSiotnXGiCW94CCjb2X 30MBwguAUfX5H13NaKzJECj1DN85yW9mhPiCbLFgmKAqNuaB8CbYEu+ZqlVHMqmO9oNjrA7IYW4 JM55YqcGigJW9vODPlyirIpfGTGbLtDndgr4RBwHEXMxBpwJk23R0s5MiJL6QN74DMY/j3o77AQ WHEUJYb/KjqBcDjOpEKgPWVcbDcCAiEzSQ5ckZBOzR0U/AZaKdFg/a6f0dbru5UdwxCbcxKqGIF kqrfMN6cIX7+9+cXuZPwZ8Y9U3DYJkvF3SWngikwn69yw== Content-Type: text/plain; charset="utf-8" dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. TQMa6UL need eMMC, I2C, GPIO and QSPI access during boot process. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi | 10 ++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi | 1 + 7 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi index 2dd635a615cb..4fa98e6a66d7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -26,6 +26,7 @@ &i2c4 { pinctrl-1 =3D <&pinctrl_i2c4_recovery>; scl-gpios =3D <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + bootph-pre-ram; status =3D "okay"; =20 pfuze3000: pmic@8 { @@ -140,9 +141,14 @@ rtc0: rtc@68 { }; }; =20 +&gpio1 { + bootph-pre-ram; +}; + &gpio4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pmic>; + bootph-pre-ram; =20 /* * PMIC & temperature sensor IRQ @@ -159,6 +165,7 @@ pmic-int-hog { &qspi { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_qspi>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -168,6 +175,7 @@ flash0: flash@0 { spi-rx-bus-width =3D <4>; spi-tx-bus-width =3D <1>; vcc-supply =3D <®_vldo4>; + bootph-pre-ram; =20 partitions { compatible =3D "fixed-partitions"; @@ -189,6 +197,7 @@ &usdhc2 { non-removable; no-sdio; no-sd; + bootph-all; status =3D "okay"; }; =20 @@ -212,5 +221,6 @@ pinctrl_pmic: pmicgrp { /* PMIC irq */ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi b/arch/arm/boot= /dts/nxp/imx/imx6ul-tqma6ul2.dtsi index e2e95dd92263..f81cd09fe0c7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi @@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi b/arch/arm/boo= t/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi index 4b87e2dc70dc..11c8f1af4173 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi @@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi b/arch/a= rm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi index 5afb9046c202..5c90d0a3ee2e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi @@ -39,5 +39,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi b/arch/= arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi index ba84a4f70ebd..133961ee7283 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi @@ -44,5 +44,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi b/arch/arm/bo= ot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi index 8541cb3f3b3e..1224ef132439 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi @@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi b/arch/arm/b= oot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi index be593d47e3b1..6dd1b359e086 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi @@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { --=20 2.43.0 From nobody Fri Apr 3 06:26:51 2026 Received: from mx-relay48-hz3.antispameurope.com (mx-relay48-hz3.antispameurope.com [94.100.134.237]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60C6225A33F for ; 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bh=99ZE7SYGvViA3Bdc/s5b6uYab0kctnMzOeoylTWBVgU=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771597888; v=1; b=WXg6gTMgam7htfWPMDZqwgVYkXdevz38lOXBVvvntifm0QNHz4qwhrchUSreR4tQEajS99Mw aNELOtNljwrKn3fL+fxRnsnl0fYyaFIsrfsAb6d/F1i0GHrJKrRRgTjw5txd3xGfmqy1a1Vj1YM Og5IUq/rxeT/xsi7+9UG1sAkHN+3+fI9Qb6XLDEOyyugM5BBbXzr1Rre9K7fpiQOlpx2NFmSJYE GjAAVa2oWlTX+nMxa6XUxgd/liC43FaayC5zoFb5DycLXiVJUFTbn5Dll5XWRzvWbsDK3c+r1/b Bd7wCmUr03ypoA2juygpzWCIz4WERwH/PEnlCwPPBgPtQ== Content-Type: text/plain; charset="utf-8" dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. MBa6ULx need regulator, SD-Card, UART and watchdog access during boot process. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp= /imx/mba6ulx.dtsi index 65fde4f52587..1fda60d62ffe 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -95,6 +95,7 @@ reg_mba6ul_3v3: regulator-mba6ul-3v3 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-pre-ram; }; =20 reg_mba6ul_5v0: regulator-mba6ul-5v0 { @@ -336,6 +337,7 @@ &sai1 { &uart1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_uart1>; + bootph-pre-ram; status =3D "okay"; }; =20 @@ -392,6 +394,7 @@ &usdhc1 { no-1-8-v; no-mmc; no-sdio; + bootph-all; status =3D "okay"; }; =20 @@ -399,6 +402,7 @@ &wdog1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_wdog1>; fsl,ext-reset-output; + bootph-pre-ram; status =3D "okay"; }; =20 @@ -494,6 +498,7 @@ pinctrl_uart1: uart1grp { MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; 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Fri, 20 Feb 2026 15:31:30 +0100 Received: from merchelm-W2.tq-net.de (host-82-135-125-110.customer.m-online.net [82.135.125.110]) (Authenticated sender: max.merchel@ew.tq-group.com) by hmail-p-smtp01-out04-hz1.hornetsecurity.com (Postfix) with ESMTPSA id 4CCF8220B97; Fri, 20 Feb 2026 15:31:12 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems Date: Fri, 20 Feb 2026 15:31:05 +0100 Message-ID: <20260220143107.186956-5-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260220143107.186956-1-Max.Merchel@ew.tq-group.com> References: <20260220143107.186956-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay93-hz2.antispameurope.com with 4fHXjs02nKz4QPVS X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 7527063d6539b56d99d50d98f41cb596 X-cloud-security: scantime:2.103 DKIM-Signature: a=rsa-sha256; bh=PLt6KIS3heA6+KbSYDWlFsnZTNJOkMMZOLH/WTZ53uI=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771597890; v=1; b=JY3l/lWJ0mTD/Kg2M5BZ7XNIMmGu1QLo7sWSsgCrd54mOxUflGapi1HMCdlScFAHFEc3REN5 pHnhHW81z9+/qCGwmqlCecNeeTy7dtx4MJIFzxogZFMgS9V7aIbH6wCi/PZNc5uoXl+5Zdai7S0 gTUgB2+y4Y1M0prIPwLrGrSsDQfZtMh7R6YJGYlkIT63zIoj6JMyh+nGKBIY4UxlaQvJa6n4HKD fHhun4Q+VGtIqKiAgDihJH8zcYJFwGTOtSamGEzXH1u3rUS346an1Xc8RaFWsS+2VuYK3AROXIC jaXqF0tH5Ku/OmnstfmIDFoS1DCP+SfvdCHD8AS5Fk5FQ== Content-Type: text/plain; charset="utf-8" TQ-Systems is written with a hyphen. Correct the spelling. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/= arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts index 9d9b6b744a1c..9d637c0a12ec 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright 2018-2022 TQ Systems GmbH + * Copyright 2018-2022 TQ-Systems GmbH * Author: Markus Niebel */ =20 @@ -10,6 +10,6 @@ #include "mba6ulx.dtsi" =20 / { - model =3D "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + model =3D "TQ-Systems TQMa6UL2L SoM on MBa6ULx board"; compatible =3D "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl= ,imx6ul"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts b/arc= h/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts index 33437aae9822..5676904820a9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts @@ -10,6 +10,6 @@ #include "mba6ulx.dtsi" =20 / { - model =3D "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + model =3D "TQ-Systems TQMa6ULL2L SoM on MBa6ULx board"; compatible =3D "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", = "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi b/arch/arm/b= oot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi index 6dd1b359e086..ac18caf5a76c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi @@ -9,7 +9,7 @@ #include "imx6ul-tqma6ulxl-common.dtsi" =20 / { - model =3D "TQ Systems TQMa6ULL2L SoM"; + model =3D "TQ-Systems TQMa6ULL2L SoM"; compatible =3D "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; }; =20 --=20 2.43.0