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Fri, 20 Feb 2026 15:30:29 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] ARM: dts: imx6qdl-tqma6: add boot phase properties Date: Fri, 20 Feb 2026 15:30:04 +0100 Message-ID: <20260220143008.186851-4-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260220143008.186851-1-Max.Merchel@ew.tq-group.com> References: <20260220143008.186851-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay94-hz2.antispameurope.com with 4fHXj24CHgz3dG6N X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: c0a012c4c0204103e9d00e65e5abcb83 X-cloud-security: scantime:2.128 DKIM-Signature: a=rsa-sha256; bh=wqJgdoCqiOdzIhzrfhNSF/MhiuLEn1kACd6MHSSRwJY=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771597848; v=1; b=Mc0yz9QyjEqOArljLdHFmAxmMYGdjIDa7ZKNkpqIX2wwj5v0IvpbFn8lVEfRMAM2tAFNpUn7 QAoTDk+T9qYbVJ3H2hrBuxjnKKwGJE1kaHjl7PiIakQMnPGOmisr43dCG5x+wnB/mKt/ucZOzb0 hZSvqY1leiuImfNhjwDlTiBdSgA1UdouSh2uM72lphwqgZmmHEWRlAR4RlGXriCNRdEvthJxW8/ bIifXlhC5ux2XWy0TzOoVb5IWMuBIGrzxwga5Fvw95QJOXXQHgzay/lLmb0QMlbML2tCA9/jMRQ cImQLBhmnKjbqvdby26kdEzrqG3Hyyzyw5AuHucycKMoA== Content-Type: text/plain; charset="utf-8" dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. TQMa6 need eMMC, I2C, GPIO, regulator and QSPI access during boot process. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi | 11 +++++++++++ arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi | 2 ++ 3 files changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi b/arch/arm/boot/d= ts/nxp/imx/imx6qdl-tqma6.dtsi index 07492f63a1f8..14676d1d905a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi @@ -11,6 +11,7 @@ &ecspi1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_ecspi1>; cs-gpios =3D <&gpio3 19 GPIO_ACTIVE_LOW>; + bootph-pre-ram; status =3D "okay"; =20 m25p80: flash@0 { @@ -19,6 +20,7 @@ m25p80: flash@0 { spi-max-frequency =3D <50000000>; vcc-supply =3D <&sw4_reg>; m25p,fast-read; + bootph-pre-ram; =20 partitions { compatible =3D "fixed-partitions"; @@ -28,6 +30,10 @@ partitions { }; }; =20 +&gpio3 { + bootph-pre-ram; +}; + &iomuxc { pinctrl_ecspi1: ecspi1grp { fsl,pins =3D < @@ -38,6 +44,7 @@ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 /* eCSPI1 SS1 */ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 >; + bootph-pre-ram; }; =20 pinctrl_i2c1: i2c1grp { @@ -45,6 +52,7 @@ pinctrl_i2c1: i2c1grp { MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 >; + bootph-pre-ram; }; =20 pinctrl_i2c1_recovery: i2c1recoverygrp { @@ -73,6 +81,7 @@ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; + bootph-all; }; }; =20 @@ -117,6 +126,7 @@ sw4_reg: sw4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-pre-ram; }; =20 reg_5v_600mA: swbst { @@ -186,6 +196,7 @@ &usdhc3 { bus-width =3D <8>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 mmccard: mmccard@0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6qdl-tqma6a.dtsi index 1251749a8dd0..67f8f59aff5a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -20,6 +20,7 @@ &i2c1 { scl-gpios =3D <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency =3D <100000>; + bootph-pre-ram; status =3D "okay"; =20 pmic: pmic@8 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6qdl-tqma6b.dtsi index 7f526f39e0f2..db552802554d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -13,6 +13,7 @@ &i2c3 { scl-gpios =3D <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency =3D <100000>; + bootph-pre-ram; status =3D "okay"; =20 pmic: pmic@8 { @@ -40,6 +41,7 @@ pinctrl_i2c3: i2c3grp { MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 >; + bootph-pre-ram; }; =20 pinctrl_i2c3_recovery: i2c3recoverygrp { --=20 2.43.0