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Fri, 20 Feb 2026 15:30:29 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] ARM: dts: imx6qdl: add boot phase properties Date: Fri, 20 Feb 2026 15:30:03 +0100 Message-ID: <20260220143008.186851-3-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260220143008.186851-1-Max.Merchel@ew.tq-group.com> References: <20260220143008.186851-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay49-hz3.antispameurope.com with 4fHXj16dSwz3ybpL X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 3f64774df25daa84c68bb334c57fd5da X-cloud-security: scantime:1.961 DKIM-Signature: a=rsa-sha256; bh=DVSOsN1ks7VLJzQhKDw9Gx2RfSThw2ZZvzsniVKDgAc=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771597847; v=1; b=Q2NMjVBIMRXr8FB6m1s0ANSMNdX8rnl5QJ4H2+TP5uN9kEJTLU/enAwMItxjsqrSwD2pWmSo jBi7LptWUPd14sxn7EEJ0voAKI3sQ+Zo92hq/kzS4akblS3DbBiDsKLD7cqrIBvWxJ/D2wpRDHE TN1sWGKa+EJJp4bskIOkGIwuvyRrmGp5wLOqHP1OpbD0u2YA64VLg6Swjir8+eiDIQqv3wogO6a AnUareraAJLTdlSMR02d+80tuTX95cCMV3311yCctIvcRivvHrrDV29vg2vTRSCrBz1u8H1jRhh OVs1zRHHKuD2Z3OWHPbiI3C1dge+E3q0Z2aHY5EDqGCEg== Content-Type: text/plain; charset="utf-8" dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. All SoCs require buses (aips and spba), clock, iomuxc, ipu and SOC access during boot process. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp= /imx/imx6qdl.dtsi index 76e6043e1f91..1fcfe0751327 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -149,6 +149,7 @@ soc: soc { compatible =3D "simple-bus"; interrupt-parent =3D <&gpc>; ranges; + bootph-all; =20 dma_apbh: dma-controller@110000 { compatible =3D "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; @@ -297,6 +298,7 @@ aips1: bus@2000000 { /* AIPS1 */ #size-cells =3D <1>; reg =3D <0x02000000 0x100000>; ranges; + bootph-pre-ram; =20 spba-bus@2000000 { compatible =3D "fsl,spba-bus", "simple-bus"; @@ -304,6 +306,7 @@ spba-bus@2000000 { #size-cells =3D <1>; reg =3D <0x02000000 0x40000>; ranges; + bootph-pre-ram; =20 spdif: spdif@2004000 { compatible =3D "fsl,imx35-spdif"; @@ -920,6 +923,7 @@ mux: mux-controller { iomuxc: pinctrl@20e0000 { compatible =3D "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg =3D <0x20e0000 0x4000>; + bootph-pre-ram; }; =20 dcic1: dcic@20e4000 { @@ -950,6 +954,7 @@ aips2: bus@2100000 { /* AIPS2 */ #size-cells =3D <1>; reg =3D <0x02100000 0x100000>; ranges; + bootph-pre-ram; =20 crypto: crypto@2100000 { compatible =3D "fsl,sec-v4.0"; @@ -1320,6 +1325,7 @@ ipu1: ipu@2400000 { <&clks IMX6QDL_CLK_IPU1_DI1>; clock-names =3D "bus", "di0", "di1"; resets =3D <&src 2>; + bootph-all; =20 ipu1_csi0: port@0 { reg =3D <0>; --=20 2.43.0