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charset="utf-8" Refactor the platform driver probe function by extracting device setup and configuration logic into reusable helper functions: xadc_device_setup(): handles IIO device allocation and basic setup xadc_device_configure(): handles device tree parsing and bipolar mask configuration This refactoring reduces code duplication and prepares for sharing the common setup logic between platform and I2C drivers. Signed-off-by: Sai Krishna Potthuri --- drivers/iio/adc/xilinx-xadc-core.c | 60 +++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 18 deletions(-) diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xa= dc-core.c index e257c1b94a5f..52b51821007d 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -1310,6 +1310,44 @@ static void xadc_cancel_delayed_work(void *data) cancel_delayed_work_sync(work); } =20 +static struct iio_dev *xadc_device_setup(struct device *dev, int size, + const struct xadc_ops **ops) +{ + struct iio_dev *indio_dev; + + *ops =3D device_get_match_data(dev); + if (!*ops) + return ERR_PTR(-ENODEV); + + indio_dev =3D devm_iio_device_alloc(dev, size); + if (!indio_dev) + return ERR_PTR(-ENOMEM); + + indio_dev->name =3D xadc_type_names[(*ops)->type]; + indio_dev->info =3D &xadc_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + return indio_dev; +} + +static int xadc_device_configure(struct device *dev, struct iio_dev *indio= _dev, + int irq, unsigned int *conf0, unsigned int *bipolar_mask) +{ + int ret, i; + + ret =3D xadc_parse_dt(indio_dev, conf0, irq); + if (ret) + return ret; + + *bipolar_mask =3D 0; + for (i =3D 0; i < indio_dev->num_channels; i++) { + if (indio_dev->channels[i].scan_type.sign =3D=3D 's') + *bipolar_mask |=3D BIT(indio_dev->channels[i].scan_index); + } + + return 0; +} + static int xadc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1322,19 +1360,15 @@ static int xadc_probe(struct platform_device *pdev) int irq; int i; =20 - ops =3D device_get_match_data(dev); - if (!ops) - return -EINVAL; + indio_dev =3D xadc_device_setup(dev, sizeof(*xadc), &ops); + if (IS_ERR(indio_dev)) + return PTR_ERR(indio_dev); =20 irq =3D platform_get_irq_optional(pdev, 0); if (irq < 0 && (irq !=3D -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL))) return irq; =20 - indio_dev =3D devm_iio_device_alloc(dev, sizeof(*xadc)); - if (!indio_dev) - return -ENOMEM; - xadc =3D iio_priv(indio_dev); xadc->ops =3D ops; init_completion(&xadc->completion); @@ -1346,11 +1380,7 @@ static int xadc_probe(struct platform_device *pdev) if (IS_ERR(xadc->base)) return PTR_ERR(xadc->base); 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charset="utf-8" Add setup_channels function pointer to xadc_ops structure to enable different interfaces to have custom channel setup logic. Signed-off-by: Sai Krishna Potthuri --- drivers/iio/adc/xilinx-xadc-core.c | 8 +++++++- drivers/iio/adc/xilinx-xadc.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xa= dc-core.c index 52b51821007d..ee58b4a80f34 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -35,6 +35,8 @@ =20 #include "xilinx-xadc.h" =20 +static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, in= t irq); + static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT =3D 500; =20 /* ZYNQ register definitions */ @@ -455,6 +457,7 @@ static const struct xadc_ops xadc_zynq_ops =3D { .get_dclk_rate =3D xadc_zynq_get_dclk_rate, .interrupt_handler =3D xadc_zynq_interrupt_handler, .update_alarm =3D xadc_zynq_update_alarm, + .setup_channels =3D xadc_parse_dt, .type =3D XADC_TYPE_S7, /* Temp in C =3D (val * 503.975) / 2**bits - 273.15 */ .temp_scale =3D 503975, @@ -567,6 +570,7 @@ static const struct xadc_ops xadc_7s_axi_ops =3D { .get_dclk_rate =3D xadc_axi_get_dclk, .update_alarm =3D xadc_axi_update_alarm, .interrupt_handler =3D xadc_axi_interrupt_handler, + .setup_channels =3D xadc_parse_dt, .flags =3D XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL, .type =3D XADC_TYPE_S7, /* Temp in C =3D (val * 503.975) / 2**bits - 273.15 */ @@ -581,6 +585,7 @@ static const struct xadc_ops xadc_us_axi_ops =3D { .get_dclk_rate =3D xadc_axi_get_dclk, .update_alarm =3D xadc_axi_update_alarm, .interrupt_handler =3D xadc_axi_interrupt_handler, + .setup_channels =3D xadc_parse_dt, .flags =3D XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL, .type =3D XADC_TYPE_US, /** @@ -1333,9 +1338,10 @@ static struct iio_dev *xadc_device_setup(struct devi= ce *dev, int size, static int xadc_device_configure(struct device *dev, struct iio_dev *indio= _dev, int irq, unsigned int *conf0, unsigned int *bipolar_mask) { + struct xadc *xadc =3D iio_priv(indio_dev); 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charset="utf-8" Replace module_platform_driver() macro with custom init and exit functions to prepare for supporting multiple bus interfaces (platform + I2C). Signed-off-by: Sai Krishna Potthuri --- drivers/iio/adc/xilinx-xadc-core.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xa= dc-core.c index ee58b4a80f34..4ddc962e4926 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -1476,7 +1476,18 @@ static struct platform_driver xadc_driver =3D { .of_match_table =3D xadc_of_match_table, }, }; -module_platform_driver(xadc_driver); + +static int __init xadc_init(void) +{ + return platform_driver_register(&xadc_driver); +} +module_init(xadc_init); + +static void __exit xadc_exit(void) +{ + platform_driver_unregister(&xadc_driver); +} +module_exit(xadc_exit); =20 MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Lars-Peter Clausen "); --=20 2.25.1 From nobody Fri Apr 17 10:36:15 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012037.outbound.protection.outlook.com [52.101.53.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAAF032D0D3; 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Thu, 19 Feb 2026 23:40:15 -0600 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 19 Feb 2026 23:40:14 -0600 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Thu, 19 Feb 2026 23:40:11 -0600 From: Sai Krishna Potthuri To: Jonathan Cameron , David Lechner , Nuno Sa , Andy Shevchenko , Michal Simek , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , Sai Krishna Potthuri Subject: [PATCH 4/5] iio: adc: xilinx-xadc: Add I2C interface support Date: Fri, 20 Feb 2026 11:09:40 +0530 Message-ID: <20260220053941.611415-5-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260220053941.611415-1-sai.krishna.potthuri@amd.com> References: <20260220053941.611415-1-sai.krishna.potthuri@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D5:EE_|PH7PR12MB6718:EE_ X-MS-Office365-Filtering-Correlation-Id: f7200a68-352a-4ad3-c78c-08de70428860 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024; 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charset="utf-8" Add I2C interface support for Xilinx System Management Wizard IP along with the existing AXI memory-mapped interface. This support enables monitoring the voltage and temperature on UltraScale+ devices where the System Management Wizard is connected via I2C. Key changes: - Implement 32-bit DRP(Dynamic Reconfiguration Port) packet format as per Xilinx PG185 specification. - Add separate I2C probe with xadc_i2c_of_match_table to handle same compatible string("xlnx,system-management-wiz-1.3") on I2C bus. - Implement delayed version of hardware initialization for I2C interface to handle the case where System Management Wizard IP is not ready during the I2C probe. - Add xadc_i2c_transaction() function to handle I2C read/write operations - Add XADC_TYPE_US_I2C type to distinguish I2C interface from AXI. Signed-off-by: Sai Krishna Potthuri --- drivers/iio/adc/Kconfig | 11 ++ drivers/iio/adc/xilinx-xadc-core.c | 206 ++++++++++++++++++++++++++++- drivers/iio/adc/xilinx-xadc.h | 7 + 3 files changed, 221 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 60038ae8dfc4..0c0adac151e4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1951,6 +1951,17 @@ config XILINX_XADC The driver can also be build as a module. If so, the module will be cal= led xilinx-xadc. =20 +config XILINX_XADC_I2C + bool "Xilinx System Management Wizard I2C Interface support" + depends on XILINX_XADC && I2C + help + Say yes here to allow accessing the System Management + Wizard on UltraScale+ devices via I2C. + + This provides voltage and temperature monitoring capabilities + through the same IIO sysfs interface, but using I2C communication + protocol. + config XILINX_AMS tristate "Xilinx AMS driver" depends on ARCH_ZYNQMP || COMPILE_TEST diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xa= dc-core.c index 4ddc962e4926..7644267092ef 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -11,9 +11,12 @@ * - AXI XADC interface: Xilinx PG019 */ =20 +#include +#include #include #include #include +#include #include #include #include @@ -35,6 +38,22 @@ =20 #include "xilinx-xadc.h" =20 +#ifdef CONFIG_XILINX_XADC_I2C +#define XADC_I2C_READ_DATA_SIZE 2 +#define XADC_I2C_WRITE_DATA_SIZE 4 /* 32-bit DRP packet */ +#define XADC_I2C_INSTR_READ BIT(2) +#define XADC_I2C_INSTR_WRITE BIT(3) + +#define XADC_I2C_DRP_DATA0_MASK GENMASK(7, 0) +#define XADC_I2C_DRP_DATA1_MASK GENMASK(15, 8) +#define XADC_I2C_DRP_ADDR_MASK GENMASK(7, 0) + +struct xadc_i2c { + struct xadc xadc; + struct i2c_client *client; +}; +#endif /* CONFIG_XILINX_XADC_I2C */ + static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, in= t irq); =20 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT =3D 500; @@ -596,6 +615,108 @@ static const struct xadc_ops xadc_us_axi_ops =3D { .temp_offset =3D 280231, }; =20 +#ifdef CONFIG_XILINX_XADC_I2C +static int xadc_i2c_transaction(struct xadc *xadc, unsigned int reg, uint1= 6_t write_data, + bool is_write, uint16_t *read_data) +{ + struct xadc_i2c *xadc_i2c =3D container_of(xadc, struct xadc_i2c, xadc); + struct i2c_client *client =3D xadc_i2c->client; + char read_buffer[XADC_I2C_READ_DATA_SIZE]; + char write_buffer[XADC_I2C_WRITE_DATA_SIZE] =3D { 0 }; + int ret; + + if (is_write) { + write_buffer[0] =3D FIELD_GET(XADC_I2C_DRP_DATA0_MASK, write_data); + write_buffer[1] =3D FIELD_GET(XADC_I2C_DRP_DATA1_MASK, write_data); + write_buffer[2] =3D FIELD_GET(XADC_I2C_DRP_ADDR_MASK, reg); + write_buffer[3] =3D XADC_I2C_INSTR_WRITE; + } else { + write_buffer[2] =3D FIELD_GET(XADC_I2C_DRP_ADDR_MASK, reg); + write_buffer[3] =3D XADC_I2C_INSTR_READ; + } + + ret =3D i2c_master_send(client, write_buffer, XADC_I2C_WRITE_DATA_SIZE); + if (ret < 0) + return ret; + + /* Read response for read operations */ + if (!is_write) { + ret =3D i2c_master_recv(client, read_buffer, XADC_I2C_READ_DATA_SIZE); + if (ret < 0) + return ret; + + *read_data =3D FIELD_PREP(XADC_I2C_DRP_DATA0_MASK, read_buffer[0]) | + FIELD_PREP(XADC_I2C_DRP_DATA1_MASK, read_buffer[1]); + } + + return 0; +} + +static int xadc_hardware_init(struct xadc *xadc) +{ + int ret, i; + + for (i =3D 0; i < 16; i++) { + ret =3D xadc_i2c_transaction(xadc, XADC_REG_THRESHOLD(i), 0, false, + &xadc->threshold[i]); + if (ret) + return ret; + } + + ret =3D xadc_i2c_transaction(xadc, XADC_REG_CONF0, xadc->conf0, true, NUL= L); + if (ret) + return ret; + + ret =3D xadc_i2c_transaction(xadc, XADC_REG_INPUT_MODE(0), xadc->bipolar_= mask, true, NULL); + if (ret) + return ret; + + ret =3D xadc_i2c_transaction(xadc, XADC_REG_INPUT_MODE(1), xadc->bipolar_= mask >> 16, true, + NULL); + if (ret) + return ret; + + xadc->hw_initialized =3D true; + + return 0; +} + +static int xadc_i2c_read_reg(struct xadc *xadc, unsigned int reg, uint16_t= *val) +{ + if (!xadc->hw_initialized) { + int ret; + + ret =3D xadc_hardware_init(xadc); + if (ret) + return ret; + } + + return xadc_i2c_transaction(xadc, reg, 0, false, val); +} + +static int xadc_i2c_write_reg(struct xadc *xadc, unsigned int reg, uint16_= t val) +{ + if (!xadc->hw_initialized) { + int ret; + + ret =3D xadc_hardware_init(xadc); + if (ret) + return ret; + } + + return xadc_i2c_transaction(xadc, reg, val, true, NULL); +} + +static const struct xadc_ops xadc_system_mgmt_wiz_i2c_ops =3D { + .read =3D xadc_i2c_read_reg, + .write =3D xadc_i2c_write_reg, + .setup_channels =3D xadc_parse_dt, + .type =3D XADC_TYPE_US_I2C, + .temp_scale =3D 509314, + .temp_offset =3D 280231, +}; +#endif /* CONFIG_XILINX_XADC_I2C */ + static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, uint16_t mask, uint16_t val) { @@ -782,7 +903,8 @@ static int xadc_power_adc_b(struct xadc *xadc, unsigned= int seq_mode) * non-existing ADC-B powers down the main ADC, so just return and don't * do anything. */ - if (xadc->ops->type =3D=3D XADC_TYPE_US) + if (xadc->ops->type =3D=3D XADC_TYPE_US || + xadc->ops->type =3D=3D XADC_TYPE_US_I2C) return 0; =20 /* Powerdown the ADC-B when it is not needed. */ @@ -805,7 +927,8 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigne= d long scan_mode) unsigned int aux_scan_mode =3D scan_mode >> 16; =20 /* UltraScale has only one ADC and supports only continuous mode */ - if (xadc->ops->type =3D=3D XADC_TYPE_US) + if (xadc->ops->type =3D=3D XADC_TYPE_US || + xadc->ops->type =3D=3D XADC_TYPE_US_I2C) return XADC_CONF1_SEQ_CONTINUOUS; =20 if (xadc->external_mux_mode =3D=3D XADC_EXTERNAL_MUX_DUAL) @@ -1306,6 +1429,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, u= nsigned int *conf, int irq) static const char * const xadc_type_names[] =3D { [XADC_TYPE_S7] =3D "xadc", [XADC_TYPE_US] =3D "xilinx-system-monitor", + [XADC_TYPE_US_I2C] =3D "xilinx-system-monitor", }; =20 static void xadc_cancel_delayed_work(void *data) @@ -1469,6 +1593,65 @@ static int xadc_probe(struct platform_device *pdev) return devm_iio_device_register(dev, indio_dev); } =20 +#ifdef CONFIG_XILINX_XADC_I2C +static int xadc_i2c_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + unsigned int conf0, bipolar_mask; + const struct xadc_ops *ops; + struct iio_dev *indio_dev; + struct xadc_i2c *xadc_i2c; + struct xadc *xadc; + int ret; + + indio_dev =3D xadc_device_setup(dev, sizeof(*xadc_i2c), &ops); + if (IS_ERR(indio_dev)) + return PTR_ERR(indio_dev); + + xadc_i2c =3D iio_priv(indio_dev); + xadc_i2c->client =3D client; + xadc =3D &xadc_i2c->xadc; + xadc->clk =3D NULL; + xadc->ops =3D ops; + mutex_init(&xadc->mutex); + spin_lock_init(&xadc->lock); + + indio_dev->name =3D xadc_type_names[xadc->ops->type]; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->info =3D &xadc_info; + + ret =3D xadc_device_configure(dev, indio_dev, 0, &conf0, &bipolar_mask); + if (ret) { + dev_err(dev, "Failed to setup the device: %d\n", ret); + return ret; + } + + i2c_set_clientdata(client, indio_dev); + xadc->conf0 =3D conf0; + xadc->bipolar_mask =3D bipolar_mask; + xadc->hw_initialized =3D false; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id xadc_i2c_of_match_table[] =3D { + { + .compatible =3D "xlnx,system-management-wiz-1.3", + .data =3D &xadc_system_mgmt_wiz_i2c_ops + }, + { }, +}; +MODULE_DEVICE_TABLE(of, xadc_i2c_of_match_table); + +static struct i2c_driver xadc_i2c_driver =3D { + .probe =3D xadc_i2c_probe, + .driver =3D { + .name =3D "xadc-i2c", + .of_match_table =3D xadc_i2c_of_match_table, + }, +}; +#endif /* CONFIG_XILINX_XADC_I2C */ + static struct platform_driver xadc_driver =3D { .probe =3D xadc_probe, .driver =3D { @@ -1479,12 +1662,29 @@ static struct platform_driver xadc_driver =3D { =20 static int __init xadc_init(void) { - return platform_driver_register(&xadc_driver); + int ret; + + ret =3D platform_driver_register(&xadc_driver); + if (ret) + return ret; + +#ifdef CONFIG_XILINX_XADC_I2C + ret =3D i2c_add_driver(&xadc_i2c_driver); + if (ret) { + platform_driver_unregister(&xadc_driver); + return ret; + } +#endif + + return 0; } module_init(xadc_init); =20 static void __exit xadc_exit(void) { +#ifdef CONFIG_XILINX_XADC_I2C + i2c_del_driver(&xadc_i2c_driver); +#endif platform_driver_unregister(&xadc_driver); } module_exit(xadc_exit); diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h index 26cd65153176..4bcafd419df2 100644 --- a/drivers/iio/adc/xilinx-xadc.h +++ b/drivers/iio/adc/xilinx-xadc.h @@ -63,6 +63,12 @@ struct xadc { unsigned int zynq_intmask; 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charset="utf-8" Convert the xilinx-xadc.txt Devicetree binding to a YAML schema format and remove the old text binding. Signed-off-by: Sai Krishna Potthuri --- .../bindings/iio/adc/xilinx-xadc.txt | 141 ------------- .../bindings/iio/adc/xilinx-xadc.yaml | 194 ++++++++++++++++++ 2 files changed, 194 insertions(+), 141 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.t= xt create mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.y= aml diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Do= cumentation/devicetree/bindings/iio/adc/xilinx-xadc.txt deleted file mode 100644 index f42e18078376..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt +++ /dev/null @@ -1,141 +0,0 @@ -Xilinx XADC device driver - -This binding document describes the bindings for the Xilinx 7 Series XADC = as well -as the UltraScale/UltraScale+ System Monitor. - -The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xil= inx. -The XADC has a DRP interface for communication. Currently two different -frontends for the DRP interface exist. One that is only available on the Z= YNQ -family as a hardmacro in the SoC portion of the ZYNQ. The other one is ava= ilable -on all series 7 platforms and is a softmacro with a AXI interface. This bi= nding -document describes the bindings for both of them since the bindings are ve= ry -similar. - -The Xilinx System Monitor is an ADC that is found in the UltraScale and -UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface= for -communication. Xilinx provides a standard IP core that can be used to acce= ss the -System Monitor through an AXI interface in the FPGA fabric. This IP core is -called the Xilinx System Management Wizard. This document describes the bi= ndings -for this IP. - -Required properties: - - compatible: Should be one of - * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device - configuration interface to interface to the XADC hardmacro. - * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to - interface to the XADC hardmacro. - * "xlnx,system-management-wiz-1.3": When using the - Xilinx System Management Wizard fabric IP core to access the - UltraScale and UltraScale+ System Monitor. - - reg: Address and length of the register set for the device - - interrupts: Interrupt for the XADC control interface. - - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, - when using the axi-xadc or the axi-system-management-wizard this must be - the clock that provides the clock to the AXI bus interface of the core. - -Optional properties: - - xlnx,external-mux: - * "none": No external multiplexer is used, this is the default - if the property is omitted. - * "single": External multiplexer mode is used with one - multiplexer. - * "dual": External multiplexer mode is used with two - multiplexers for simultaneous sampling. - - xlnx,external-mux-channel: Configures which pair of pins is used to - sample data in external mux mode. - Valid values for single external multiplexer mode are: - 0: VP/VN - 1: VAUXP[0]/VAUXN[0] - 2: VAUXP[1]/VAUXN[1] - ... - 16: VAUXP[15]/VAUXN[15] - Valid values for dual external multiplexer mode are: - 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8] - 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9] - ... - 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15] - - This property needs to be present if the device is configured for - external multiplexer mode (either single or dual). If the device is - not using external multiplexer mode the property is ignored. - - xnlx,channels: List of external channels that are connected to the ADC - Required properties: - * #address-cells: Should be 1. - * #size-cells: Should be 0. - - The child nodes of this node represent the external channels which are - connected to the ADC. If the property is no present no external - channels will be assumed to be connected. - - Each child node represents one channel and has the following - properties: - Required properties: - * reg: Pair of pins the channel is connected to. - 0: VP/VN - 1: VAUXP[0]/VAUXN[0] - 2: VAUXP[1]/VAUXN[1] - ... - 16: VAUXP[15]/VAUXN[15] - Note each channel number should only be used at most - once. - Optional properties: - * xlnx,bipolar: If set the channel is used in bipolar - mode. - - -Examples: - xadc@f8007100 { - compatible =3D "xlnx,zynq-xadc-1.00.a"; - reg =3D <0xf8007100 0x20>; - interrupts =3D <0 7 4>; - interrupt-parent =3D <&gic>; - clocks =3D <&pcap_clk>; - - xlnx,channels { - #address-cells =3D <1>; - #size-cells =3D <0>; - channel@0 { - reg =3D <0>; - }; - channel@1 { - reg =3D <1>; - }; - channel@8 { - reg =3D <8>; - }; - }; - }; - - xadc@43200000 { - compatible =3D "xlnx,axi-xadc-1.00.a"; - reg =3D <0x43200000 0x1000>; - interrupts =3D <0 53 4>; - interrupt-parent =3D <&gic>; - clocks =3D <&fpga1_clk>; - - xlnx,channels { - #address-cells =3D <1>; - #size-cells =3D <0>; - channel@0 { - reg =3D <0>; - xlnx,bipolar; - }; - }; - }; - - adc@80000000 { - compatible =3D "xlnx,system-management-wiz-1.3"; - reg =3D <0x80000000 0x1000>; - interrupts =3D <0 81 4>; - interrupt-parent =3D <&gic>; - clocks =3D <&fpga1_clk>; - - xlnx,channels { - #address-cells =3D <1>; - #size-cells =3D <0>; - channel@0 { - reg =3D <0>; - xlnx,bipolar; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml b/D= ocumentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml new file mode 100644 index 000000000000..17508fef1f43 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/xilinx-xadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XADC and System Monitor ADC + +description: + The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from X= ilinx. + The XADC has a DRP interface for communication. Currently two different + frontends for the DRP interface exist. One that is only available on the= ZYNQ + family as a hardmacro in the SoC portion of the ZYNQ. The other one is a= vailable + on all series 7 platforms and is a softmacro with an AXI interface. + + The Xilinx System Monitor is an ADC that is found in the UltraScale and + UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interfa= ce for + communication. Xilinx provides a standard IP core that can be used to ac= cess the + System Monitor through an AXI interface in the FPGA fabric. This IP core= is + called the Xilinx System Management Wizard. + + The System Management Wizard can also be accessed via I2C interface for = remote + monitoring scenarios where the system Management Wizard is located on a = different chip. + +maintainers: + - Lars-Peter Clausen + - Sai Krishna Potthuri + +properties: + compatible: + enum: + - xlnx,zynq-xadc-1.00.a + - xlnx,axi-xadc-1.00.a + - xlnx,system-management-wiz-1.3 + - xlnx,system-management-wiz-1.3-remote + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + When using the ZYNQ this must be the ZYNQ PCAP clock, + when using the axi-xadc or the axi-system-management-wizard this mus= t be + the clock that provides the clock to the AXI bus interface of the co= re. + + xlnx,external-mux: + $ref: /schemas/types.yaml#/definitions/string + enum: + - none + - single + - dual + default: none + description: | + External multiplexer configuration: + - "none": No external multiplexer is used (default) + - "single": External multiplexer mode is used with one multiplexer + - "dual": External multiplexer mode is used with two multiplexers + for simultaneous sampling + + xlnx,external-mux-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 16 + description: | + Configures which pair of pins is used to sample data in external mux= mode. + Valid values for single external multiplexer mode are 0-16: + 0: VP/VN + 1-16: VAUXP[0-15]/VAUXN[0-15] + Valid values for dual external multiplexer mode are 1-8: + 1-8: VAUXP[0-7]/VAUXN[0-7] - VAUXP[8-15]/VAUXN[8-15] + This property needs to be present if the device is configured for + external multiplexer mode (either single or dual). + + xlnx,channels: + $ref: '#/$defs/channels' + +allOf: + - if: + required: + - xlnx,external-mux + properties: + xlnx,external-mux: + enum: + - single + - dual + then: + required: + - xlnx,external-mux-channel + +required: + - compatible + - reg + +unevaluatedProperties: false + +$defs: + channels: + type: object + description: List of external channels that are connected to the ADC + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^channel@([0-9]|1[0-6])$": + type: object + properties: + reg: + minimum: 0 + maximum: 16 + description: | + Pair of pins the channel is connected to: + 0: VP/VN + 1-16: VAUXP[0-15]/VAUXN[0-15] + Note each channel number should only be used at most once. + + xlnx,bipolar: + type: boolean + description: If set, the channel is used in bipolar mode + + required: + - reg + + unevaluatedProperties: false + + required: + - '#address-cells' + - '#size-cells' + + unevaluatedProperties: false + +examples: + - | + #include + xadc@f8007100 { + compatible =3D "xlnx,zynq-xadc-1.00.a"; + reg =3D <0xf8007100 0x20>; + interrupts =3D <0 7 4>; + clocks =3D <&pcap_clk>; + + xlnx,channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + }; + channel@1 { + reg =3D <1>; + }; + channel@8 { + reg =3D <8>; + }; + }; + }; + + - | + xadc@43200000 { + compatible =3D "xlnx,axi-xadc-1.00.a"; + reg =3D <0x43200000 0x1000>; + interrupts =3D <0 53 4>; + clocks =3D <&fpga1_clk>; + + xlnx,channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + xlnx,bipolar; + }; + }; + }; + + - | + adc@80000000 { + compatible =3D "xlnx,system-management-wiz-1.3"; + reg =3D <0x80000000 0x1000>; + interrupts =3D <0 81 4>; + clocks =3D <&fpga1_clk>; + + xlnx,channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + xlnx,bipolar; + }; + }; + }; --=20 2.25.1