From nobody Fri Apr 3 12:33:14 2026 Received: from srv01.abscue.de (abscue.de [89.58.28.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B5B53090DE; Fri, 20 Feb 2026 17:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.28.240 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771607540; cv=none; b=KgAq8wWXrOrjKa2uTEk8SrlmZe3uP9BXEc4DWErYjDJELFn7dM/BgwYFtrGJpEOPKiIqEKRYDBbyIu/ChVYF/AkDHHkttIiZOtHcagOi1ZhW7zfuQg7foR4yhGG6A3CjH/OcJU4nBTf9mQkZL59r0/YcpkNBQP4xuhOZh84mQeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771607540; c=relaxed/simple; bh=l9n78PrlERskAAFtJC7dsJynepAFJSeSY6cGQYixgEg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Iuy7V/cg3RAwpYSpQIe877+LT+/9q6HJiBLFXJcNO8nu1XQEX2CCMYeBT8lcgMQHIZWM/Q6v9lpNTlu6wclPNey5btJH0uB/4mVv/MgP8OvZuTrL75BFievZ1ajpVFVFGrZTDVBCVdeyAlgLgt5ej+3xfJ/EHwFHTAGl8riZFfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de; spf=pass smtp.mailfrom=abscue.de; dkim=fail (0-bit key) header.d=abscue.de header.i=@abscue.de header.b=sBohaxPk reason="key not found in DNS"; arc=none smtp.client-ip=89.58.28.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=abscue.de Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=abscue.de header.i=@abscue.de header.b="sBohaxPk" Received: from fluffy-mammal.metal.fwg-cag.de (unknown [IPv6:2001:9e8:cdd4:c900:fc49:439e:37d7:68d]) by srv01.abscue.de (Postfix) with ESMTPSA id 1EF591C6E34; Fri, 20 Feb 2026 18:02:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=abscue.de; s=dkim; t=1771606965; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1Q2EbxLqZZlsx/ThvrFIhnR879lhgdAno9gLbL4IBbk=; b=sBohaxPkjmNVvRxFQ6wDH6Bvrww9ubw4wQnLSVmS6HjJfgleBoQH3l5EQHXtU7evAn9PKt DSjQDaZxfQKP0F/ugl3vs9NhnrV4vwp7XGeeb7UOe1VI8iESCtprKR35VdL1S7+DJyakK4 o3FcOPyAW2ntaDIZITuZJHdJEQtM8ax52ynvyBJbaSpirxn1rjEv2oWK00PLOyuYAwAYBZ gAFdwAUQqpFJ3iEnAQxf/AZhElFZsfQ8/Sg8NEtmpNXFchtvrCJGwl1CjYz/TzUvHlJK/9 mpGbkINALWX8hFzJXdUgiRpLSBIbW1tFktSxMZ14InBPC21IAyDG+LAYBQkb9A== From: =?utf-8?q?Otto_Pfl=C3=BCger?= Date: Fri, 20 Feb 2026 18:01:49 +0100 Subject: [PATCH 1/3] dt-bindings: regulator: Document Unisoc SC2730 PMIC bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-sc2730-regulators-v1-1-3f2bbc9ecf14@abscue.de> References: <20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de> In-Reply-To: <20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Lee Jones Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.3 Add bindings for the regulators found in the Spreadtrum/Unisoc SC2730 PMIC, used e.g. with the UMS512 and UMS9230 SoCs. Signed-off-by: Otto Pfl=C3=BCger --- .../bindings/regulator/sprd,sc2730-regulator.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2730-regula= tor.yaml b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulato= r.yaml new file mode 100644 index 000000000000..36f5f4d338bb --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/sprd,sc2730-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc SC2730 Power Management IC regulators + +maintainers: + - Otto Pfl=C3=BCger + +properties: + compatible: + const: sprd,sc2730-regulator + +patternProperties: + "^DCDC_(CORE|CPU|GEN[0-1]|GPU|MEM|MEMQ|MODEM|SRAM)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^LDO_AVDD(12|18)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^LDO_VDD(18_DCXO|28)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^LDO_VDD(EMMCCORE|KPLED|LDO[0-2]|SD(CORE|IO)|SIM[0-2]|USB33|WCN|WIFIPA)= $": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^LDO_VDDCAM(A0|A1|D0|D1|IO|MOT)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^LDO_VDDRF(1V25|18)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false +... --=20 2.51.0 From nobody Fri Apr 3 12:33:14 2026 Received: from srv01.abscue.de (abscue.de [89.58.28.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B5302F3C26; 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arc=none smtp.client-ip=89.58.28.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=abscue.de Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=abscue.de header.i=@abscue.de header.b="qIw1Khu5" Received: from fluffy-mammal.metal.fwg-cag.de (unknown [IPv6:2001:9e8:cdd4:c900:fc49:439e:37d7:68d]) by srv01.abscue.de (Postfix) with ESMTPSA id ADB031C6E35; Fri, 20 Feb 2026 18:02:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=abscue.de; s=dkim; t=1771606971; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pkowgPBRpxCHbF2C7DNbg/lISjQnMGiRDK9RgEjUL2I=; b=qIw1Khu5k032UtguxtAs139L0XU26gr0U0wDe/KnGxL2daVYvgRbekVLZZuDFbPyNFqhOS YUkv5id1ftXVzpTUsHRZ8yeMi9QS+OnTbUeiNfMVeLIaMvxa7abPyY1gLHUQyZV+nU7xEQ KH5rpfgmSCkiXvDKUDQugCb2mwQ0G12a21t4ldTIRbhTT+orJ0PRFmD/my2rhwl7ZYvzab znUElfXmEnTipqnyoOUJjux7iSxzdoOPw/se8M4XegTv8S7jWayFyuQB4AI9icOEU+SvO7 1MyDR1GjdBRISFbCBbsP5b5QxZDI+dTesKEluFINOylxkadZVo+SgUiIRoMLJA== From: =?utf-8?q?Otto_Pfl=C3=BCger?= Date: Fri, 20 Feb 2026 18:01:50 +0100 Subject: [PATCH 2/3] dt-bindings: mfd: sprd,sc2731: Reference sprd,sc2730-regulator bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-sc2730-regulators-v1-2-3f2bbc9ecf14@abscue.de> References: <20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de> In-Reply-To: <20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Lee Jones Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.3 The SC2730 PMIC provides a different set of regulators than SC2731 and thus requires separate regulator bindings. Determine which bindings to include based on the compatible string of the PMIC. Signed-off-by: Otto Pfl=C3=BCger --- Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml b/Docum= entation/devicetree/bindings/mfd/sprd,sc2731.yaml index b023e1ef8d3c..e4ebb511bba1 100644 --- a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml +++ b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml @@ -99,6 +99,19 @@ required: - '#interrupt-cells' - '#size-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - sprd,sc2730 + then: + properties: + regulators: + type: object + $ref: /schemas/regulator/sprd,sc2730-regulator.yaml# + additionalProperties: false =20 examples: --=20 2.51.0 From nobody Fri Apr 3 12:33:14 2026 Received: from srv01.abscue.de (abscue.de [89.58.28.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA342877E5; Fri, 20 Feb 2026 17:02:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.28.240 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771606982; cv=none; b=H4Vs+0GTwLcYH9gVFmFzCv8D1ikFnw0oxQaGOvAvMqLkNeL1d/xpivU9IN0S1dqyr6X8rfgmtPRioK0U4hu9M8EHNWRGOI8pKGWdCWLl9K9qTq+dVvhQvY8xzCgBfSgYqAA6SorOzMToKF1LdjynE+PgDGzisZ9v+gYIYtLr5AM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771606982; c=relaxed/simple; bh=0rT549WSrOcLYAWVJP+BkJWstwlSqRlnLVQXweeAv3s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ta2ligO5yWTjnxkB7mX/XsamkGUz5dVv3A2G2DBHzS8JooRP4tzrEegXqzvMtOEa12ayucoZJzks0wv98U+ojnCaRYBQUU0hg4v0rNmVe2npF4ZpLACab9VWitPmxhtc6o6YruZcZm+xp2a4S74waJbmvu/3KGcgULLxegcYK1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de; spf=pass smtp.mailfrom=abscue.de; dkim=fail (0-bit key) header.d=abscue.de header.i=@abscue.de header.b=Qiw9U8vL reason="key not found in DNS"; arc=none smtp.client-ip=89.58.28.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=abscue.de Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=abscue.de header.i=@abscue.de header.b="Qiw9U8vL" Received: from fluffy-mammal.metal.fwg-cag.de (unknown [IPv6:2001:9e8:cdd4:c900:fc49:439e:37d7:68d]) by srv01.abscue.de (Postfix) with ESMTPSA id 72AD11C6E36; Fri, 20 Feb 2026 18:02:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=abscue.de; s=dkim; t=1771606971; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BOzGRoSQiT1vhjp3OLJxqASttU93FiHBpeELMAYCHWM=; b=Qiw9U8vLhphEs3EPG2eOwwVSFH2gKjlSMRAMbI4iy+i0X5D2j94tKyDbtHspEc15gLFpxe yMSRcbCkaoXFJMJmMxXpPgyR5+zpHZ4uinAMTwclseMhg3c1HCAK+0i6aWMUcp3u7seN2A zokfozeMe61JLL+BQ6640n+7GE64UMNpv/RktEUm3kjFc9kI6wir72+GqFinPQLJAGAOK3 nX5fOoCytWFdu7KrcYCbhOAtI6uqeQiUdQFa66v7N5oZtPZ1YDUFRzJ3Y/ZjBgj3k1/9fa evvwBV6uhTFFRDx8rbwXM0+Ijz7HemtmZTakIf8GLTxe7wGIaC22pTL2DpZtJw== From: =?utf-8?q?Otto_Pfl=C3=BCger?= Date: Fri, 20 Feb 2026 18:01:51 +0100 Subject: [PATCH 3/3] regulator: Add regulator driver for Unisoc SC2730 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-sc2730-regulators-v1-3-3f2bbc9ecf14@abscue.de> References: <20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de> In-Reply-To: <20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Lee Jones Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.3 Add a regulator driver for the Spreadtrum/Unisoc SC2730 PMIC, used e.g. with the UMS512 and UMS9230 SoCs. This version of the driver is based on a downstream driver provided by Unisoc [1] and the existing SC2731 driver. Signed-off-by: Otto Pfl=C3=BCger [1]: https://github.com/MotorolaMobilityLLC/kernel-sprd/blob/android-13-rel= ease-tla33/drivers/regulator/sc2730-regulator.c --- drivers/regulator/Kconfig | 7 + drivers/regulator/Makefile | 1 + drivers/regulator/sc2730-regulator.c | 419 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 427 insertions(+) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index a708fc63f581..d152d4f7995d 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1484,6 +1484,13 @@ config REGULATOR_S5M8767 via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and supports DVS mode with 8bits of output voltage control. =20 +config REGULATOR_SC2730 + tristate "Spreadtrum SC2730 power regulator driver" + depends on MFD_SC27XX_PMIC || COMPILE_TEST + help + This driver provides support for the voltage regulators on the + SC2730 PMIC. + config REGULATOR_SC2731 tristate "Spreadtrum SC2731 power regulator driver" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 35639f3115fd..9de6f1347d14 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -171,6 +171,7 @@ obj-$(CONFIG_REGULATOR_S2DOS05) +=3D s2dos05-regulator.o obj-$(CONFIG_REGULATOR_S2MPA01) +=3D s2mpa01.o obj-$(CONFIG_REGULATOR_S2MPS11) +=3D s2mps11.o obj-$(CONFIG_REGULATOR_S5M8767) +=3D s5m8767.o +obj-$(CONFIG_REGULATOR_SC2730) +=3D sc2730-regulator.o obj-$(CONFIG_REGULATOR_SC2731) +=3D sc2731-regulator.o obj-$(CONFIG_REGULATOR_SKY81452) +=3D sky81452-regulator.o obj-$(CONFIG_REGULATOR_SLG51000) +=3D slg51000-regulator.o diff --git a/drivers/regulator/sc2730-regulator.c b/drivers/regulator/sc273= 0-regulator.c new file mode 100644 index 000000000000..b1f34fe67dc9 --- /dev/null +++ b/drivers/regulator/sc2730-regulator.c @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Spreadtrum Communications Inc. + */ + +#include +#include +#include +#include +#include +#include + +/* + * SC2730 regulator base address + */ +#define SC2730_REGULATOR_BASE 0x1800 + +/* + * SC2730 regulator lock register + */ +#define SC2730_WR_UNLOCK_VALUE 0x6e7f +#define SC2730_PWR_WR_PROT (SC2730_REGULATOR_BASE + 0x3d0) + +/* + * SC2730 enable register + */ +#define SC2730_POWER_PD_SW (SC2730_REGULATOR_BASE + 0x01c) +#define SC2730_LDO_VDDRF18_PD (SC2730_REGULATOR_BASE + 0x10c) +#define SC2730_LDO_VDDCAMIO_PD (SC2730_REGULATOR_BASE + 0x118) +#define SC2730_LDO_VDDWCN_PD (SC2730_REGULATOR_BASE + 0x11c) +#define SC2730_LDO_VDDCAMD1_PD (SC2730_REGULATOR_BASE + 0x128) +#define SC2730_LDO_VDDCAMD0_PD (SC2730_REGULATOR_BASE + 0x134) +#define SC2730_LDO_VDDRF1V25_PD (SC2730_REGULATOR_BASE + 0x140) +#define SC2730_LDO_AVDD12_PD (SC2730_REGULATOR_BASE + 0x14c) +#define SC2730_LDO_VDDCAMA0_PD (SC2730_REGULATOR_BASE + 0x158) +#define SC2730_LDO_VDDCAMA1_PD (SC2730_REGULATOR_BASE + 0x164) +#define SC2730_LDO_VDDCAMMOT_PD (SC2730_REGULATOR_BASE + 0x170) +#define SC2730_LDO_VDDSIM2_PD (SC2730_REGULATOR_BASE + 0x194) +#define SC2730_LDO_VDDEMMCCORE_PD (SC2730_REGULATOR_BASE + 0x1a0) +#define SC2730_LDO_VDDSDCORE_PD (SC2730_REGULATOR_BASE + 0x1ac) +#define SC2730_LDO_VDDSDIO_PD (SC2730_REGULATOR_BASE + 0x1b8) +#define SC2730_LDO_VDDWIFIPA_PD (SC2730_REGULATOR_BASE + 0x1d0) +#define SC2730_LDO_VDDUSB33_PD (SC2730_REGULATOR_BASE + 0x1e8) +#define SC2730_LDO_VDDLDO0_PD (SC2730_REGULATOR_BASE + 0x1f4) +#define SC2730_LDO_VDDLDO1_PD (SC2730_REGULATOR_BASE + 0x200) +#define SC2730_LDO_VDDLDO2_PD (SC2730_REGULATOR_BASE + 0x20c) +#define SC2730_LDO_VDDKPLED_PD (SC2730_REGULATOR_BASE + 0x38c) + +/* + * SC2730 enable mask + */ +#define SC2730_DCDC_CPU_PD_MASK BIT(4) +#define SC2730_DCDC_GPU_PD_MASK BIT(3) +#define SC2730_DCDC_CORE_PD_MASK BIT(5) +#define SC2730_DCDC_MODEM_PD_MASK BIT(11) +#define SC2730_DCDC_MEM_PD_MASK BIT(6) +#define SC2730_DCDC_MEMQ_PD_MASK BIT(12) +#define SC2730_DCDC_GEN0_PD_MASK BIT(8) +#define SC2730_DCDC_GEN1_PD_MASK BIT(7) +#define SC2730_DCDC_SRAM_PD_MASK BIT(13) +#define SC2730_LDO_AVDD18_PD_MASK BIT(2) +#define SC2730_LDO_VDDRF18_PD_MASK BIT(0) +#define SC2730_LDO_VDDCAMIO_PD_MASK BIT(0) +#define SC2730_LDO_VDDWCN_PD_MASK BIT(0) +#define SC2730_LDO_VDDCAMD1_PD_MASK BIT(0) +#define SC2730_LDO_VDDCAMD0_PD_MASK BIT(0) +#define SC2730_LDO_VDDRF1V25_PD_MASK BIT(0) +#define SC2730_LDO_AVDD12_PD_MASK BIT(0) +#define SC2730_LDO_VDDCAMA0_PD_MASK BIT(0) +#define SC2730_LDO_VDDCAMA1_PD_MASK BIT(0) +#define SC2730_LDO_VDDCAMMOT_PD_MASK BIT(0) +#define SC2730_LDO_VDDSIM2_PD_MASK BIT(0) +#define SC2730_LDO_VDDEMMCCORE_PD_MASK BIT(0) +#define SC2730_LDO_VDDSDCORE_PD_MASK BIT(0) +#define SC2730_LDO_VDDSDIO_PD_MASK BIT(0) +#define SC2730_LDO_VDD28_PD_MASK BIT(1) +#define SC2730_LDO_VDDWIFIPA_PD_MASK BIT(0) +#define SC2730_LDO_VDD18_DCXO_PD_MASK BIT(10) +#define SC2730_LDO_VDDUSB33_PD_MASK BIT(0) +#define SC2730_LDO_VDDLDO0_PD_MASK BIT(0) +#define SC2730_LDO_VDDLDO1_PD_MASK BIT(0) +#define SC2730_LDO_VDDLDO2_PD_MASK BIT(0) +#define SC2730_LDO_VDDKPLED_PD_MASK BIT(15) + +/* + * SC2730 vsel register + */ +#define SC2730_DCDC_CPU_VOL (SC2730_REGULATOR_BASE + 0x44) +#define SC2730_DCDC_GPU_VOL (SC2730_REGULATOR_BASE + 0x54) +#define SC2730_DCDC_CORE_VOL (SC2730_REGULATOR_BASE + 0x64) +#define SC2730_DCDC_MODEM_VOL (SC2730_REGULATOR_BASE + 0x74) +#define SC2730_DCDC_MEM_VOL (SC2730_REGULATOR_BASE + 0x84) +#define SC2730_DCDC_MEMQ_VOL (SC2730_REGULATOR_BASE + 0x94) +#define SC2730_DCDC_GEN0_VOL (SC2730_REGULATOR_BASE + 0xa4) +#define SC2730_DCDC_GEN1_VOL (SC2730_REGULATOR_BASE + 0xb4) +#define SC2730_DCDC_SRAM_VOL (SC2730_REGULATOR_BASE + 0xdc) +#define SC2730_LDO_AVDD18_VOL (SC2730_REGULATOR_BASE + 0x104) +#define SC2730_LDO_VDDRF18_VOL (SC2730_REGULATOR_BASE + 0x110) +#define SC2730_LDO_VDDCAMIO_VOL (SC2730_REGULATOR_BASE + 0x28) +#define SC2730_LDO_VDDWCN_VOL (SC2730_REGULATOR_BASE + 0x120) +#define SC2730_LDO_VDDCAMD1_VOL (SC2730_REGULATOR_BASE + 0x12c) +#define SC2730_LDO_VDDCAMD0_VOL (SC2730_REGULATOR_BASE + 0x138) +#define SC2730_LDO_VDDRF1V25_VOL (SC2730_REGULATOR_BASE + 0x144) +#define SC2730_LDO_AVDD12_VOL (SC2730_REGULATOR_BASE + 0x150) +#define SC2730_LDO_VDDCAMA0_VOL (SC2730_REGULATOR_BASE + 0x15c) +#define SC2730_LDO_VDDCAMA1_VOL (SC2730_REGULATOR_BASE + 0x168) +#define SC2730_LDO_VDDCAMMOT_VOL (SC2730_REGULATOR_BASE + 0x174) +#define SC2730_LDO_VDDSIM2_VOL (SC2730_REGULATOR_BASE + 0x198) +#define SC2730_LDO_VDDEMMCCORE_VOL (SC2730_REGULATOR_BASE + 0x1a4) +#define SC2730_LDO_VDDSDCORE_VOL (SC2730_REGULATOR_BASE + 0x1b0) +#define SC2730_LDO_VDDSDIO_VOL (SC2730_REGULATOR_BASE + 0x1bc) +#define SC2730_LDO_VDD28_VOL (SC2730_REGULATOR_BASE + 0x1c8) +#define SC2730_LDO_VDDWIFIPA_VOL (SC2730_REGULATOR_BASE + 0x1d4) +#define SC2730_LDO_VDD18_DCXO_VOL (SC2730_REGULATOR_BASE + 0x1e0) +#define SC2730_LDO_VDDUSB33_VOL (SC2730_REGULATOR_BASE + 0x1ec) +#define SC2730_LDO_VDDLDO0_VOL (SC2730_REGULATOR_BASE + 0x1f8) +#define SC2730_LDO_VDDLDO1_VOL (SC2730_REGULATOR_BASE + 0x204) +#define SC2730_LDO_VDDLDO2_VOL (SC2730_REGULATOR_BASE + 0x210) +#define SC2730_LDO_VDDKPLED_VOL (SC2730_REGULATOR_BASE + 0x38c) + +/* + * SC2730 vsel register mask + */ +#define SC2730_DCDC_CPU_VOL_MASK GENMASK(8, 0) +#define SC2730_DCDC_GPU_VOL_MASK GENMASK(8, 0) +#define SC2730_DCDC_CORE_VOL_MASK GENMASK(8, 0) +#define SC2730_DCDC_MODEM_VOL_MASK GENMASK(8, 0) +#define SC2730_DCDC_MEM_VOL_MASK GENMASK(7, 0) +#define SC2730_DCDC_MEMQ_VOL_MASK GENMASK(8, 0) +#define SC2730_DCDC_GEN0_VOL_MASK GENMASK(7, 0) +#define SC2730_DCDC_GEN1_VOL_MASK GENMASK(7, 0) +#define SC2730_DCDC_SRAM_VOL_MASK GENMASK(8, 0) +#define SC2730_LDO_AVDD18_VOL_MASK GENMASK(5, 0) +#define SC2730_LDO_VDDRF18_VOL_MASK GENMASK(5, 0) +#define SC2730_LDO_VDDCAMIO_VOL_MASK GENMASK(5, 0) +#define SC2730_LDO_VDDWCN_VOL_MASK GENMASK(5, 0) +#define SC2730_LDO_VDDCAMD1_VOL_MASK GENMASK(4, 0) +#define SC2730_LDO_VDDCAMD0_VOL_MASK GENMASK(4, 0) +#define SC2730_LDO_VDDRF1V25_VOL_MASK GENMASK(4, 0) +#define SC2730_LDO_AVDD12_VOL_MASK GENMASK(4, 0) +#define SC2730_LDO_VDDCAMA0_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDCAMA1_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDCAMMOT_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDSIM2_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDEMMCCORE_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDSDCORE_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDSDIO_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDD28_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDWIFIPA_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDD18_DCXO_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDUSB33_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDLDO0_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDLDO1_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDLDO2_VOL_MASK GENMASK(7, 0) +#define SC2730_LDO_VDDKPLED_VOL_MASK GENMASK(14, 7) + +enum sc2730_regulator_id { + SC2730_DCDC_CPU, + SC2730_DCDC_GPU, + SC2730_DCDC_CORE, + SC2730_DCDC_MODEM, + SC2730_DCDC_MEM, + SC2730_DCDC_MEMQ, + SC2730_DCDC_GEN0, + SC2730_DCDC_GEN1, + SC2730_DCDC_SRAM, + SC2730_LDO_AVDD18, + SC2730_LDO_VDDRF18, + SC2730_LDO_VDDCAMIO, + SC2730_LDO_VDDWCN, + SC2730_LDO_VDDCAMD1, + SC2730_LDO_VDDCAMD0, + SC2730_LDO_VDDRF1V25, + SC2730_LDO_AVDD12, + SC2730_LDO_VDDCAMA0, + SC2730_LDO_VDDCAMA1, + SC2730_LDO_VDDCAMMOT, + SC2730_LDO_VDDSIM0, + SC2730_LDO_VDDSIM1, + SC2730_LDO_VDDSIM2, + SC2730_LDO_VDDEMMCCORE, + SC2730_LDO_VDDSDCORE, + SC2730_LDO_VDDSDIO, + SC2730_LDO_VDD28, + SC2730_LDO_VDDWIFIPA, + SC2730_LDO_VDD18_DCXO, + SC2730_LDO_VDDUSB33, + SC2730_LDO_VDDLDO0, + SC2730_LDO_VDDLDO1, + SC2730_LDO_VDDLDO2, + SC2730_LDO_VDDKPLED, +}; + +static const struct regulator_ops sc2730_regu_linear_ops =3D { + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .list_voltage =3D regulator_list_voltage_linear, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, +}; + +#define SC2730_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask, \ + vstep, vmin, vmax, min_sel) { \ + .name =3D #_id, \ + .of_match =3D of_match_ptr(#_id), \ + .ops =3D &sc2730_regu_linear_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D SC2730_##_id, \ + .owner =3D THIS_MODULE, \ + .min_uV =3D vmin, \ + .n_voltages =3D ((vmax) - (vmin)) / (vstep) + 1, \ + .uV_step =3D vstep, \ + .enable_is_inverted =3D true, \ + .enable_val =3D 0, \ + .enable_reg =3D en_reg, \ + .enable_mask =3D en_mask, \ + .vsel_reg =3D vreg, \ + .vsel_mask =3D vmask, \ + .linear_min_sel =3D min_sel, \ +} + +static const struct regulator_desc regulators[] =3D { + SC2730_REGU_LINEAR(DCDC_CPU, SC2730_POWER_PD_SW, + SC2730_DCDC_CPU_PD_MASK, SC2730_DCDC_CPU_VOL, + SC2730_DCDC_CPU_VOL_MASK, 3125, 0, 1596875, + 0), + SC2730_REGU_LINEAR(DCDC_GPU, SC2730_POWER_PD_SW, + SC2730_DCDC_GPU_PD_MASK, SC2730_DCDC_GPU_VOL, + SC2730_DCDC_GPU_VOL_MASK, 3125, 0, 1596875, + 0), + SC2730_REGU_LINEAR(DCDC_CORE, SC2730_POWER_PD_SW, + SC2730_DCDC_CORE_PD_MASK, SC2730_DCDC_CORE_VOL, + SC2730_DCDC_CORE_VOL_MASK, 3125, 0, 1596875, + 0), + SC2730_REGU_LINEAR(DCDC_MODEM, SC2730_POWER_PD_SW, + SC2730_DCDC_MODEM_PD_MASK, SC2730_DCDC_MODEM_VOL, + SC2730_DCDC_MODEM_VOL_MASK, 3125, 0, 1596875, + 0), + SC2730_REGU_LINEAR(DCDC_MEM, SC2730_POWER_PD_SW, + SC2730_DCDC_MEM_PD_MASK, SC2730_DCDC_MEM_VOL, + SC2730_DCDC_MEM_VOL_MASK, 6250, 0, 1593750, + 0), + SC2730_REGU_LINEAR(DCDC_MEMQ, SC2730_POWER_PD_SW, + SC2730_DCDC_MEMQ_PD_MASK, SC2730_DCDC_MEMQ_VOL, + SC2730_DCDC_MEMQ_VOL_MASK, 3125, 0, 1596875, + 0), + SC2730_REGU_LINEAR(DCDC_GEN0, SC2730_POWER_PD_SW, + SC2730_DCDC_GEN0_PD_MASK, SC2730_DCDC_GEN0_VOL, + SC2730_DCDC_GEN0_VOL_MASK, 9375, 20000, 2410625, + 0), + SC2730_REGU_LINEAR(DCDC_GEN1, SC2730_POWER_PD_SW, + SC2730_DCDC_GEN1_PD_MASK, SC2730_DCDC_GEN1_VOL, + SC2730_DCDC_GEN1_VOL_MASK, 6250, 50000, 1643750, + 0), + SC2730_REGU_LINEAR(DCDC_SRAM, SC2730_POWER_PD_SW, + SC2730_DCDC_SRAM_PD_MASK, SC2730_DCDC_SRAM_VOL, + SC2730_DCDC_SRAM_VOL_MASK, 3125, 0, 1596875, + 0), + SC2730_REGU_LINEAR(LDO_AVDD18, SC2730_POWER_PD_SW, + SC2730_LDO_AVDD18_PD_MASK, SC2730_LDO_AVDD18_VOL, + SC2730_LDO_AVDD18_VOL_MASK, 10000, 1175000, 1805000, + 0), + SC2730_REGU_LINEAR(LDO_VDDRF18, SC2730_LDO_VDDRF18_PD, + SC2730_LDO_VDDRF18_PD_MASK, SC2730_LDO_VDDRF18_VOL, + SC2730_LDO_VDDRF18_VOL_MASK, 10000, 1175000, 1805000, + 0), + SC2730_REGU_LINEAR(LDO_VDDCAMIO, SC2730_LDO_VDDCAMIO_PD, + SC2730_LDO_VDDCAMIO_PD_MASK, SC2730_LDO_VDDCAMIO_VOL, + SC2730_LDO_VDDCAMIO_VOL_MASK, 10000, 1200000, + 1830000, 0), + SC2730_REGU_LINEAR(LDO_VDDWCN, SC2730_LDO_VDDWCN_PD, + SC2730_LDO_VDDWCN_PD_MASK, SC2730_LDO_VDDWCN_VOL, + SC2730_LDO_VDDWCN_VOL_MASK, 15000, 900000, 1845000, + 0), + SC2730_REGU_LINEAR(LDO_VDDCAMD1, SC2730_LDO_VDDCAMD1_PD, + SC2730_LDO_VDDCAMD1_PD_MASK, SC2730_LDO_VDDCAMD1_VOL, + SC2730_LDO_VDDCAMD1_VOL_MASK, 15000, 900000, + 1365000, 0), + SC2730_REGU_LINEAR(LDO_VDDCAMD0, SC2730_LDO_VDDCAMD0_PD, + SC2730_LDO_VDDCAMD0_PD_MASK, SC2730_LDO_VDDCAMD0_VOL, + SC2730_LDO_VDDCAMD0_VOL_MASK, 15000, 900000, + 1365000, 0), + SC2730_REGU_LINEAR(LDO_VDDRF1V25, SC2730_LDO_VDDRF1V25_PD, + SC2730_LDO_VDDRF1V25_PD_MASK, + SC2730_LDO_VDDRF1V25_VOL, + SC2730_LDO_VDDRF1V25_VOL_MASK, 15000, 900000, + 1365000, 0), + SC2730_REGU_LINEAR(LDO_AVDD12, SC2730_LDO_AVDD12_PD, + SC2730_LDO_AVDD12_PD_MASK, SC2730_LDO_AVDD12_VOL, + SC2730_LDO_AVDD12_VOL_MASK, 15000, 900000, 1365000, + 0), + SC2730_REGU_LINEAR(LDO_VDDCAMA0, SC2730_LDO_VDDCAMA0_PD, + SC2730_LDO_VDDCAMA0_PD_MASK, SC2730_LDO_VDDCAMA0_VOL, + SC2730_LDO_VDDCAMA0_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDCAMA1, SC2730_LDO_VDDCAMA1_PD, + SC2730_LDO_VDDCAMA1_PD_MASK, SC2730_LDO_VDDCAMA1_VOL, + SC2730_LDO_VDDCAMA1_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDCAMMOT, SC2730_LDO_VDDCAMMOT_PD, + SC2730_LDO_VDDCAMMOT_PD_MASK, + SC2730_LDO_VDDCAMMOT_VOL, + SC2730_LDO_VDDCAMMOT_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDSIM2, SC2730_LDO_VDDSIM2_PD, + SC2730_LDO_VDDSIM2_PD_MASK, SC2730_LDO_VDDSIM2_VOL, + SC2730_LDO_VDDSIM2_VOL_MASK, 10000, 1200000, 3750000, + 0), + SC2730_REGU_LINEAR(LDO_VDDEMMCCORE, SC2730_LDO_VDDEMMCCORE_PD, + SC2730_LDO_VDDEMMCCORE_PD_MASK, + SC2730_LDO_VDDEMMCCORE_VOL, + SC2730_LDO_VDDEMMCCORE_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDSDCORE, SC2730_LDO_VDDSDCORE_PD, + SC2730_LDO_VDDSDCORE_PD_MASK, + SC2730_LDO_VDDSDCORE_VOL, + SC2730_LDO_VDDSDCORE_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDSDIO, SC2730_LDO_VDDSDIO_PD, + SC2730_LDO_VDDSDIO_PD_MASK, SC2730_LDO_VDDSDIO_VOL, + SC2730_LDO_VDDSDIO_VOL_MASK, 10000, 1200000, 3750000, + 0), + SC2730_REGU_LINEAR(LDO_VDD28, SC2730_POWER_PD_SW, + SC2730_LDO_VDD28_PD_MASK, SC2730_LDO_VDD28_VOL, + SC2730_LDO_VDD28_VOL_MASK, 10000, 1200000, 3750000, + 0), + SC2730_REGU_LINEAR(LDO_VDDWIFIPA, SC2730_LDO_VDDWIFIPA_PD, + SC2730_LDO_VDDWIFIPA_PD_MASK, + SC2730_LDO_VDDWIFIPA_VOL, + SC2730_LDO_VDDWIFIPA_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDD18_DCXO, SC2730_POWER_PD_SW, + SC2730_LDO_VDD18_DCXO_PD_MASK, + SC2730_LDO_VDD18_DCXO_VOL, + SC2730_LDO_VDD18_DCXO_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDUSB33, SC2730_LDO_VDDUSB33_PD, + SC2730_LDO_VDDUSB33_PD_MASK, SC2730_LDO_VDDUSB33_VOL, + SC2730_LDO_VDDUSB33_VOL_MASK, 10000, 1200000, + 3750000, 0), + SC2730_REGU_LINEAR(LDO_VDDLDO0, SC2730_LDO_VDDLDO0_PD, + SC2730_LDO_VDDLDO0_PD_MASK, SC2730_LDO_VDDLDO0_VOL, + SC2730_LDO_VDDLDO0_VOL_MASK, 10000, 1200000, 3750000, + 0), + SC2730_REGU_LINEAR(LDO_VDDLDO1, SC2730_LDO_VDDLDO1_PD, + SC2730_LDO_VDDLDO1_PD_MASK, SC2730_LDO_VDDLDO1_VOL, + SC2730_LDO_VDDLDO1_VOL_MASK, 10000, 1200000, 3750000, + 0), + SC2730_REGU_LINEAR(LDO_VDDLDO2, SC2730_LDO_VDDLDO2_PD, + SC2730_LDO_VDDLDO2_PD_MASK, SC2730_LDO_VDDLDO2_VOL, + SC2730_LDO_VDDLDO2_VOL_MASK, 10000, 1200000, 3750000, + 0), + SC2730_REGU_LINEAR(LDO_VDDKPLED, SC2730_LDO_VDDKPLED_PD, + SC2730_LDO_VDDKPLED_PD_MASK, SC2730_LDO_VDDKPLED_VOL, + SC2730_LDO_VDDKPLED_VOL_MASK, 10000, 1200000, + 3750000, 0), +}; + +static int sc2730_regulator_unlock(struct regmap *regmap) +{ + return regmap_write(regmap, SC2730_PWR_WR_PROT, + SC2730_WR_UNLOCK_VALUE); +} + +static int sc2730_regulator_probe(struct platform_device *pdev) +{ + int i, ret; + struct regmap *regmap; + struct regulator_config config =3D { }; + struct regulator_dev *rdev; + + regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) { + dev_err(&pdev->dev, "failed to get regmap.\n"); + return -ENODEV; + } + + ret =3D sc2730_regulator_unlock(regmap); + if (ret) { + dev_err(&pdev->dev, "failed to release regulator lock\n"); + return ret; + } + + config.dev =3D &pdev->dev; + config.regmap =3D regmap; + + for (i =3D 0; i < ARRAY_SIZE(regulators); i++) { + rdev =3D devm_regulator_register(&pdev->dev, ®ulators[i], + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register regulator %s\n", + regulators[i].name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct of_device_id sc2730_regulator_of_match[] =3D { + { .compatible =3D "sprd,sc2730-regulator" }, + { } +}; +MODULE_DEVICE_TABLE(of, sc2730_regulator_of_match); + +static struct platform_driver sc2730_regulator_driver =3D { + .driver =3D { + .name =3D "sc2730-regulator", + .of_match_table =3D sc2730_regulator_of_match, + }, + .probe =3D sc2730_regulator_probe, +}; + +module_platform_driver(sc2730_regulator_driver); + +MODULE_AUTHOR("Chen Junhui "); +MODULE_DESCRIPTION("Spreadtrum SC2730 regulator driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0