From nobody Fri Apr 17 10:36:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41DD82AD25 for ; Fri, 20 Feb 2026 05:54:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771566877; cv=none; b=Fv/3fqziXNyIYkpJHOgGMsZkfPkgLzILbGc7gU6/VZjyjXAGLzXehDvlMW5AwHErj88nrHQcA1mU4G00rtckf5dp02NyOVd+nB65DcvefHMGp96kLae6+Kj2Q4mqcb+TXE4dOtFqxsK2fOZdFEQpAuzzZwCQVhuwPSFbHxbRWNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771566877; c=relaxed/simple; bh=yTnXF7Ft6VvbHmgcahe1v/ziOK4hNnjrl83gdkHvKLc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rzeC9RuUVYJO2RV7POh1m+ToicJOO6CyHm9svqEV7vrTst/Hshm2IXKm5B/whn8JF/P2SCawkrWBHa7iT2YQ7+tlaqBsm0oIRny/V3S/+WlvaSq2iSvQySTKb8yYsnLeY2RThJS5W3z++UHG17xg4BT7aID5UB5gWZDnryw27WE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=W0KRFdu3; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=QsUUrn4Q; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="W0KRFdu3"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="QsUUrn4Q" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61K5SO742380894 for ; Fri, 20 Feb 2026 05:54:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jbywBh+Fp37quyHpJxEH+Oxm1N60Sf17rtYjYQDeu7k=; b=W0KRFdu3S8xLEbPM +vVB6SAytJ0OvrgXsDrAgKIIemrwCj/JYtsJ1inT288St8k6ABVmX2jN4uRx8Wv/ dQ9gDOUDgEavy6SwpG+mneE4eAObdsqM9kGdJJ75cc2QmlzsGHDlm1U1qfrkCNZw 4IM7XkHi4zpER9Hpx0lWOBo+GD6Mum1XLnmnEetY63PI4prT7S4eQjH+ramjRP31 7aa7uUzhgij0yTE1Gs5uibt+3Fzo49KprgQMbZStxhBoxyT61Bh2TkJqDtQ7u5zT 2oGLz208A3dQHuGNf/hWE9I9SSna13UPMQvsAeKw3B47+sBn8VQUVuNvoVuxFhoJ +ItRVg== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cechh8rxw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 20 Feb 2026 05:54:35 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2a946c0e441so16330145ad.1 for ; Thu, 19 Feb 2026 21:54:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771566874; x=1772171674; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jbywBh+Fp37quyHpJxEH+Oxm1N60Sf17rtYjYQDeu7k=; b=QsUUrn4Q74vLrU3u53vgdbfwiGowRbd2MJDygXllMuBsL/nlWePydXDnTcLANbAtyK pO+ImJZKQZwV5XfhCoJ2DhjoC491rPT/JPQ686lz6zNNwRufm9WeewcVWFenEjPSDNBB yH4KKZm3BZN9LkEbJsjfDwulm3AxHx3XxSdzHOR9chVdSZlhHZ0YGOlIhDdqf88RnwyL tjMBvffOBz+OblSEG2gffO5Qv2BOnmZNExD0wi5e9kozIWtp+LfF2pkPbDuUhCI8FMGr AKFh66XEqMGHPvPrjjIqPK22LTt0dpPdJr9BYzIuyiJMfbhyBd9X71jSv3DNNSg2oBtd lygQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771566874; x=1772171674; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jbywBh+Fp37quyHpJxEH+Oxm1N60Sf17rtYjYQDeu7k=; b=og7K+usQia8T0nWUpNgXDzqaW0PJ9Lo/2GbtwlPtnDcsVqzrUfdLfL98ptjKxbxkYW kcy3pTWRLhYIDHHeRXE+sDnMf54IYOC03RAffEcW8qiG8t4dRoZAVVjZ/w2xAuWc4pES f1bYXgRREgfsc0gK6XqP/XrnN9FfVxM5MXvgxORt5/B8pdfoG26E5XxqeHB9IY4WoCbE LtrRRZa+1HAs6SHjUwB4L4e6F87yC7S539ddK2dxoT8ppm4VSvDMosSOeZy5uOdBn50m 997AZa9RmaM+qVxmcJHHYQErTh7j2S5LQYFdVBNYK2QLBUweK979HteAx+kWGu8J8nHg o7aw== X-Forwarded-Encrypted: i=1; AJvYcCXAJkQ8uKNSqQs+/8cIJLPPpQ8WZG15evje4qHnEaDYkpXy+HKST2aT7bkY0HOQPjXzxGOqUwqkvs7ymC8=@vger.kernel.org X-Gm-Message-State: AOJu0Yxi6d0IDLURgY7uf5vGkECQKFI1FquZ6ns8pOhGstowgHmtR+A4 B65RephoHQs43XaxcvcVHXx0WSWhHTIiDevDcfvFox1aPtGBeCZ1/HP8E7oXanel4E7/4LwVsfz +PUBut4pmI3kqg8pAegjdaEpD5b4nqnXP4g3V48oROapAStFtLia60sHLGQs251bRV3I= X-Gm-Gg: AZuq6aJDfph9oiVbkjIeZVImwUV7NJ/svgoOIFI9JHGTGcrzur+Yf1SBYQvGHJqerd3 FQv26U2hpR4QKmOpZoflnXgGnbpBa+iYzeb2/4Ff+vD1PD6gh5TFpcXp5xeSqsNzUhkeYQrCTQB jSpL3uLuA7cnZnrc0PSMBUbedbULDBizGErhUWkWsZRo8KzdmeHdoST0J1n80bL3h+eRzrtikex mjz2mvvjSXPEwXBp2Vn/6YiMLoiJkBfz/HLq/6yeNx60MvOsZ7/3Nezq4aRQCkaZXtmMpVz7CZO vWM8cc31UbXIv7nU7I4lzvjNR94lJdUxYkC3UZzLdd3SV0sLpGMiddYglOeRNTjH2Kd1yOlhUS8 NkSSBYy4g/fZio82r0T73rEPKuRJRm2QA2jl5negqm9JMUg== X-Received: by 2002:a17:903:2449:b0:2a9:42ba:b093 with SMTP id d9443c01a7336-2ad50eee65amr75156845ad.25.1771566874017; Thu, 19 Feb 2026 21:54:34 -0800 (PST) X-Received: by 2002:a17:903:2449:b0:2a9:42ba:b093 with SMTP id d9443c01a7336-2ad50eee65amr75156575ad.25.1771566873462; Thu, 19 Feb 2026 21:54:33 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a6fa326sm197949665ad.1.2026.02.19.21.54.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 21:54:33 -0800 (PST) From: Taniya Das Date: Fri, 20 Feb 2026 11:24:20 +0530 Subject: [PATCH v3 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-gpucc_sm8750_v2-v3-1-6c5408564c3c@oss.qualcomm.com> References: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> In-Reply-To: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: HZtcEDArcrsyyk_6EZPjci6g9GkZ7mD3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIwMDA0OCBTYWx0ZWRfXylFuJ9h2xdAt GqVZ95+X8VQoe5M1bJ9rhYhrsm0DedP0BwCn9ZNKLO9cgI/SY3/OvdKqsMStctTP2ZZbFhwjd7D LHnBk6l3dTBrCZ/zHephpkhL/ZH5r6MmyjK0QgqWU7c94q3ri01NYEPaXjPD97XbLH492sjSz3F QyX//ssew56Xi7o6ubg2SYcUf2J3LmZa3RZbRHa3B4QXh9nDevPyPJW0k5wdlpzz7cGHk4OT8Fj cHMPGftaE776fuItSdNCiLndP4ZzmP2tSStsfQYaIQNwgn+8QLDiiaiLTVcLBrm1zibUjNIntXq sLq9sYwsi51p2X98rMNAl+zyfh/VFXdDqueuDIrehqBtDmM3jEvzKj3sY6ttmsNkV4Ce6ESgALP ktGktZgRwva9EShU8OCs4gb7L4NrxmqY5v946MDyiH7etKzj88wVO3KzzLsnsPVm6ybOc1LG46m EyLH+N0L4ojnyud6ljw== X-Proofpoint-ORIG-GUID: HZtcEDArcrsyyk_6EZPjci6g9GkZ7mD3 X-Authority-Analysis: v=2.4 cv=KYzfcAYD c=1 sm=1 tr=0 ts=6997f71b cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=DuI_pPAKbSgazMGYJwsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_06,2026-02-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602200048 From: Konrad Dybcio The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Update the bindings to accommodate for SM8750 SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 1 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + include/dt-bindings/clock/qcom,sm8750-gpucc.h | 50 ++++++++++++++++++= ++++ 3 files changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkct= l.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.ya= ml index 5490a975f3db7d253a17cc13a67f6c44e0d47ef3..1876f23c174e4ede590847d8022= 2e49b4200d8ba 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,kaanapali-gxclkctl + - qcom,sm8750-gxclkctl =20 power-domains: description: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 6feaa32569f9a852c2049fee00ee7a2e2aefb558..3504db982cfa71fc03e187c3dac= 148d5f1cfb6ec 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -22,6 +22,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,sm8750-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h =20 properties: @@ -35,6 +36,7 @@ properties: - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,sm8750-gpucc - qcom,x1e80100-gpucc - qcom,x1p42100-gpucc =20 diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bin= dings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..e2143d905fece19f4ef5cf41372= 4f1597daa85ba --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +#endif --=20 2.34.1 From nobody Fri Apr 17 10:36:14 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 937CD2FFF90 for ; Fri, 20 Feb 2026 05:54:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771566882; cv=none; b=cPc5TLxs7qpmXwb1zTE64pUzS/ZDqgkhb2xxGoaLYlPzkqduz6mZQxYO2cjqZOhwKNSwSsDc2btpk/NjyYfx855UB2Y3F5f6vWzXIx/KtepR3qbjv09GfsTU+yp2ciebwET7REAWmoffQch47ovz0SnhGoMoURe5mD+6aQ+rluc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771566882; c=relaxed/simple; bh=cqWTKKBymZofvGgsP3aYbRSILzbJ0Vww2W4ZEbHVKng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c6X7nLCf8EPecbuuJGyhMQUYz3rrZHuTgI0Me8ztCTTZ7ya7675mhacjVI6QxpWYzWK1oIwclSjHgTkAO7eCJBma/iE+n6bScocus0kX2FSyKypY1tQOyv+HkV2jmLh/Bx0HYGe48NMPP1fwCXW2gkkZDhxhYJ2E+zRVf4pqrks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=GwVTcFZm; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=YZ46RgX7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="GwVTcFZm"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="YZ46RgX7" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61K5WRiK1813906 for ; Fri, 20 Feb 2026 05:54:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= rViScmI0SufRwx6haTNO04GzBn02vMQigY95Lu2CzHo=; b=GwVTcFZmqhujy+fI uNnU/Ye4QHKrrg2A5CwaKKpx9Bf/OPwq7bfCLHjXyTzFzkIfwDg0RwBmYnGXewRk MVcA7YA8MN5mgXwAtpI+QcC//PC2sTXzMX0l7sNnOtCq9xdQaNsnxDIaPeh3XAvf acdUvmo/n+9Wqpc059o7iaMdFuZmAnSkc48LETM62OgPfmTg/KBZ+jhV95bMjeqt 2mAaJCZOX+qKjoQ1qrn8tV2Xvd9DHeWpkxfiUP6h3lwzpVDMXaLM4/yhGDfHgAVk Hy9+/m7TRknwZc8FJKaGRVuhBGJU8sX9Sv7iSwF0dDRthgikrIJQlmZOiKiaJ+x4 M2nJHw== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cedsnrmrw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 20 Feb 2026 05:54:39 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2a8fc061ce1so124563025ad.0 for ; Thu, 19 Feb 2026 21:54:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771566879; x=1772171679; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rViScmI0SufRwx6haTNO04GzBn02vMQigY95Lu2CzHo=; b=YZ46RgX71AHVrb92Txj+uLgVsxSkSxbo0vrISFVnph73I7hqTEXjwxzycKBnhfs1bF 7buc0CmziV4qUU4TvBIRHDP2zovvJOZuKgyAOjMmDLZyZnX8Y5RzKoc1vXJJldGxQCId jVPaVHYjqrFg0G78t8v0boSPda3t8ZYeft0hpinCOAXO5qAYP37qV98eg7rYAHEvZFlD gec8ci3GezEhr1zH8Pv+plsT85NAVY/GCWj/NwcxRWvYzwj1QnkmvQbOBVkNRyqCMgxp U99xflbZgNBmcB98bNcIiWfIMTfwfb3Ls87Ccf/n9IKUDrAxIoGoEg+SzD+bdneXLB2x TuDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771566879; x=1772171679; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rViScmI0SufRwx6haTNO04GzBn02vMQigY95Lu2CzHo=; b=kdQzojyJe69sQI1UBL4JqwfciVZVuI4r8bDg28I04j1XwCZIY5N6J5CEbKPPJ5AduN lJzepGttGM8wLtzswOgygCAL924U2ao8j2LUvz8rg28HdCOkul2aoDgZMO8FAny8mnsH Uf7Vyp/p4a/61zqhPxiN2Ezl9isiteOxVx4HeSA5QEf8So070FvmAOWJRiHaiBel/z6C Bhlm7cJqAG650wiI293Cbw82/0xSvfS0hggZ42utdo27tHgyY1LjgZOFC/+50QjokYRH aX3GMnmMjbJWegigueRIKW7pMcTkfwciDpXI7JHythB+HiWpat6Sqtz0TdQ78dDCHQN/ 8WmA== X-Forwarded-Encrypted: i=1; AJvYcCWMZC6cVse1wYEOQR5+Zq4OPbpTidjqKqU1s5jK4Qb45RLv9BzUfo2CnuNbvgGZt1uAzj+72CW/UEZwops=@vger.kernel.org X-Gm-Message-State: AOJu0Yzj1i0FAXlo1LaPG6vx6Ed3OjKJ/1v+GmwxxH8kpKyeXHxxB64J 6QPboIE3nbDSY/ENwaIKxB0CR/k2YJEr/BrrCZ3I02WG0NAot1Pkcb6ebKMIKjLY3rWwkqtWNaE MYOvPJqxQHlB1x6tgYXBGgJ8mldFvye6F6PqIERFgKcJd03GUIyv76JtrYRxBjrL2G4A= X-Gm-Gg: AZuq6aKht0NKjRg/52MDlVrP7Ed4SmBlfCiyBneUj6JzeWx1RmuL7OGFS86u9DsMq9a dHbG/3vbsrHbm1xjM6XQK1J3b+uW1Kye/FzaOT8pGqJSqepkyxNx941TkLh3tL+sMR4JHDcZnru /hHJ/11hMr77CIDG2MuLVG6ACi+JUmy0ygcgnnD1w28kIjd8YTKWA5U7Fpe60wCqYAec6iCZZzo FU421/hx5YK0WE3DfvIp40mXBxi7AGtb9MUrqn0t2sFYoXnuzcQdSyv8uq3DxUxZoLi1cT1nuU4 erXcOLg80E3luKXaKiGGnZL7dY19cdGVDWv4PO/V36bxEDdYj5aGEVCJXGCQFmWoKiDlO93pRGb ZsVq1J9LB/PeINodXCzrBMK5FM2heQAkJ0EtlQhdITT9LdA== X-Received: by 2002:a17:902:d4c1:b0:2a9:43a9:d371 with SMTP id d9443c01a7336-2ad6cde3970mr7707265ad.37.1771566878999; Thu, 19 Feb 2026 21:54:38 -0800 (PST) X-Received: by 2002:a17:902:d4c1:b0:2a9:43a9:d371 with SMTP id d9443c01a7336-2ad6cde3970mr7707065ad.37.1771566878419; Thu, 19 Feb 2026 21:54:38 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a6fa326sm197949665ad.1.2026.02.19.21.54.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 21:54:38 -0800 (PST) From: Taniya Das Date: Fri, 20 Feb 2026 11:24:21 +0530 Subject: [PATCH v3 2/3] clk: qcom: Add a driver for SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-gpucc_sm8750_v2-v3-2-6c5408564c3c@oss.qualcomm.com> References: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> In-Reply-To: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIwMDA0OCBTYWx0ZWRfX8eZEZMFs3uoR pSqzj39gwHf+8NkS9SHF6kQfSBcvaXYjrgYCQsp3FR2y15tgYW7ikTPtcfcfzGcG+NJybmrAVoL Tn7ZKUb12o4W0yLU1MlPr1WIdnMyK4Z2btRQClowUVIm08cvRYx+mKUwKeYucjQampJ7/W0DQqv 1lGBsTx56Vxe8l8t6RTTOU2LHhSI8vrSf3MIgSAvHA+D6eD1nDqYpKuFK4wWb5er6rfmuPiPO7q T0qQuq0CheUeuZjmOq2/2JdJRJK4i9EFuCQG4CRgepsPcPQlP1S/zHBldsQ/IGKrBwlzfdUKeHp TG/LOSmVA1G+hTRWK4Va50e9iottNG4bFpOs3DG9BQqlE2TyTVDLB0LK0jyQWmdh0HL94nmaziG FiMLc43GDdNvrr7SoPddbF424xS7LagxTxQBPCG5b0pwwqFg0v3fJ8J/78Mv6QHgVYLPHGS2xLA gTAa1Xov+HNXbjmXRBQ== X-Proofpoint-ORIG-GUID: VFtl6nBAAlqNS7UPe2s1KKequLt2i52S X-Authority-Analysis: v=2.4 cv=JsD8bc4C c=1 sm=1 tr=0 ts=6997f71f cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=PLT511quuigA__OA0o4A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: VFtl6nBAAlqNS7UPe2s1KKequLt2i52S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_06,2026-02-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602200048 From: Konrad Dybcio Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for SM8750 as the GX clock controller is a reuse of the Kaanapali driver. Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8750.c | 472 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 482 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb7445e396048a5bba23fce8d719281f..e4ec41e3dc7dee43a5682a3bd93= 297785e67e41f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1481,6 +1481,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_GPUCC_8750 + tristate "SM8750 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + help + Support for the graphics clock controller on SM8750 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_LPASSCC_6115 tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55f1914079f15323b8cdd1608ad4c0..817b13f5e78cb534e165b09d95e= 70cd4a58b12bd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -180,6 +180,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o +obj-$(CONFIG_SM_GPUCC_8750) +=3D gpucc-sm8750.o gxclkctl-kaanapali.o obj-$(CONFIG_SM_GPUCC_MILOS) +=3D gpucc-milos.o obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o diff --git a/drivers/clk/qcom/gpucc-sm8750.c b/drivers/clk/qcom/gpucc-sm875= 0.c new file mode 100644 index 0000000000000000000000000000000000000000..2983683e6fbb06b39ecf5e91cf5= 9df74fb61c8d5 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8750.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_elu_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x34, + .alpha =3D 0x1555, + .config_ctl_val =3D 0x19660387, + .config_ctl_hi_val =3D 0x098060a0, + .config_ctl_hi1_val =3D 0xb416cb20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D taycan_elu_vco, + .num_vco =3D ARRAY_SIZE(taycan_elu_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpu_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_elu_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0_out_even.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .fw_name =3D "gpll0_out_main" }, + { .fw_name =3D "gpll0_out_main_div" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x942c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x910c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x910c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x90e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x9010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x9110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x9070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x9060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x93e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x90f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9080, + .gds_hw_ctrl =3D 0x9094, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm8750_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] =3D &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_sm8750_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8750_resets[] =3D { + [GPU_CC_GPU_CC_XO_BCR] =3D { 0x9000 }, + [GPU_CC_GPU_CC_GX_BCR] =3D { 0x905c }, + [GPU_CC_GPU_CC_CX_BCR] =3D { 0x907c }, + [GPU_CC_GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPU_CC_GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPU_CC_GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, +}; + +static const struct regmap_config gpu_cc_sm8750_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9800, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *gpu_cc_alpha_plls[] =3D { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_sm8750_critical_cbcrs[] =3D { + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9064, /* GPU_CC_GX_AHB_FF_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ + 0x93a4, /* GPU_CC_CB_CLK */ + 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */ +}; + +static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data =3D { + .alpha_plls =3D gpu_cc_alpha_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_alpha_plls), + .clk_cbcrs =3D gpu_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_sm8750_desc =3D { + .config =3D &gpu_cc_sm8750_regmap_config, + .clks =3D gpu_cc_sm8750_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sm8750_clocks), + .resets =3D gpu_cc_sm8750_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sm8750_resets), + .gdscs =3D gpu_cc_sm8750_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sm8750_gdscs), + .driver_data =3D &gpu_cc_sm8750_driver_data, +}; + +static const struct of_device_id gpu_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table); + +static int gpu_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc); +} + +static struct platform_driver gpu_cc_sm8750_driver =3D { + .probe =3D gpu_cc_sm8750_probe, + .driver =3D { + .name =3D "sm8750-gpucc", + .of_match_table =3D gpu_cc_sm8750_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8750_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Apr 17 10:36:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C452F83AC for ; Fri, 20 Feb 2026 05:54:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771566887; cv=none; b=qPKdfj8eBpYSIJjHdfKV4wqmC6UbhGDNXFzyzTwN3IvT3y6NHPRnt1y8YcoCXAEh/N9eDs0wruGDaFXusBXMwCwPHOne64zdIqnI9GaeJNi1FwgSnPk7l6cxB/186hq4FEl7FumRjzZID0Tiqyi/sxuNXM+3z7Y4YFM3OrP//c8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771566887; c=relaxed/simple; bh=YJTFGMEepF3OlAHZP8f2rwHLxWqlT+Xu+VLIoE2sCe4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Aqzyjn1m7Re5jRla7cmnpjl1n0oo0GLbtc30zpkX7OTdgFCnHWJCqvM6xMY+luc7RORE9Zda95WTJqEh7INvbMqi1MhqemYPx72EfHGhVUaM60hmCiofRYeFGr5YbNftlLBSzlpBzjP5dv/LAnw7MQGSPtoJRTIHxlwViadYk7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=p4Jdk/Rs; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=C7aqkyAm; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="p4Jdk/Rs"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="C7aqkyAm" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61K5Rm0Q3697643 for ; Fri, 20 Feb 2026 05:54:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= AjonDUMUOPD0sBh3EsKMWNmFtBDTuVGTl0/oR15Yd1s=; b=p4Jdk/Rs7dUJlMhZ oV5+XMPM9WavYwL7edqsuIxFb9511c5RVXbx9WjEi0pyJRcRMGwNwF2GXT0TcqJl RFeJF2Mk/gW5QQfYAGhmjdSt2Sr6xBJfV2If3lVdeU1cw/nrJNR3leUC1YHmfGyG 9mEVyC1DbgDdEuDGg0a8Z3OO85vY4NS6JGTCetinq2rGKTQuhBnwcEzHVNOz8mcG glVXDv6ksEAQ4v+uzaUipeDaE/c/I80wM4Y3BIPeCMVB3Ou7j7w+4K2Q4gUvaU1W YcGLri+C8FxpHNspmMEHyB9vokJ0IcdF/MgaSORM1GguWWgxMsbnZ047WEA5Usy0 B0F7iA== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ceh5jg3yn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 20 Feb 2026 05:54:44 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2ad44941ea2so11385755ad.1 for ; Thu, 19 Feb 2026 21:54:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771566884; x=1772171684; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AjonDUMUOPD0sBh3EsKMWNmFtBDTuVGTl0/oR15Yd1s=; b=C7aqkyAmqCIbRZQOXsqanssBa1DEZYNiTfHbMumVWNGgKraTI/OsC2D1JT4CHMjfXG Qb7PA+2nFGAia9dE2YFMy7DK9Ew1ufprMreOPmH/wtfkKf9JGerF3nY5z1tWlBV0Obju WhDjP1kAmVIZfwgT4CXGdJeEtd010Td5yMgMsKdZUzVSJpIppl2TXXdRojc3kbPg42P+ tMVbGwUSqri3HQcaLOaW+AtEUjn1spnDGpRjldw+9j80jO5JdcYfy/DFd0IX33ZKuP6g ngnR4oljAjdtIkpMh2Xl8udv1vamfVRdsICMZjk4VNGgGDw8vLnVn/eFC/Q23Nt29MRa DhMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771566884; x=1772171684; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=AjonDUMUOPD0sBh3EsKMWNmFtBDTuVGTl0/oR15Yd1s=; b=P3wPeSQrpKgXSDKF+JFD/V2I9KDQ47aJlR678asrfYqjB+hJN4VQmv1RPO0S4QWInv px43RBa9Y2B/d+PF5AGSpwsrU+270idZG+VfMSeJ+SvRtTsitZj0e1lUk27Bhw6b5Rsv MorYkegRcfo1OA5tJDbGWBtGyL0b79WxhT5Hn5ELS4sFtv9QScxWzEQI4p4yjg8tn76i G7SRKGoMmfb4XlcGdOD24JKm5wsO/YgVxNviN7gPZp2d90NT290XWQGsD04XnQGMEogU AFNeuMRn5a99RW28vGn4ULhH9e/ZvHdi9NUJh9DoDOSruVTjk/YpTxnukCQG5ZmdTh/c miMw== X-Forwarded-Encrypted: i=1; AJvYcCUTR2W3fwsoi2JwI7NCartyJ0NEH+2xbF4TpF0AU457nYbI0xN7VCL0DofEcOGQ6pD2rWPSOTD1rTsR5u4=@vger.kernel.org X-Gm-Message-State: AOJu0YwOKnmNdVtY4Jh9muRHsPQ9VthHaZ24rKtuQTQdFyOynng5XHsA u1Crs3/q061iOEJdUQtSd2tkPZsKbJ+ZQY3rmY4/QmX82WhTjuF+0ZwROH98mpLkPUJVg2grFgI Dps2Uorj4vSQDBB5gO7Ws33uTb2OCd5nWUQMDIoxy512Y/s3R+t8eOw0tZCUkL29fjqZb2kvC47 c= X-Gm-Gg: AZuq6aK+0FN+AU+dwAMS7H1CsMZ1ZaB8WmtJy8AHKHvxMppSeqYHr3tlJBUKFS9hDmO Ka7H+g2RxKjcXGlMVcT6UEKQL07+7xVzP/bcq2WBfVbdN2oz1aEWmvnBVu0r4NGo1hmvGWpL1uD OEoSxIGDITjIH3C9qQHauu3gndb7ktz3aR91X0M58C8537+++pJqeujaGuyqKgU1MqwNLsedrIk J3oQBZkUT4bPe8nSu/7fXbeEN2mcgx4bqVdsja3ISubF+InoY0qplLIlIsCYmE9BXyjHhARudMX VorBngEwGnL90artumpDhdDxeK1itl86Hr2OLoMJDMTWIQcMz/QEemRZhM/GsGmc40bIykRTX+I oigo+LFlSJy28dGaoFgYXOlHl3vuLTx45hLZEJuWjFf8TVw== X-Received: by 2002:a17:902:ef52:b0:2aa:e6fa:2f67 with SMTP id d9443c01a7336-2ad5b0e1346mr58078435ad.29.1771566883772; Thu, 19 Feb 2026 21:54:43 -0800 (PST) X-Received: by 2002:a17:902:ef52:b0:2aa:e6fa:2f67 with SMTP id d9443c01a7336-2ad5b0e1346mr58078275ad.29.1771566883313; Thu, 19 Feb 2026 21:54:43 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a6fa326sm197949665ad.1.2026.02.19.21.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 21:54:43 -0800 (PST) From: Taniya Das Date: Fri, 20 Feb 2026 11:24:22 +0530 Subject: [PATCH v3 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-gpucc_sm8750_v2-v3-3-6c5408564c3c@oss.qualcomm.com> References: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> In-Reply-To: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=Raedyltv c=1 sm=1 tr=0 ts=6997f724 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=-JMICv5YTLeUKPlIpiEA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIwMDA0OCBTYWx0ZWRfX4Xrs5UFmDBbN sebpTAedvAYT0VzONzlX7dGvhNmR9IgmOuOnB6tmkUPYWwUQffhb7xqVXa9ER0E8AgqeJh+E25o J7f+9K1pHKvYeDeKrBvzn6hSZ/TILFehSmwLEMm8uiVmRp7bAWE6oxCQqfP/79Go7L9F+pFnrr3 avo8C1gFaJhCEFmr4LdR6FMf/d0FKctX5yimPp43rP7Tpd+yBGt4MSnyIE57Nqze/RvGcu5dDXS CvDhbbSd6ZwHbOH0d8NX+9Df1ms2u0GwV8F9DIU/XvEJtObKMEO0gQjz6L0QUvFG9bFV39YjFkn yTlHlB9z2t63jqRSe6wRSJ/AStByMI449g+U3zf0xFhJIaSzhYZTwtln2eLNAPdJ/e0qH5/McBa ozw3p6UZHVu+z9DgoFUIupCl7b08tTMiDVD82QDU8FlF2pmu3Ks2Wl5ZWwhLmUcyavsQbnhLrhq mdSHiX5zkT53ISayytQ== X-Proofpoint-GUID: xMRbdUntMwJ0EzU_L9OXqgaJlrYLtYGF X-Proofpoint-ORIG-GUID: xMRbdUntMwJ0EzU_L9OXqgaJlrYLtYGF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_06,2026-02-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602200048 From: Konrad Dybcio Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 64 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index f56b1f889b857a28859910f5c4465c8ce3473b00..0cc931d0bc96e9563ce4e7989ec= d4ba50bd424f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4,7 +4,9 @@ */ =20 #include +#include #include +#include #include #include #include @@ -3001,6 +3003,30 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm8750-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; @@ -4515,6 +4541,44 @@ tpdm_swao_out: endpoint { }; }; =20 + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0x0 0x15000000 0x0 0x100000>; --=20 2.34.1