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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Nicolas Ferre , Claudiu Beznea , Thomas Gleixner , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Max Hsu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1795; i=max.hsu@sifive.com; h=from:subject:message-id; bh=YJgGJZFBEeFnKwCZBKtMF/4z3f6ENQ0IR89Zow+dMes=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBpmBr8Oji0/4OVhQOIUlKAIgJBQ5IPR4YxPGYhh goHXM5+HRiJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCaZga/AAKCRDSA/2dB3lA vdGEDACBZOQzifNbSjKgt1DwPNhFpnL3Bj+UAEIr0weXbZ7rZsZ2J71Bn7D2TjtbPF6gSUQh9TB u23Gvon4ro7QrbdH9K+Sg9Dhe50X7LjXj978B2jLf48Jb2xVvo32OBNuvHZidvgOv5ZGsuMvfak xlX0HB2czT1jn/Orh1i/zz1UW4/pMcGGgOhZ4/BMg6LutjuEic9quiKJo+oXqeBwySJmq4RTVbK zC87a0yqs40PXIHgUC76c9JjqspvRjEFVXRqY9vYgi5DQhRPOZIrjO196ZK6WDj5vrVT67yCkEc gRZeiums12ErPNalqrAOMceY3J1vHscNh2BzhAUmh50Hztck0BMHRc7TO/S/ExWT4yXFbwA2pfy 41fHmAxMxpliC7zdowFN4ftLDrnxI05dS31ML9SgUoz82WPlypMS47DOw3bPrIMeI95HF3zRgDM 7QdyG5280seME+oT3I9NUn6bVru2yTmihfXUlKeQs+7F+34waoB8I+wODhRbKVuwkaRpY= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Add the SiFive FU740-C000 ethernet controller compatible string to the Cadence MACB binding documentation. The FU740 ethernet controller uses the same GEMGXL management block as the FU540, which is tightly coupled with the Cadence MACB IP. This follows the SiFive IP versioning scheme which requires SoC-specific compatible strings for proper hardware identification. Signed-off-by: Max Hsu --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documen= tation/devicetree/bindings/net/cdns,macb.yaml index cb14c35ba996..b46dde1da170 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -63,6 +63,7 @@ properties: - mobileye,eyeq5-gem # Mobileye EyeQ5 SoCs - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet = interface - sifive,fu540-c000-gem # SiFive FU540-C000 SoC + - sifive,fu740-c000-gem # SiFive FU740-C000 SoC =20 - items: - enum: @@ -74,7 +75,7 @@ properties: minItems: 1 items: - description: Basic register set - - description: GEMGXL Management block registers on SiFive FU540-C00= 0 SoC + - description: GEMGXL Management block registers on SiFive FU540/FU7= 40 SoCs =20 interrupts: minItems: 1 @@ -181,7 +182,9 @@ allOf: properties: compatible: contains: - const: sifive,fu540-c000-gem + enum: + - sifive,fu540-c000-gem + - sifive,fu740-c000-gem then: properties: reg: --=20 2.43.0 From nobody Fri Apr 3 11:12:47 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A83F33556E for ; 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Fri, 20 Feb 2026 00:28:00 -0800 (PST) Received: from [127.0.1.1] ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796a6c1bfsm54717688f8f.13.2026.02.20.00.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Feb 2026 00:27:59 -0800 (PST) From: Max Hsu Date: Fri, 20 Feb 2026 16:27:06 +0800 Subject: [PATCH 2/5] dt-bindings: interrupt-controller: Add SiFive FU740-C000 PLIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-fu740-v1-2-c8af54130c58@sifive.com> References: <20260220-fu740-v1-0-c8af54130c58@sifive.com> In-Reply-To: <20260220-fu740-v1-0-c8af54130c58@sifive.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Nicolas Ferre , Claudiu Beznea , Thomas Gleixner , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Max Hsu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1136; i=max.hsu@sifive.com; h=from:subject:message-id; bh=+TEwwtm2PIIgCWLeUnV15+Q2Dgy5dOcAStHu0XOpeeI=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBpmBr8cO7VEZscQY0zwzt3wIUXXTtpZ7n9utbAR BIceK0tIVCJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCaZga/AAKCRDSA/2dB3lA vacmDACN3HpL09hYqpED9ADdDNvaGs2XPvXqwYYTw4Q8Gi2omOHC6ANk2+p4FIhtZGNWF1DCAXW 39uj6PCsaAmKbD0AlImrsZehkQstr8ZxWWGSyF/A8lHHiUo72DALiy0f9Le5/Q7lFP1WHxEKJUD ZB/tvXmGE1zaH8Xd9zyDy+Y+TtCzTSjsS7TJIDvWWI5ty1XBDwgu74OIl/Oj4mNYXsuLRMQhs+o kIFTfsAkwm3m69y8ehbu/866xrxHAwczikLK7CJKOC+yz8Nuh6TiiFxtkhIJhyglChhwP4Omg/R mBRwMMWjgrZzJrja9MRKAKqz7McqQ9klazip2tG+OqdK1A+I9ohjvjSDUYv7WHeuTYLppErpejq JgjnKzhh5jHNt0eCX8LimCCjkAMKZU17YdierhFwYY2/WHBZIWTT0U66retiUgH7QJLo0AUwCHu 1jQYUohMD0CTJtilFGYcx7r/3kBgSXpUhuPyuxLFvU2Mks8SEjk3cI+0d6YRBC6L9eR8w= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Add the SiFive FU740-C000 PLIC compatible string to the binding documentation. This follows the SiFive IP versioning scheme which requires SoC-specific compatible strings for proper hardware identification, even when the IP blocks are functionally identical. Signed-off-by: Max Hsu Acked-by: Conor Dooley --- .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index e0267223887e..351d26ab1956 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -63,6 +63,7 @@ properties: - eswin,eic7700-plic - microchip,pic64gx-plic - sifive,fu540-c000-plic + - sifive,fu740-c000-plic - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic --=20 2.43.0 From nobody Fri Apr 3 11:12:47 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4B2732C939 for ; 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Fri, 20 Feb 2026 00:28:06 -0800 (PST) Received: from [127.0.1.1] ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796a6c1bfsm54717688f8f.13.2026.02.20.00.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Feb 2026 00:28:06 -0800 (PST) From: Max Hsu Date: Fri, 20 Feb 2026 16:27:07 +0800 Subject: [PATCH 3/5] net: macb: Add support for SiFive FU740-C000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-fu740-v1-3-c8af54130c58@sifive.com> References: <20260220-fu740-v1-0-c8af54130c58@sifive.com> In-Reply-To: <20260220-fu740-v1-0-c8af54130c58@sifive.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Nicolas Ferre , Claudiu Beznea , Thomas Gleixner , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Max Hsu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2939; i=max.hsu@sifive.com; h=from:subject:message-id; bh=0m9SXNeE/1HuxmVVgd6EQeU2mfVVz/U5fwVARClwTUI=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBpmBr8KrQfSF56ZFRp7zsifCcNkjxhIe9isJ/dR /Xauu9FbtqJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCaZga/AAKCRDSA/2dB3lA vY0fC/9G0xFFMdVahjzntxTBBBwK1F7PW8C7zDUURKiLa8PkirTxJxTourqf4rQb2XgFbwLO0rN us4GMZapSvbla4BFvmyqGflep/5R/NUytr0oUofbP+aszYNwhy64wx+9EsJ8m06/dawIB6Ijc0i v4NFVg9sY/qP/AvpcNnza98E35pHbJrRPzkkla5r/RuOYDOZmqahA7xNbeR68Bhl5CYfs5OK0uU hz+bQGglKUjorGsOdwVMXVSfnAzhzssdWBYS1dpwN/mw8vSwHSTcyK/No3seAEFAAtxkDll8c58 EqMwp00Fn4lQwl3cRrNCMvL7gK0e8olM3Yj7ZWt9clJf+phxFQibD6hu4Qk6af224t9ZaFN2IM/ 8P7vdlJRFc6wUcSrx2a8yMSJXpl9ARr15zMKVOmOERjn4mOuBVA6iAVC5Vb1EXEgGUvqD3hkMAe tsXWsIwDXasWBbXpx+Ny84ejE0h8Plckd3fkHi9XhHKJXsYjAXFaJCYf6aVAQpczzEkQQ= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Add a distinct configuration for the SiFive FU740-C000 ethernet controller to comply with the SiFive IP versioning guidelines. The FU740 ethernet controller uses the same management IP block as the FU540, which is tightly coupled with the Cadence MACB IP and manages boundary signals. To avoid code duplication while maintaining distinct SoC identification, this patch: - Renames sifive_fu540_macb_mgmt to sifive_macb_mgmt to reflect that it's shared between FU540 and FU740 - Adds a fu740_c000_config structure that reuses the FU540 initialization functions - Follows the established pattern in this driver where multiple SoC configs share the same init functions Signed-off-by: Max Hsu --- drivers/net/ethernet/cadence/macb_main.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index 43cd013bb70e..10d049391a73 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -39,8 +39,8 @@ #include #include "macb.h" =20 -/* This structure is only used for MACB on SiFive FU540 devices */ -struct sifive_fu540_macb_mgmt { +/* This structure is used for MACB on SiFive FU540/FU740 devices */ +struct sifive_macb_mgmt { void __iomem *reg; unsigned long rate; struct clk_hw hw; @@ -4650,7 +4650,7 @@ static const struct macb_usrio_config macb_default_us= rio =3D { /* max number of receive buffers */ #define AT91ETHER_MAX_RX_DESCR 9 =20 -static struct sifive_fu540_macb_mgmt *mgmt; +static struct sifive_macb_mgmt *mgmt; =20 static int at91ether_alloc_coherent(struct macb *lp) { @@ -5236,6 +5236,16 @@ static const struct macb_config fu540_c000_config = =3D { .usrio =3D &macb_default_usrio, }; =20 +static const struct macb_config fu740_c000_config =3D { + .caps =3D MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, + .dma_burst_length =3D 16, + .clk_init =3D fu540_c000_clk_init, + .init =3D fu540_c000_init, + .jumbo_max_len =3D 10240, + .usrio =3D &macb_default_usrio, +}; + static const struct macb_config at91sam9260_config =3D { .caps =3D MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, .clk_init =3D macb_clk_init, @@ -5411,6 +5421,7 @@ static const struct of_device_id macb_dt_ids[] =3D { { .compatible =3D "cdns,zynqmp-gem", .data =3D &zynqmp_config}, /* deprec= ated */ { .compatible =3D "cdns,zynq-gem", .data =3D &zynq_config }, /* deprecate= d */ { .compatible =3D "sifive,fu540-c000-gem", .data =3D &fu540_c000_config }, + { .compatible =3D "sifive,fu740-c000-gem", .data =3D &fu740_c000_config }, { .compatible =3D "microchip,mpfs-macb", .data =3D &mpfs_config }, { .compatible =3D "microchip,sama7g5-gem", .data =3D &sama7g5_gem_config = }, { .compatible =3D "microchip,sama7g5-emac", .data =3D &sama7g5_emac_confi= g }, --=20 2.43.0 From nobody Fri Apr 3 11:12:47 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F42933556E for ; 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Fri, 20 Feb 2026 00:28:13 -0800 (PST) Received: from [127.0.1.1] ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796a6c1bfsm54717688f8f.13.2026.02.20.00.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Feb 2026 00:28:12 -0800 (PST) From: Max Hsu Date: Fri, 20 Feb 2026 16:27:08 +0800 Subject: [PATCH 4/5] riscv: dts: sifive: fu740: Use correct ethernet compatible string Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-fu740-v1-4-c8af54130c58@sifive.com> References: <20260220-fu740-v1-0-c8af54130c58@sifive.com> In-Reply-To: <20260220-fu740-v1-0-c8af54130c58@sifive.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Nicolas Ferre , Claudiu Beznea , Thomas Gleixner , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Max Hsu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1012; i=max.hsu@sifive.com; h=from:subject:message-id; bh=A1K63zp8qaSu12/rz2C04BAncHqq+vlSUPdPl98mUA8=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBpmBr8b2XrUrBxDXHt5A67Hwwa7ka+Ty9EZgdkQ 7WSQEVEN1eJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCaZga/AAKCRDSA/2dB3lA ve0TDACsrXUlZYiA3LTQB96Ic/SvGiR39+u7jjo1RB8zDPY1fFcdIlM9ICXPe+VMcFkE0MJlwSz eSI4zgllduH5jMJBLGiVlFzhCkKG7r8LyrHyB+j+U+MY12Jioy7EGWP7uEdzokTTZBEABG6ft48 OP7yapHigO+rIauXOp0snpDXnPRS4cA23v5t1/bGBeYWjJtrcpxDEfCIXHn0gcraFlWLAL11Pzh TMos7QkH9T1+whYSbQn6Ne8Pa2XfYaDbXynLLQCOptWUYRugy2DyTkYaaoKxFCRqFZUlHh38PJr DeXHrbyE3PpDPnS4PY0X+O3HCDFkiCfUyWe7rinj7YwZtte+BzrP1JAAzO5/n/pIsYS4CgPfw81 3fxEBh0OY6uFUXTwj+FE8Uq1ZYko4KmaI9WBuSIQ00+nn/bijbxhRF3Aj2FIVv1bY/aCr2vDhfG UuoKrPQGX6nNz2NXw/tTQP4LXv/sV2yA0xGGYmNbapDjDybxtl9CFyahUAByOTbNPO5x8= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Update the ethernet node compatible string from "sifive,fu540-c000-gem" to "sifive,fu740-c000-gem" to comply with the SiFive IP versioning scheme documented in sifive-blocks-ip-versioning.txt. The versioning scheme requires SoC-specific compatible strings even when IP blocks are functionally identical. Signed-off-by: Max Hsu --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/d= ts/sifive/fu740-c000.dtsi index 6150f3397bff..15e11a03582a 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -273,7 +273,7 @@ spi0: spi@10050000 { status =3D "disabled"; }; eth0: ethernet@10090000 { - compatible =3D "sifive,fu540-c000-gem"; + compatible =3D "sifive,fu740-c000-gem"; interrupt-parent =3D <&plic0>; interrupts =3D <55>; reg =3D <0x0 0x10090000 0x0 0x2000>, --=20 2.43.0 From nobody Fri Apr 3 11:12:47 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B468030DEBD for ; Fri, 20 Feb 2026 08:28:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 20 Feb 2026 00:28:19 -0800 (PST) Received: from [127.0.1.1] ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796a6c1bfsm54717688f8f.13.2026.02.20.00.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Feb 2026 00:28:19 -0800 (PST) From: Max Hsu Date: Fri, 20 Feb 2026 16:27:09 +0800 Subject: [PATCH 5/5] riscv: dts: sifive: fu740: Use correct PLIC compatible string Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-fu740-v1-5-c8af54130c58@sifive.com> References: <20260220-fu740-v1-0-c8af54130c58@sifive.com> In-Reply-To: <20260220-fu740-v1-0-c8af54130c58@sifive.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Nicolas Ferre , Claudiu Beznea , Thomas Gleixner , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Max Hsu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1052; i=max.hsu@sifive.com; h=from:subject:message-id; bh=4GANKwuw4Gmvjt4yzo6mJduIJtLD4oH0IHu2XPGqRsA=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBpmBr8A5x0AN6WLq/BdWL/ZvvVR001n1rPKS373 hQAgd5vgOmJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCaZga/AAKCRDSA/2dB3lA vUkOC/0emc5DX/XLv6NvlYCRNIsC14BaTvJqWzTvJMubMPLS86hHgd3FKQ7Uyb58051WiOLwAsz cZ5AXNu8PWhFfZ+5aMcENxul9NU7y/aIYoD/m7oTozg+qnQ/Auiuw+sA68uBPKrR+nloV55s2/4 y4L0wfIX9asSx+Wx1H9rVEWCSt0F7vyAJw2ZPxe63ySqy5Xo94rukEpaYDcUb2eCyNT7bpjyiv4 BWMESgWKFLD4SERy6CSScQ8HgNkc9cuYdPLH/28EmfXvLqeiZtlAfcCmFbdRQdUQcXCnTiw8IyU bHvBM5KnFqNqVI4WlO2dSppzOYM+1fUoyYNHls4yC0x3v7XZpkZUvvniJ+wfD2ySZ9SmdhwOSx9 nlEe39EPyWVPTjorh6pmsmrTHzcdAhma1I3FuhiD4+WjzpcJYmH5mhmY4jIifqvSgffVzDRpohV 99j6p2JFWXqHmVfIA9TtlV+Uai6/eMHYdklOUmBQQKzTSc1q0dMYAPOUoVbPxQ7Nurf7A= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Update the PLIC compatible string from "sifive,fu540-c000-plic" to "sifive,fu740-c000-plic" to comply with the SiFive IP versioning scheme documented in sifive-blocks-ip-versioning.txt. The versioning scheme requires SoC-specific compatible strings for proper hardware identification. Signed-off-by: Max Hsu --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/d= ts/sifive/fu740-c000.dtsi index 15e11a03582a..a44ccbf4822b 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -182,7 +182,7 @@ soc { plic0: interrupt-controller@c000000 { #interrupt-cells =3D <1>; #address-cells =3D <0>; - compatible =3D "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; + compatible =3D "sifive,fu740-c000-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xc000000 0x0 0x4000000>; riscv,ndev =3D <69>; interrupt-controller; --=20 2.43.0