From nobody Fri Apr 3 12:36:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 405402FCBF5; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771605988; cv=none; b=HuhqGs84OM5dBRFW+bfk0j3dLJYVr2ijMXp8l8T/t78ME0x/WtcyVVecJR3+E9CpWXpS97sY9CBgBSVaLcfqV29EE8l29ABU1aPj9ac8N3ipXOFuDun9U6qgsuZLx/+EF/I4I/bSGFrPlNfvaVGSfRYZYYnWfUfMoV3ZbCwxpEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771605988; c=relaxed/simple; bh=qGfD1H4x6YjZ8VNUBNKxT4RPDbKQRKosiRwLjGpb5SE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZNbsu6OpQcRvCEZ6Zf30268gH+g7it4wD9zQuLtZO8RTAiWniRlHP4+W9cQJ5Qqy+JylVpxsp0VF3ESk5LUsXbgPvAjNoFjt5OG75rcl0YJgcgacvsev4439hKaYd0kbJOYEA3dWFAtOW7vQRHfmN72iV4nEUzZ7JbHfMSZlPtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kpnEPuYC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kpnEPuYC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1058CC116C6; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771605988; bh=qGfD1H4x6YjZ8VNUBNKxT4RPDbKQRKosiRwLjGpb5SE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kpnEPuYCkniwlitVqjGHkCNhQatz+g5jIn0BCbSJzTXDo82HfP4Fi1eXsqyefUQW0 vAhBx8hLVX1VNhEsFDtzK7p4fdRbb2CSFdny06UMscVNDh5dprhKDGIOmJrL2yiNIv CvV+keILB197L61IvNOenZltt/9eYq7Mb5GJLkE5IYbMpq0ktqrOkUBGE8rvInT4jf liDpHK1WEleK7oz77/G8Gz/TKkmiF45CCpY51mug4ZvZCzHwU5k1qfOsxFg/aCcSo3 AIGzoaLhEK2EsRnjmRjBZob0rj1e3js7DnFeYZeyXAwSvKg4of3C3cO0iAOsw9vZk5 aWGcTK9awXvyg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07811C5AD2B; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Fri, 20 Feb 2026 16:46:10 +0000 Subject: [PATCH RFC 6/8] iio: frequency: ad9910: add RAM mode support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-6-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=24545; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=40I0rilF1cHROAoMlCMzfANWq5mVGiNIdWyQOhmms9c=; b=VvkTsGZI/KknPTpJ6PpEwHZMg41CzEw4eJh6QVnAG0FyZ116KzVuLojAIM9qIpfB/tOvbUrq4 XQ04+jWCktXBISaHrvtQcjZ1GujuE3GyKBkUl8/VOO2XsGau7FR9U56 X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add RAM channel with support for profile-based control. This includes: - RAM data loading via binary sysfs attribute (ram_data); - Per-profile RAM configuration (start/end address, step rate, operating mode, dwell control); - RAM destination control (frequency, phase, amplitude, polar); - RAM operating modes (direct switch, ramp up, bidirectional ramp, continuous bidirectional, continuous recirculate); - Profile switching for RAM playback; - Sampling frequency control via profile step rate; - ram_en-aware read/write paths that redirect single tone frequency/phase/amplitude access through reg_profile cache when RAM is active; When RAM is enabled, the DDS core parameters (frequency, phase, amplitude) for the single tone channel are sourced from a shadow register cache (reg_profile[]) since the profile registers are repurposed for RAM control. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 474 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 455 insertions(+), 19 deletions(-) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index 84698bf2dc4e..8fd7ebe7e6b0 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -150,6 +150,15 @@ #define AD9910_PROFILE_ST_POW_MSK GENMASK_ULL(47, 32) #define AD9910_PROFILE_ST_FTW_MSK AD9910_REG_LOW32_MSK =20 +/* Profile Register Format (RAM Mode) */ +#define AD9910_PROFILE_RAM_OPEN_MSK GENMASK_ULL(61, 57) +#define AD9910_PROFILE_RAM_STEP_RATE_MSK GENMASK_ULL(55, 40) +#define AD9910_PROFILE_RAM_END_ADDR_MSK GENMASK_ULL(39, 30) +#define AD9910_PROFILE_RAM_START_ADDR_MSK GENMASK_ULL(23, 14) +#define AD9910_PROFILE_RAM_NO_DWELL_HIGH_MSK BIT_ULL(5) +#define AD9910_PROFILE_RAM_ZERO_CROSSING_MSK BIT_ULL(3) +#define AD9910_PROFILE_RAM_MODE_CONTROL_MSK GENMASK_ULL(2, 0) + /* Device constants */ #define AD9910_PI_NANORAD 3141592653UL =20 @@ -164,6 +173,14 @@ #define AD9910_NUM_PROFILES 8 =20 #define AD9910_DRG_DEST_NUM 3 +#define AD9910_RAM_DEST_NUM 4 + +#define AD9910_RAM_SIZE_MAX_WORDS 1024 +#define AD9910_RAM_WORD_SIZE sizeof(u32) +#define AD9910_RAM_SIZE_MAX_BYTES (AD9910_RAM_SIZE_MAX_WORDS * AD9910_RAM_= WORD_SIZE) +#define AD9910_RAM_ADDR_MAX (AD9910_RAM_SIZE_MAX_WORDS - 1) + +#define AD9910_RAM_PROFILE_CTL_CONT_MSK BIT(4) =20 /* PLL constants */ #define AD9910_PLL_MIN_N 12 @@ -208,6 +225,7 @@ enum ad9910_channel { AD9910_CHANNEL_SINGLE_TONE, AD9910_CHANNEL_PARALLEL_PORT, AD9910_CHANNEL_DRG, + AD9910_CHANNEL_RAM, }; =20 /** @@ -235,6 +253,27 @@ enum ad9910_drg_oper_mode { AD9910_DRG_OPER_MODE_BIDIR_CONT, }; =20 +/** + * enum ad9910_ram_oper_mode - AD9910 RAM Playback Operating Mode + * + * @AD9910_RAM_MODE_DIRECT_SWITCH: Direct profile switching between profil= es + * @AD9910_RAM_MODE_RAMP_UP: Ramp up for current profile + * @AD9910_RAM_MODE_BIDIR: Ramp up/down for profile 0 + * @AD9910_RAM_MODE_BIDIR_CONT: Continuous ramp up/down for current profile + * @AD9910_RAM_MODE_RAMP_UP_CONT: Continuous ramp up for current profile + * @AD9910_RAM_MODE_SEQ: Sequenced playback of RAM profiles up to target p= rofile + * @AD9910_RAM_MODE_SEQ_CONT: Continuous sequenced playback of RAM profiles + */ +enum ad9910_ram_oper_mode { + AD9910_RAM_MODE_DIRECT_SWITCH, + AD9910_RAM_MODE_RAMP_UP, + AD9910_RAM_MODE_BIDIR, + AD9910_RAM_MODE_BIDIR_CONT, + AD9910_RAM_MODE_RAMP_UP_CONT, + AD9910_RAM_MODE_SEQ, + AD9910_RAM_MODE_SEQ_CONT, +}; + enum { AD9910_PROFILE, AD9910_POWERDOWN, @@ -256,6 +295,8 @@ enum { AD9910_DRG_AMP_DEC_STEP, AD9910_DRG_INC_STEP_RATE, AD9910_DRG_DEC_STEP_RATE, + AD9910_RAM_START_ADDR, + AD9910_RAM_END_ADDR, }; =20 struct ad9910_data { @@ -294,6 +335,13 @@ struct ad9910_state { u16 val16; } reg[AD9910_REG_NUM_CACHED]; =20 + /* + * alternate profile registers used to store RAM profile settings when + * RAM mode is disabled and Single Tone profile settings when RAM mode + * is enabled. + */ + u64 reg_profile[AD9910_NUM_PROFILES]; + /* * Lock for accessing device registers and state variables. */ @@ -331,6 +379,16 @@ static const char * const ad9910_drg_oper_mode_str[] = =3D { [AD9910_DRG_OPER_MODE_BIDIR_CONT] =3D "bidirectional_continuous", }; =20 +static const char * const ad9910_ram_oper_mode_str[] =3D { + [AD9910_RAM_MODE_DIRECT_SWITCH] =3D "direct_switch", + [AD9910_RAM_MODE_RAMP_UP] =3D "ramp_up", + [AD9910_RAM_MODE_BIDIR] =3D "bidirectional", + [AD9910_RAM_MODE_BIDIR_CONT] =3D "bidirectional_continuous", + [AD9910_RAM_MODE_RAMP_UP_CONT] =3D "ramp_up_continuous", + [AD9910_RAM_MODE_SEQ] =3D "sequenced", + [AD9910_RAM_MODE_SEQ_CONT] =3D "sequenced_continuous", +}; + /** * ad9910_rational_scale() - Perform scaling of input given a reference. * @input: The input value to be scaled. @@ -377,6 +435,18 @@ static inline int ad9910_spi_write(struct ad9910_state= *st, u8 reg, size_t len, return ret; } =20 +static inline int ad9910_ram_load(struct ad9910_state *st, void *data, + size_t count) +{ + struct spi_transfer t[] =3D { + { .tx_buf =3D st->buf, .len =3D 1, }, + { .tx_buf =3D data, .len =3D count, }, + }; + + st->buf[0] =3D AD9910_REG_RAM; + return spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); +} + #define AD9910_REG_READ_FN(nb) \ static inline int ad9910_reg##nb##_read(struct ad9910_state *st, \ u8 reg, u##nb * data) \ @@ -464,6 +534,14 @@ static int ad9910_chan_destination_set(struct iio_dev = *indio_dev, AD9910_CFR2_DRG_DEST_MSK, FIELD_PREP(AD9910_CFR2_DRG_DEST_MSK, val), true); + case AD9910_CHANNEL_RAM: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + return -EBUSY; + + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_RAM_PLAYBACK_DEST_MSK, + FIELD_PREP(AD9910_CFR1_RAM_PLAYBACK_DEST_MSK, val), + true); default: return -EINVAL; } @@ -480,6 +558,9 @@ static int ad9910_chan_destination_get(struct iio_dev *= indio_dev, case AD9910_CHANNEL_DRG: return FIELD_GET(AD9910_CFR2_DRG_DEST_MSK, st->reg[AD9910_REG_CFR2].val32); + case AD9910_CHANNEL_RAM: + return FIELD_GET(AD9910_CFR1_RAM_PLAYBACK_DEST_MSK, + st->reg[AD9910_REG_CFR1].val32); default: return -EINVAL; } @@ -510,6 +591,93 @@ static int ad9910_drg_oper_mode_get(struct iio_dev *in= dio_dev, st->reg[AD9910_REG_CFR2].val32); } =20 +static int ad9910_ram_oper_mode_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + u32 profile_ctl; + int ret; + + guard(mutex)(&st->lock); + + /* + * RAM sequenced modes use the internal profile control: + * - Sequence mode takes precedence over regular profile modes + * - Active profile defines the internal profile control target + * - Profile 0 cannot be used as sequenced mode target + * - Profile X cannot be set as sequenced mode target if another + * profile is currently set. + */ + profile_ctl =3D FIELD_GET(AD9910_CFR1_INT_PROFILE_CTL_MSK, + st->reg[AD9910_REG_CFR1].val32); + if (AD9910_RAM_PROFILE_CTL_CONT_MSK & profile_ctl) + profile_ctl =3D (profile_ctl & ~AD9910_RAM_PROFILE_CTL_CONT_MSK) + 1; + + if (val >=3D AD9910_RAM_MODE_SEQ) { + if (!st->profile) + return -EINVAL; + + if (profile_ctl && profile_ctl !=3D st->profile) + return -EBUSY; + + /* update profile control */ + profile_ctl =3D st->profile; + if (val =3D=3D AD9910_RAM_MODE_SEQ_CONT) + profile_ctl =3D AD9910_RAM_PROFILE_CTL_CONT_MSK | (profile_ctl - 1); + profile_ctl =3D FIELD_PREP(AD9910_CFR1_INT_PROFILE_CTL_MSK, profile_ctl); + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_INT_PROFILE_CTL_MSK, + profile_ctl, true); + } + + if (profile_ctl && profile_ctl =3D=3D st->profile) { + /* clear internal profile control */ + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_INT_PROFILE_CTL_MSK, + 0, true); + if (ret) + return ret; + } + + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32)) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + FIELD_PREP(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, val), + true); + + FIELD_MODIFY(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + &st->reg_profile[st->profile], val); + return 0; +} + +static int ad9910_ram_oper_mode_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + u32 profile_ctl; + bool seq_cont =3D false; + + guard(mutex)(&st->lock); + + profile_ctl =3D FIELD_GET(AD9910_CFR1_INT_PROFILE_CTL_MSK, + st->reg[AD9910_REG_CFR1].val32); + if (AD9910_RAM_PROFILE_CTL_CONT_MSK & profile_ctl) { + seq_cont =3D true; + profile_ctl =3D (profile_ctl & ~AD9910_RAM_PROFILE_CTL_CONT_MSK) + 1; + } + + if (profile_ctl && profile_ctl =3D=3D st->profile) + return (seq_cont) ? AD9910_RAM_MODE_SEQ_CONT : AD9910_RAM_MODE_SEQ; + + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32)) + return FIELD_GET(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + return FIELD_GET(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + st->reg_profile[st->profile]); +} + static ssize_t ad9910_ext_info_read(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, @@ -532,6 +700,22 @@ static ssize_t ad9910_ext_info_read(struct iio_dev *in= dio_dev, val =3D BIT(FIELD_GET(AD9910_CFR2_FM_GAIN_MSK, st->reg[AD9910_REG_CFR2].val32)); break; + case AD9910_RAM_START_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + val =3D FIELD_GET(AD9910_PROFILE_RAM_START_ADDR_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + val =3D FIELD_GET(AD9910_PROFILE_RAM_START_ADDR_MSK, + st->reg_profile[st->profile]); + break; + case AD9910_RAM_END_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + val =3D FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + val =3D FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, + st->reg_profile[st->profile]); + break; default: return -EINVAL; } @@ -576,6 +760,33 @@ static ssize_t ad9910_ext_info_write(struct iio_dev *i= ndio_dev, AD9910_CFR2_FM_GAIN_MSK, val32, true); break; + case AD9910_RAM_START_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + return -EBUSY; + + if (val32 > AD9910_RAM_ADDR_MAX) + return -EINVAL; + + if (val32 > FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, + st->reg_profile[st->profile])) + FIELD_MODIFY(AD9910_PROFILE_RAM_END_ADDR_MSK, + &st->reg_profile[st->profile], val32); + + FIELD_MODIFY(AD9910_PROFILE_RAM_START_ADDR_MSK, + &st->reg_profile[st->profile], val32); + break; + case AD9910_RAM_END_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + return -EBUSY; + + if (val32 > AD9910_RAM_ADDR_MAX || + val32 < FIELD_GET(AD9910_PROFILE_RAM_START_ADDR_MSK, + st->reg_profile[st->profile])) + return -EINVAL; + + FIELD_MODIFY(AD9910_PROFILE_RAM_END_ADDR_MSK, + &st->reg_profile[st->profile], val32); + break; default: return -EINVAL; } @@ -967,6 +1178,20 @@ static const struct iio_enum ad9910_drg_oper_mode_enu= m =3D { .get =3D ad9910_drg_oper_mode_get, }; =20 +static const struct iio_enum ad9910_ram_destination_enum =3D { + .items =3D ad9910_destination_str, + .num_items =3D AD9910_RAM_DEST_NUM, + .set =3D ad9910_chan_destination_set, + .get =3D ad9910_chan_destination_get, +}; + +static const struct iio_enum ad9910_ram_oper_mode_enum =3D { + .items =3D ad9910_ram_oper_mode_str, + .num_items =3D ARRAY_SIZE(ad9910_ram_oper_mode_str), + .set =3D ad9910_ram_oper_mode_set, + .get =3D ad9910_ram_oper_mode_get, +}; + static const struct iio_chan_spec_ext_info ad9910_shared_ext_info[] =3D { AD9910_EXT_INFO("profile", AD9910_PROFILE, IIO_SHARED_BY_TYPE), AD9910_EXT_INFO("powerdown", AD9910_POWERDOWN, IIO_SHARED_BY_TYPE), @@ -1003,6 +1228,16 @@ static const struct iio_chan_spec_ext_info ad9910_dr= g_ext_info[] =3D { { }, }; =20 +static const struct iio_chan_spec_ext_info ad9910_ram_ext_info[] =3D { + IIO_ENUM("destination", IIO_SEPARATE, &ad9910_ram_destination_enum), + IIO_ENUM_AVAILABLE("destination", IIO_SEPARATE, &ad9910_ram_destination_e= num), + IIO_ENUM("operating_mode", IIO_SEPARATE, &ad9910_ram_oper_mode_enum), + IIO_ENUM_AVAILABLE("operating_mode", IIO_SEPARATE, &ad9910_ram_oper_mode_= enum), + AD9910_EXT_INFO("address_start", AD9910_RAM_START_ADDR, IIO_SEPARATE), + AD9910_EXT_INFO("address_end", AD9910_RAM_END_ADDR, IIO_SEPARATE), + { }, +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHANNEL_SINGLE_TONE] =3D { .type =3D IIO_ALTVOLTAGE, @@ -1032,6 +1267,18 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), .ext_info =3D ad9910_drg_ext_info, }, + [AD9910_CHANNEL_RAM] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_RAM, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_FREQUENCY) | + BIT(IIO_CHAN_INFO_PHASE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info =3D ad9910_ram_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -1040,10 +1287,13 @@ static int ad9910_read_raw(struct iio_dev *indio_de= v, { struct ad9910_state *st =3D iio_priv(indio_dev); u64 tmp64; - u32 tmp32; + u32 tmp32, ram_en; =20 guard(mutex)(&st->lock); =20 + ram_en =3D FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, + st->reg[AD9910_REG_CFR1].val32); + switch (info) { case IIO_CHAN_INFO_ENABLE: switch (chan->channel) { @@ -1055,30 +1305,77 @@ static int ad9910_read_raw(struct iio_dev *indio_de= v, *val =3D FIELD_GET(AD9910_CFR2_DRG_ENABLE_MSK, st->reg[AD9910_REG_CFR2].val32); break; + case AD9910_CHANNEL_RAM: + *val =3D ram_en; + break; default: return -EINVAL; } return IIO_VAL_INT; case IIO_CHAN_INFO_FREQUENCY: - tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, - st->reg[AD9910_REG_PROFILE(st->profile)].val64); + if (chan->channel =3D=3D AD9910_CHANNEL_SINGLE_TONE) { + if (!ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, + st->reg_profile[st->profile]); + } else { + tmp32 =3D st->reg[AD9910_REG_FTW].val32; + } tmp64 =3D (u64)tmp32 * st->data.sysclk_freq_hz; *val =3D upper_32_bits(tmp64); *val2 =3D upper_32_bits((u64)lower_32_bits(tmp64) * MICRO); return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_PHASE: - tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, - st->reg[AD9910_REG_PROFILE(st->profile)].val64); + if (chan->channel =3D=3D AD9910_CHANNEL_SINGLE_TONE) { + if (!ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, + st->reg_profile[st->profile]); + } else { + tmp32 =3D st->reg[AD9910_REG_POW].val16; + } tmp32 =3D ((u64)tmp32 * AD9910_MAX_PHASE_MICRORAD) >> 16; *val =3D tmp32 / MICRO; *val2 =3D tmp32 % MICRO; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_SCALE: - tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, - st->reg[AD9910_REG_PROFILE(st->profile)].val64); + if (chan->channel =3D=3D AD9910_CHANNEL_SINGLE_TONE) { + if (!ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, + st->reg_profile[st->profile]); + } else { + tmp32 =3D FIELD_GET(AD9910_ASF_SCALE_FACTOR_MSK, + st->reg[AD9910_REG_ASF].val32); + } *val =3D 0; *val2 =3D (u64)tmp32 * MICRO >> 14; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + switch (chan->channel) { + case AD9910_CHANNEL_RAM: + if (ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_RAM_STEP_RATE_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_RAM_STEP_RATE_MSK, + st->reg_profile[st->profile]); + break; + default: + return -EINVAL; + } + if (!tmp32) + return -ERANGE; + tmp32 *=3D 4; + *val =3D st->data.sysclk_freq_hz / tmp32; + *val2 =3D div_u64((u64)(st->data.sysclk_freq_hz % tmp32) * MICRO, tmp32); + return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; } @@ -1092,9 +1389,13 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, u64 tmp64; u32 tmp32; u16 tmp16; + int ram_en, ret =3D 0; =20 guard(mutex)(&st->lock); =20 + ram_en =3D FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, + st->reg[AD9910_REG_CFR1].val32); + switch (info) { case IIO_CHAN_INFO_ENABLE: val =3D val ? 1 : 0; @@ -1109,6 +1410,26 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, return ad9910_reg32_update(st, AD9910_REG_CFR2, AD9910_CFR2_DRG_ENABLE_MSK, tmp32, true); + case AD9910_CHANNEL_RAM: + if (ram_en =3D=3D val) + return 0; + + /* switch profile configs */ + for (int i =3D 0; i < AD9910_NUM_PROFILES; i++) { + tmp64 =3D st->reg[AD9910_REG_PROFILE(i)].val64; + ret =3D ad9910_reg64_write(st, + AD9910_REG_PROFILE(i), + st->reg_profile[i], + false); + if (ret) + return ret; + st->reg_profile[i] =3D tmp64; + } + + tmp32 =3D FIELD_PREP(AD9910_CFR1_RAM_ENABLE_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_RAM_ENABLE_MSK, + tmp32, true); default: return -EINVAL; } @@ -1118,10 +1439,18 @@ static int ad9910_write_raw(struct iio_dev *indio_d= ev, =20 tmp32 =3D ad9910_rational_scale((u64)val * MICRO + val2, BIT_ULL(32), (u64)MICRO * st->data.sysclk_freq_hz); - return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), - AD9910_PROFILE_ST_FTW_MSK, - FIELD_PREP(AD9910_PROFILE_ST_FTW_MSK, tmp32), - true); + if (chan->channel !=3D AD9910_CHANNEL_SINGLE_TONE) + return ad9910_reg32_write(st, AD9910_REG_FTW, tmp32, true); + + if (!ram_en) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_FTW_MSK, + FIELD_PREP(AD9910_PROFILE_ST_FTW_MSK, tmp32), + true); + + FIELD_MODIFY(AD9910_PROFILE_ST_FTW_MSK, + &st->reg_profile[st->profile], tmp32); + break; case IIO_CHAN_INFO_PHASE: tmp64 =3D (u64)val * MICRO + val2; if (val < 0 || val2 < 0 || tmp64 >=3D AD9910_MAX_PHASE_MICRORAD) @@ -1129,10 +1458,19 @@ static int ad9910_write_raw(struct iio_dev *indio_d= ev, =20 tmp32 =3D DIV_U64_ROUND_CLOSEST(tmp64 << 16, AD9910_MAX_PHASE_MICRORAD); tmp16 =3D min(tmp32, AD9910_POW_MAX); - return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), - AD9910_PROFILE_ST_POW_MSK, - FIELD_PREP(AD9910_PROFILE_ST_POW_MSK, tmp16), - true); + + if (chan->channel !=3D AD9910_CHANNEL_SINGLE_TONE) + return ad9910_reg16_write(st, AD9910_REG_POW, tmp16, true); + + if (!ram_en) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_POW_MSK, + FIELD_PREP(AD9910_PROFILE_ST_POW_MSK, tmp16), + true); + + FIELD_MODIFY(AD9910_PROFILE_ST_POW_MSK, + &st->reg_profile[st->profile], tmp16); + break; case IIO_CHAN_INFO_SCALE: if (val < 0 || val > 1 || (val =3D=3D 1 && val2 > 0)) return -EINVAL; @@ -1140,13 +1478,51 @@ static int ad9910_write_raw(struct iio_dev *indio_d= ev, tmp64 =3D ((u64)val * MICRO + val2) << 14; tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, MICRO); tmp16 =3D min(tmp64, AD9910_ASF_MAX); - return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), - AD9910_PROFILE_ST_ASF_MSK, - FIELD_PREP(AD9910_PROFILE_ST_ASF_MSK, tmp16), - true); + + if (chan->channel !=3D AD9910_CHANNEL_SINGLE_TONE) + return ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_SCALE_FACTOR_MSK, + FIELD_PREP(AD9910_ASF_SCALE_FACTOR_MSK, tmp16), + true); + + if (!ram_en) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_ASF_MSK, + FIELD_PREP(AD9910_PROFILE_ST_ASF_MSK, tmp16), + true); + + FIELD_MODIFY(AD9910_PROFILE_ST_ASF_MSK, + &st->reg_profile[st->profile], tmp16); + break; + case IIO_CHAN_INFO_SAMP_FREQ: + tmp64 =3D ((u64)val * MICRO + val2) * 4; + if (!tmp64) + return -EINVAL; + + tmp64 =3D DIV64_U64_ROUND_CLOSEST((u64)st->data.sysclk_freq_hz * MICRO, = tmp64); + tmp32 =3D clamp(tmp64, 1U, AD9910_STEP_RATE_MAX); + + switch (chan->channel) { + case AD9910_CHANNEL_RAM: + if (ram_en) { + tmp64 =3D FIELD_PREP(AD9910_PROFILE_RAM_STEP_RATE_MSK, tmp32); + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_RAM_STEP_RATE_MSK, + tmp64, true); + } + + FIELD_MODIFY(AD9910_PROFILE_RAM_STEP_RATE_MSK, + &st->reg_profile[st->profile], tmp32); + break; + default: + return -EINVAL; + } + break; default: return -EINVAL; } + + return ret; } =20 static int ad9910_write_raw_get_fmt(struct iio_dev *indio_dev, @@ -1159,6 +1535,7 @@ static int ad9910_write_raw_get_fmt(struct iio_dev *i= ndio_dev, case IIO_CHAN_INFO_FREQUENCY: case IIO_CHAN_INFO_PHASE: case IIO_CHAN_INFO_SCALE: + case IIO_CHAN_INFO_SAMP_FREQ: return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; @@ -1247,13 +1624,65 @@ static ssize_t sysclk_frequency_show(struct device = *dev, =20 static IIO_DEVICE_ATTR_RO(sysclk_frequency, 0); =20 +static ssize_t ram_data_write(struct file *filp, struct kobject *kobj, + const struct bin_attribute *attr, char *buf, + loff_t off, size_t count) +{ + struct ad9910_state *st =3D iio_priv(dev_to_iio_dev(kobj_to_dev(kobj))); + u64 tmp64, backup; + u32 start, end; + int ret, ret2; + + if (off + count > AD9910_RAM_SIZE_MAX_BYTES || !count || + off % AD9910_RAM_WORD_SIZE !=3D 0 || + count % AD9910_RAM_WORD_SIZE !=3D 0) + return -EINVAL; + + guard(mutex)(&st->lock); + + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32)) + return -EBUSY; + + /* ensure profile is selected */ + ret =3D ad9910_profile_set(st, st->profile); + if (ret) + return ret; + + /* backup profile register */ + backup =3D st->reg[AD9910_REG_PROFILE(st->profile)].val64; + start =3D off / AD9910_RAM_WORD_SIZE; + end =3D (off + count) / AD9910_RAM_WORD_SIZE - 1; + tmp64 =3D AD9910_PROFILE_RAM_STEP_RATE_MSK | + FIELD_PREP(AD9910_PROFILE_RAM_START_ADDR_MSK, start) | + FIELD_PREP(AD9910_PROFILE_RAM_END_ADDR_MSK, end); + ret =3D ad9910_reg64_write(st, AD9910_REG_PROFILE(st->profile), tmp64, tr= ue); + if (ret) + return ret; + + /* write ram data and restore profile register */ + ret =3D ad9910_ram_load(st, buf, count); + ret2 =3D ad9910_reg64_write(st, AD9910_REG_PROFILE(st->profile), backup, = true); + if (!ret) + ret =3D ret2; + + return ret ?: count; +} + +static const BIN_ATTR_WO(ram_data, AD9910_RAM_SIZE_MAX_BYTES); + static struct attribute *ad9910_attrs[] =3D { &iio_dev_attr_sysclk_frequency.dev_attr.attr, NULL }; =20 +static const struct bin_attribute *const ad9910_bin_attrs[] =3D { + &bin_attr_ram_data, + NULL +}; + static const struct attribute_group ad9910_attrs_group =3D { .attrs =3D ad9910_attrs, + .bin_attrs =3D ad9910_bin_attrs, }; =20 static const struct iio_info ad9910_info =3D { @@ -1426,6 +1855,13 @@ static int ad9910_setup(struct ad9910_state *st, str= uct reset_control *dev_rst) if (ret) return ret; =20 + for (int i =3D 0; i < AD9910_NUM_PROFILES; i++) { + st->reg_profile[i] =3D AD9910_PROFILE_RAM_OPEN_MSK; + st->reg_profile[i] |=3D FIELD_PREP(AD9910_PROFILE_RAM_STEP_RATE_MSK, 1); + st->reg_profile[i] |=3D FIELD_PREP(AD9910_PROFILE_RAM_END_ADDR_MSK, + AD9910_RAM_ADDR_MAX); + } + return ad9910_io_update(st); } =20 --=20 2.43.0