From nobody Fri Apr 3 12:36:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C7692F746D; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771605988; cv=none; b=HNjBaUheqeHn2oN3Hx12Kt87onSrmwLdi9dNDm1g9wMBubVKx2oB8+yeCggfgaA/0h+YAou2Ge7bTTzKPTfr1EfY+yCx7mj+HmJGCMZ7VTVCydTpASIHm1dlSNJBvA3u9gEeYwciQVwUW2gdKbISZmbpgElDQjUZPG/WMw9XUus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771605988; c=relaxed/simple; bh=80Ttt9waVKnbzFusqMa1pdz3FceYeKKeLomVK8Af1Dk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DV34tJHq8HFSeLl5awm2Tr6AwRtAhFvvs8ydw8iK/EHy0AKwAhLR7reVgYvG9+JFCHvUq9qAfC0iVuzEif3abBgQ8WFKUrTBTfvWwgJku1nziVLe2c6P11UFVkQQDy7+GdY3mR9dmi1ON2lj5Sl/61QQyGZtBfFQEJoe5WXFAJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VY8qQs07; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VY8qQs07" Received: by smtp.kernel.org (Postfix) with ESMTPS id F0C15C2BCB5; Fri, 20 Feb 2026 16:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771605988; bh=80Ttt9waVKnbzFusqMa1pdz3FceYeKKeLomVK8Af1Dk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VY8qQs07NJePD4DD1rNozMMtzyjsJWhJeYYn/zWPWlWYuCymp1oaxiOnQmqHD8fgX rvufnVeJT612NQsKzPbAXgSildaafylmg9vZoKdga4cs9oUk+YXM4Ja4MMO1G+qkRt ppl2MvjBBuowmRn07vFZIBkPepBGOfJztWN7DXB544gtVVGd3kqQVdZ9Y5m4f5yDBA sMaWJ4wMBhlTPeFjdQwCfmShQensJf3EpZ3I/2Uy36mHN+zBx/Af6qcsf09MrX0vJl fKjg8IECqY7dS/Ljw+LJEvkTfxq2LEIRw9g8mBLQm6v/tyjQzF8GD9lDEBb2G3WSEI 0qT5FuDQ0/erQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E092EC5ACD3; Fri, 20 Feb 2026 16:46:27 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Fri, 20 Feb 2026 16:46:09 +0000 Subject: [PATCH RFC 5/8] iio: frequency: ad9910: add digital ramp generator support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-5-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=17752; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=izJCqqe/mjPLHctBorpLyiMP1dZRqD1NyGEif4TXAjw=; b=2IVfzeWafZ9tnV0QCz+Ju0CiRp6gWOSDBaaJ6nWuDC33d72ygpNw8qEUfZvntliTvaroSZHLg hiOvY7N6QV3CXkJbrTeszMLhadA8sVEV5crFYdyhAWiXcXUzICTLTAA X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add DRG channel with destination selection (frequency, phase, or amplitude), operating mode control, configurable upper/lower limits, increment/decrement step sizes, and step rate settings for the digital ramp generator. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 454 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 454 insertions(+) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index a72e3685f676..84698bf2dc4e 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -133,6 +133,18 @@ #define AD9910_MC_SYNC_OUTPUT_DELAY_MSK GENMASK(15, 11) #define AD9910_MC_SYNC_INPUT_DELAY_MSK GENMASK(7, 3) =20 +/* Digital Ramp Limit Register */ +#define AD9910_DRG_LIMIT_UPPER_MSK AD9910_REG_HIGH32_MSK +#define AD9910_DRG_LIMIT_LOWER_MSK AD9910_REG_LOW32_MSK + +/* Digital Ramp Step Register */ +#define AD9910_DRG_STEP_DEC_MSK AD9910_REG_HIGH32_MSK +#define AD9910_DRG_STEP_INC_MSK AD9910_REG_LOW32_MSK + +/* Digital Ramp Rate Register */ +#define AD9910_DRG_RATE_DEC_MSK GENMASK(31, 16) +#define AD9910_DRG_RATE_INC_MSK GENMASK(15, 0) + /* Profile Register Format (Single Tone Mode) */ #define AD9910_PROFILE_ST_ASF_MSK GENMASK_ULL(61, 48) #define AD9910_PROFILE_ST_POW_MSK GENMASK_ULL(47, 32) @@ -148,8 +160,11 @@ #define AD9910_ASF_PP_LSB_MAX (BIT(6) - 1) #define AD9910_POW_MAX (BIT(16) - 1) #define AD9910_POW_PP_LSB_MAX (BIT(8) - 1) +#define AD9910_STEP_RATE_MAX (BIT(16) - 1) #define AD9910_NUM_PROFILES 8 =20 +#define AD9910_DRG_DEST_NUM 3 + /* PLL constants */ #define AD9910_PLL_MIN_N 12 #define AD9910_PLL_MAX_N 127 @@ -192,6 +207,32 @@ enum ad9910_channel { AD9910_CHANNEL_SINGLE_TONE, AD9910_CHANNEL_PARALLEL_PORT, + AD9910_CHANNEL_DRG, +}; + +/** + * enum ad9910_destination - AD9910 DDS core parameter destination + */ +enum ad9910_destination { + AD9910_DEST_FREQUENCY, + AD9910_DEST_PHASE, + AD9910_DEST_AMPLITUDE, + AD9910_DEST_POLAR, +}; + +/** + * enum ad9910_drg_oper_mode - Digital Ramp Generator Operating Mode + * + * @AD9910_DRG_OPER_MODE_BIDIR: Normal Ramp Generation + * @AD9910_DRG_OPER_MODE_RAMP_DOWN: No-dwell Low only operation + * @AD9910_DRG_OPER_MODE_RAMP_UP: No-dwell High only operation + * @AD9910_DRG_OPER_MODE_BIDIR_CONT: Both No-dwell High/Low operation + */ +enum ad9910_drg_oper_mode { + AD9910_DRG_OPER_MODE_BIDIR, + AD9910_DRG_OPER_MODE_RAMP_DOWN, + AD9910_DRG_OPER_MODE_RAMP_UP, + AD9910_DRG_OPER_MODE_BIDIR_CONT, }; =20 enum { @@ -201,6 +242,20 @@ enum { AD9910_PP_FREQ_OFFSET, AD9910_PP_PHASE_OFFSET, AD9910_PP_AMP_OFFSET, + AD9910_DRG_FREQ_UPPER_LIMIT, + AD9910_DRG_FREQ_LOWER_LIMIT, + AD9910_DRG_FREQ_INC_STEP, + AD9910_DRG_FREQ_DEC_STEP, + AD9910_DRG_PHASE_UPPER_LIMIT, + AD9910_DRG_PHASE_LOWER_LIMIT, + AD9910_DRG_PHASE_INC_STEP, + AD9910_DRG_PHASE_DEC_STEP, + AD9910_DRG_AMP_UPPER_LIMIT, + AD9910_DRG_AMP_LOWER_LIMIT, + AD9910_DRG_AMP_INC_STEP, + AD9910_DRG_AMP_DEC_STEP, + AD9910_DRG_INC_STEP_RATE, + AD9910_DRG_DEC_STEP_RATE, }; =20 struct ad9910_data { @@ -262,6 +317,20 @@ static const char * const ad9910_refclk_out_drv0[] =3D= { "disabled", "low", "medium", "high", }; =20 +static const char * const ad9910_destination_str[] =3D { + [AD9910_DEST_FREQUENCY] =3D "frequency", + [AD9910_DEST_PHASE] =3D "phase", + [AD9910_DEST_AMPLITUDE] =3D "amplitude", + [AD9910_DEST_POLAR] =3D "polar", +}; + +static const char * const ad9910_drg_oper_mode_str[] =3D { + [AD9910_DRG_OPER_MODE_BIDIR] =3D "bidirectional", + [AD9910_DRG_OPER_MODE_RAMP_DOWN] =3D "ramp_down", + [AD9910_DRG_OPER_MODE_RAMP_UP] =3D "ramp_up", + [AD9910_DRG_OPER_MODE_BIDIR_CONT] =3D "bidirectional_continuous", +}; + /** * ad9910_rational_scale() - Perform scaling of input given a reference. * @input: The input value to be scaled. @@ -381,6 +450,66 @@ static int ad9910_powerdown_set(struct ad9910_state *s= t, bool enable) return gpiod_set_value_cansleep(st->gpio_pwdown, enable); } =20 +static int ad9910_chan_destination_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + switch (chan->channel) { + case AD9910_CHANNEL_DRG: + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_DRG_DEST_MSK, + FIELD_PREP(AD9910_CFR2_DRG_DEST_MSK, val), + true); + default: + return -EINVAL; + } +} + +static int ad9910_chan_destination_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + switch (chan->channel) { + case AD9910_CHANNEL_DRG: + return FIELD_GET(AD9910_CFR2_DRG_DEST_MSK, + st->reg[AD9910_REG_CFR2].val32); + default: + return -EINVAL; + } +} + +static int ad9910_drg_oper_mode_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_DRG_NO_DWELL_MSK, + FIELD_PREP(AD9910_CFR2_DRG_NO_DWELL_MSK, val), + true); +} + +static int ad9910_drg_oper_mode_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + return FIELD_GET(AD9910_CFR2_DRG_NO_DWELL_MSK, + st->reg[AD9910_REG_CFR2].val32); +} + static ssize_t ad9910_ext_info_read(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, @@ -546,6 +675,264 @@ static ssize_t ad9910_pp_attrs_write(struct iio_dev *= indio_dev, return ret ?: len; } =20 +static ssize_t ad9910_step_rate_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int vals[2]; + u32 tmp32; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_INC_STEP_RATE: + tmp32 =3D FIELD_GET(AD9910_DRG_RATE_INC_MSK, + st->reg[AD9910_REG_DRG_RATE].val32); + break; + case AD9910_DRG_DEC_STEP_RATE: + tmp32 =3D FIELD_GET(AD9910_DRG_RATE_DEC_MSK, + st->reg[AD9910_REG_DRG_RATE].val32); + break; + default: + return -EINVAL; + } + + if (tmp32 =3D=3D 0) + return -ERANGE; + + tmp32 *=3D 4; + vals[0] =3D st->data.sysclk_freq_hz / tmp32; + vals[1] =3D div_u64((u64)(st->data.sysclk_freq_hz % tmp32) * MICRO, tmp32= ); + + return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), va= ls); +} + +static ssize_t ad9910_step_rate_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + u64 rate_val; + u64 sysclk_uhz; + int ret; + + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + sysclk_uhz =3D (u64)st->data.sysclk_freq_hz * MICROHZ_PER_HZ; + rate_val =3D ((u64)val * MICROHZ_PER_HZ + val2) * 4; + if (rate_val =3D=3D 0 || rate_val > sysclk_uhz) + return -EINVAL; + + rate_val =3D min(DIV64_U64_ROUND_CLOSEST(sysclk_uhz, rate_val), + AD9910_STEP_RATE_MAX); + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_INC_STEP_RATE: + ret =3D ad9910_reg32_update(st, AD9910_REG_DRG_RATE, + AD9910_DRG_RATE_INC_MSK, + FIELD_PREP(AD9910_DRG_RATE_INC_MSK, rate_val), + true); + break; + case AD9910_DRG_DEC_STEP_RATE: + ret =3D ad9910_reg32_update(st, AD9910_REG_DRG_RATE, + AD9910_DRG_RATE_DEC_MSK, + FIELD_PREP(AD9910_DRG_RATE_DEC_MSK, rate_val), true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + +static ssize_t ad9910_drg_attrs_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + unsigned int type; + int vals[2]; + u64 tmp64; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_AMP_UPPER_LIMIT: + tmp64 =3D FIELD_GET(AD9910_DRG_LIMIT_UPPER_MSK, + st->reg[AD9910_REG_DRG_LIMIT].val64); + break; + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + tmp64 =3D FIELD_GET(AD9910_DRG_LIMIT_LOWER_MSK, + st->reg[AD9910_REG_DRG_LIMIT].val64); + break; + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_AMP_INC_STEP: + tmp64 =3D FIELD_GET(AD9910_DRG_STEP_INC_MSK, + st->reg[AD9910_REG_DRG_STEP].val64); + break; + case AD9910_DRG_FREQ_DEC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + tmp64 =3D FIELD_GET(AD9910_DRG_STEP_DEC_MSK, + st->reg[AD9910_REG_DRG_STEP].val64); + break; + default: + return -EINVAL; + } + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_FREQ_DEC_STEP: + type =3D IIO_VAL_INT_PLUS_MICRO; + tmp64 *=3D st->data.sysclk_freq_hz; + vals[0] =3D upper_32_bits(tmp64); + vals[1] =3D upper_32_bits((u64)lower_32_bits(tmp64) * MICRO); + break; + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + type =3D IIO_VAL_INT_PLUS_NANO; + tmp64 *=3D AD9910_PI_NANORAD; + tmp64 >>=3D 31; + vals[0] =3D div_u64_rem(tmp64, NANO, &vals[1]); + break; + case AD9910_DRG_AMP_UPPER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + case AD9910_DRG_AMP_INC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + type =3D IIO_VAL_INT_PLUS_NANO; + vals[0] =3D 0; + vals[1] =3D tmp64 * NANO >> 32; + break; + default: + return -EINVAL; + } + + return iio_format_value(buf, type, ARRAY_SIZE(vals), vals); +} + +static ssize_t ad9910_drg_attrs_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + u64 tmp64; + int ret; + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_FREQ_DEC_STEP: + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + if (val >=3D st->data.sysclk_freq_hz / 2) + return -EINVAL; + + tmp64 =3D (u64)val * MICRO + val2; + tmp64 =3D ad9910_rational_scale(tmp64, BIT_ULL(32), + (u64)MICRO * st->data.sysclk_freq_hz); + break; + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + ret =3D iio_str_to_fixpoint(buf, NANO / 10, &val, &val2); + if (ret) + return ret; + + if (val < 0 || val2 < 0) + return -EINVAL; + + tmp64 =3D (u64)val * NANO + val2; + if (tmp64 > 2ULL * AD9910_PI_NANORAD) + return -EINVAL; + + tmp64 <<=3D 31; + tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, AD9910_PI_NANORAD); + break; + case AD9910_DRG_AMP_UPPER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + case AD9910_DRG_AMP_INC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + ret =3D iio_str_to_fixpoint(buf, NANO / 10, &val, &val2); + if (ret) + return ret; + + if (val < 0 || val > 1 || (val =3D=3D 1 && val2 > 0)) + return -EINVAL; + + tmp64 =3D ((u64)val * NANO + val2) << 32; + tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, NANO); + break; + default: + return -EINVAL; + } + + tmp64 =3D min(tmp64, U32_MAX); + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_AMP_UPPER_LIMIT: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_LIMIT, + AD9910_DRG_LIMIT_UPPER_MSK, + FIELD_PREP(AD9910_DRG_LIMIT_UPPER_MSK, tmp64), + true); + break; + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_LIMIT, + AD9910_DRG_LIMIT_LOWER_MSK, + FIELD_PREP(AD9910_DRG_LIMIT_LOWER_MSK, tmp64), + true); + break; + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_AMP_INC_STEP: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_STEP, + AD9910_DRG_STEP_INC_MSK, + FIELD_PREP(AD9910_DRG_STEP_INC_MSK, tmp64), + true); + break; + case AD9910_DRG_FREQ_DEC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_STEP, + AD9910_DRG_STEP_DEC_MSK, + FIELD_PREP(AD9910_DRG_STEP_DEC_MSK, tmp64), + true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + #define AD9910_EXT_INFO_TMPL(_name, _ident, _shared, _fn_desc) { \ .name =3D _name, \ .read =3D ad9910_ ## _fn_desc ## _read, \ @@ -560,6 +947,26 @@ static ssize_t ad9910_pp_attrs_write(struct iio_dev *i= ndio_dev, #define AD9910_PP_EXT_INFO(_name, _ident) \ AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, pp_attrs) =20 +#define AD9910_STEP_RATE_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, step_rate) + +#define AD9910_DRG_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, drg_attrs) + +static const struct iio_enum ad9910_drg_destination_enum =3D { + .items =3D ad9910_destination_str, + .num_items =3D AD9910_DRG_DEST_NUM, + .set =3D ad9910_chan_destination_set, + .get =3D ad9910_chan_destination_get, +}; + +static const struct iio_enum ad9910_drg_oper_mode_enum =3D { + .items =3D ad9910_drg_oper_mode_str, + .num_items =3D ARRAY_SIZE(ad9910_drg_oper_mode_str), + .set =3D ad9910_drg_oper_mode_set, + .get =3D ad9910_drg_oper_mode_get, +}; + static const struct iio_chan_spec_ext_info ad9910_shared_ext_info[] =3D { AD9910_EXT_INFO("profile", AD9910_PROFILE, IIO_SHARED_BY_TYPE), AD9910_EXT_INFO("powerdown", AD9910_POWERDOWN, IIO_SHARED_BY_TYPE), @@ -574,6 +981,28 @@ static const struct iio_chan_spec_ext_info ad9910_pp_e= xt_info[] =3D { { }, }; =20 +static const struct iio_chan_spec_ext_info ad9910_drg_ext_info[] =3D { + IIO_ENUM("destination", IIO_SEPARATE, &ad9910_drg_destination_enum), + IIO_ENUM_AVAILABLE("destination", IIO_SEPARATE, &ad9910_drg_destination_e= num), + IIO_ENUM("operating_mode", IIO_SEPARATE, &ad9910_drg_oper_mode_enum), + IIO_ENUM_AVAILABLE("operating_mode", IIO_SEPARATE, &ad9910_drg_oper_mode_= enum), + AD9910_DRG_EXT_INFO("frequency_max", AD9910_DRG_FREQ_UPPER_LIMIT), + AD9910_DRG_EXT_INFO("frequency_min", AD9910_DRG_FREQ_LOWER_LIMIT), + AD9910_DRG_EXT_INFO("frequency_increment", AD9910_DRG_FREQ_INC_STEP), + AD9910_DRG_EXT_INFO("frequency_decrement", AD9910_DRG_FREQ_DEC_STEP), + AD9910_DRG_EXT_INFO("phase_max", AD9910_DRG_PHASE_UPPER_LIMIT), + AD9910_DRG_EXT_INFO("phase_min", AD9910_DRG_PHASE_LOWER_LIMIT), + AD9910_DRG_EXT_INFO("phase_increment", AD9910_DRG_PHASE_INC_STEP), + AD9910_DRG_EXT_INFO("phase_decrement", AD9910_DRG_PHASE_DEC_STEP), + AD9910_DRG_EXT_INFO("scale_max", AD9910_DRG_AMP_UPPER_LIMIT), + AD9910_DRG_EXT_INFO("scale_min", AD9910_DRG_AMP_LOWER_LIMIT), + AD9910_DRG_EXT_INFO("scale_increment", AD9910_DRG_AMP_INC_STEP), + AD9910_DRG_EXT_INFO("scale_decrement", AD9910_DRG_AMP_DEC_STEP), + AD9910_STEP_RATE_EXT_INFO("increment_sampling_frequency", AD9910_DRG_INC_= STEP_RATE), + AD9910_STEP_RATE_EXT_INFO("decrement_sampling_frequency", AD9910_DRG_DEC_= STEP_RATE), + { }, +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHANNEL_SINGLE_TONE] =3D { .type =3D IIO_ALTVOLTAGE, @@ -594,6 +1023,15 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), .ext_info =3D ad9910_pp_ext_info, }, + [AD9910_CHANNEL_DRG] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_DRG, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), + .ext_info =3D ad9910_drg_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -613,6 +1051,10 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, *val =3D FIELD_GET(AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, st->reg[AD9910_REG_CFR2].val32); break; + case AD9910_CHANNEL_DRG: + *val =3D FIELD_GET(AD9910_CFR2_DRG_ENABLE_MSK, + st->reg[AD9910_REG_CFR2].val32); + break; default: return -EINVAL; } @@ -662,6 +1104,11 @@ static int ad9910_write_raw(struct iio_dev *indio_dev, return ad9910_reg32_update(st, AD9910_REG_CFR2, AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, tmp32, true); + case AD9910_CHANNEL_DRG: + tmp32 =3D FIELD_PREP(AD9910_CFR2_DRG_ENABLE_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_DRG_ENABLE_MSK, + tmp32, true); default: return -EINVAL; } @@ -972,6 +1419,13 @@ static int ad9910_setup(struct ad9910_state *st, stru= ct reset_control *dev_rst) if (ret) return ret; =20 + /* configure step rate with default values */ + reg32 =3D FIELD_PREP(AD9910_DRG_RATE_DEC_MSK, 1) | + FIELD_PREP(AD9910_DRG_RATE_INC_MSK, 1); + ret =3D ad9910_reg32_write(st, AD9910_REG_DRG_RATE, reg32, false); + if (ret) + return ret; + return ad9910_io_update(st); } =20 --=20 2.43.0