From nobody Fri Apr 3 11:13:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E205B2C21DD; Fri, 20 Feb 2026 16:46:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771605988; cv=none; b=TjE4AEBV5MtdiAEarD6MAm6hqc+BvKhOGINzhKZtiZXfOR299yF1HY/aKysMY+/nBwEnzzGO03ZvW+N99kPjhp70JlFNUrfJVyeE9UC/40I3BxAFsDVn3CrIolTA76WVRIit1hzMcIpB+vJEhUxYMNG2OrvOXlM5Pe7d4Jkzkrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771605988; c=relaxed/simple; bh=8T/jMptybufGxRUxM7/5o85KlbStqb1sIH6Mta04ABQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Lw+mmff+CIfzuO79MiOICuPLvNRNAEBV/eZIdzFSlzi/aCUcOEtj4YQFEhy8wzHzJsLKOXaPWwO75hRZhWQhSYXyWmB7KP2Wvh7n5crQ8BqDd2XcOyO4+0ivoBWx+aKy8YHUAlEIhazxIys7uKvw4IkAeS1WjyRwdxz4Al7AIP8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KKATW7n0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KKATW7n0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 98F5AC19424; Fri, 20 Feb 2026 16:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771605987; bh=8T/jMptybufGxRUxM7/5o85KlbStqb1sIH6Mta04ABQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KKATW7n0IJlUihDEzszGpUFa74NcmMmT8ezLwA6RqIGuwOEkrnJJXqDHpj0K+UpWO g41027WvcBAx7XVitvZPx6rjRY9omwltw97VKWSwyKOA9D7Xi5L/EVN2p9jCCZarBu +4t7vjcNd/k4mf3wtvJgRY2Vdzg1K0yuMjv5QPiVtXZMXeTvBxuf0wV8if/T5zLoiT CN3fuWe94mrcPJwIfqRKlQEyYsQiz6d0FRYWVgHCDH7+VVVmhJLdnpTYdPRQozXDW2 EyqCrDfpf4y76P7DYvnERdFxxCTGRc26fgVTMI0gZxNVVPpH59ZjbLv5daAcxGhv0p j/FpgNscPtYDw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 830D3C5ACC1; Fri, 20 Feb 2026 16:46:27 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Fri, 20 Feb 2026 16:46:05 +0000 Subject: [PATCH RFC 1/8] dt-bindings: iio: frequency: add ad9910 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-1-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=8500; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=z//Z0l3LpZmXPafUE4JJ++VbXBpuP6Jb0ARDmbbi/9Y=; b=tMM1fBTnwN259oS02qmc1e9qaBf5eMxapoOfk4WKZ53XsXIq+5YpsFYSjJnoeOBwK9Ns1h9KH h6bGCA/6dJBAdyzA2s5KuTs3ndqq9rhkMZbhymgpDmZj14pknWgsxYq X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar DT-bindings for AD9910, a 1 GSPS DDS with 14-bit DAC. It includes configurations for the reference clock path, DAC current, reset and basic GPIO control. Signed-off-by: Rodrigo Alencar --- .../bindings/iio/frequency/adi,ad9910.yaml | 236 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 243 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,ad9910.yam= l b/Documentation/devicetree/bindings/iio/frequency/adi,ad9910.yaml new file mode 100644 index 000000000000..43b21d1428ba --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,ad9910.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,ad9910.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD9910 Direct Digital Synthesizer + +maintainers: + - Rodrigo Alencar + +description: + The AD9910 is a 1 GSPS direct digital synthesizer (DDS) with an integrat= ed + 14-bit DAC. It features single tone mode with 8 configurable profiles, + a digital ramp generator, RAM control, OSK, and a parallel data port for + high-speed streaming. + + https://www.analog.com/en/products/ad9910.html + +properties: + compatible: + const: adi,ad9910 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 70000000 + + clocks: + maxItems: 1 + description: + Reference clock input (REFCLK). When the PLL is enabled, this is + multiplied by adi,pll-multiplier to produce the system clock. + When the PLL is bypassed, the reference clock is used directly or di= vided + by 2 based on adi,reference-div2-enable to produce the system clock. + + dvdd-io33-supply: + description: 3.3V Digital I/O supply. + + avdd33-supply: + description: 3.3V Analog DAC supply. + + dvdd18-supply: + description: 1.8V Digital Core supply. + + avdd18-supply: + description: 1.8V Analog Core supply. + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - items: + - const: dev + - items: + - const: dev + - const: io + + reset-gpios: + maxItems: 2 + description: + GPIOs controlling the device reset and the I/O_RESET pins. This is o= nly + used if resets property is not defined. + + powerdown-gpios: + maxItems: 1 + description: + GPIO controlling the EXT_PWR_DWN pin. + + update-gpios: + maxItems: 1 + description: + GPIO controlling the I/O_UPDATE pin. + + profile-gpios: + minItems: 3 + maxItems: 3 + description: + GPIOs controlling the PROFILE[2:0] pins for profile selection. + + adi,pll-multiplier: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 12 + maximum: 127 + description: + PLL feedback divider value (N). The system clock frequency is + REFCLK * N. When not specified, the PLL is bypassed. + + adi,pll-vco-select: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: | + VCO frequency range selection (0-5). When not specified and the PLL + is enabled, the VCO range is automatically selected based on the + computed system clock frequency. Typical VCO frequency ranges are: + - Range 0: 370 MHz to 510 MHz (Auto-selected when <=3D 465 MHz) + - Range 1: 420 MHz to 590 MHz (Auto-selected when > 465 MHz and <=3D= 545 MHz) + - Range 2: 500 MHz to 700 MHz (Auto-selected when > 545 MHz and <=3D= 650 MHz) + - Range 3: 600 MHz to 880 MHz (Auto-selected when > 650 MHz and <=3D= 790 MHz) + - Range 4: 700 MHz to 950 MHz (Auto-selected when > 790 MHz and <=3D= 885 MHz) + - Range 5: 820 MHz to 1050 MHz (Auto-selected when > 885 MHz) + + adi,charge-pump-current-microamp: + minimum: 212 + maximum: 387 + default: 387 + description: + PLL charge pump current in microamps. Only applicable when the PLL + is enabled. The value is rounded to the nearest supported step. + + adi,refclk-out-drive-strength: + $ref: /schemas/types.yaml#/definitions/string + enum: [ disabled, low, medium, high ] + default: disabled + description: + Reference clock output (DRV0) drive strength. Only applicable when + the PLL is enabled. + + adi,reference-div2-enable: + type: boolean + description: + Enable the reference clock input divider. When enabled, the input + reference frequency is halved before deriving the system clock. + This is only applicable when the PLL is bypassed. + + adi,inverse-sinc-enable: + type: boolean + description: + Enable the inverse sinc filter that compensates for the sinc roll-off + of the DAC output. When it is enabled, the filter introduces up to 3= dB + of insertion loss. + + adi,sine-output-enable: + type: boolean + description: + Select sine wave output from the DDS core. When not set, the + output is a cosine wave. + + adi,sync-clk-disable: + type: boolean + description: + Disable the SYNC_CLK output pin. SYNC_CLK runs at one quarter + of the system clock frequency. + + adi,pdclk-disable: + type: boolean + description: + Disable the parallel data clock (PDCLK) output. PDCLK runs at + one quarter of the system clock frequency. + + adi,pdclk-invert: + type: boolean + description: + Invert the polarity of the PDCLK output. + + adi,tx-enable-invert: + type: boolean + description: + Invert the polarity of the TX_ENABLE input pin. + + adi,dac-output-current-microamp: + minimum: 8640 + maximum: 31590 + default: 20070 + description: + DAC full-scale output current in microamps. + +dependencies: + adi,pll-vco-select: [ 'adi,pll-multiplier' ] + adi,charge-pump-current-microamp: [ 'adi,pll-multiplier' ] + adi,refclk-out-drive-strength: [ 'adi,pll-multiplier' ] + +required: + - compatible + - reg + - clocks + - dvdd-io33-supply + - avdd33-supply + - dvdd18-supply + - avdd18-supply + +dependentSchemas: + resets: + properties: + reset-gpios: false + reset-gpios: + properties: + resets: false + adi,reference-div2-enable: + properties: + adi,pll-multiplier: false + adi,pll-multiplier: + properties: + adi,reference-div2-enable: false + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + dds@0 { + compatible =3D "adi,ad9910"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + clocks =3D <&ad9910_refclk>; + + dvdd-io33-supply =3D <&vdd_io33>; + avdd33-supply =3D <&vdd_a33>; + dvdd18-supply =3D <&vdd_d18>; + avdd18-supply =3D <&vdd_a18>; + + reset-gpios =3D <&gpio 0 GPIO_ACTIVE_HIGH>, + <&gpio 1 GPIO_ACTIVE_HIGH>; + powerdown-gpios =3D <&gpio 2 GPIO_ACTIVE_HIGH>; + update-gpios =3D <&gpio 3 GPIO_ACTIVE_HIGH>; + profile-gpios =3D <&gpio 4 GPIO_ACTIVE_HIGH>, + <&gpio 5 GPIO_ACTIVE_HIGH>, + <&gpio 6 GPIO_ACTIVE_HIGH>; + + adi,pll-multiplier =3D <40>; + adi,charge-pump-current-microamp =3D <387>; + adi,refclk-out-drive-strength =3D "disabled"; + adi,inverse-sinc-enable; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 1251965d70bd..79b4180e2334 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1610,6 +1610,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/dac/adi,ad9739a.yaml F: drivers/iio/dac/ad9739a.c =20 +ANALOG DEVICES INC AD9910 DRIVER +M: Rodrigo Alencar +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/frequency/adi,ad9910.yaml + ANALOG DEVICES INC MAX22007 DRIVER M: Janani Sunil L: linux-iio@vger.kernel.org --=20 2.43.0 From nobody Fri Apr 3 11:13:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1FA32BF00A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-2-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=31269; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=NklAdf1n8yPlTn/R39JfRc5ZvDb6hbZH5nXxwPPMcnw=; b=XB71dGDEyEhoRPKx22O0hivIaoukNzrkbfoudabM1usarMPni+PEjZzL36roXEDFr3KUL2TGy mdYAAKzc3FaApToryBUpir5FUZ61aomqme4V0CuZTb1LHt6Fvdhrc5x X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add the core AD9910 DDS driver infrastructure with single tone mode support. This includes SPI register access, profile management via GPIO pins, PLL/DAC configuration from firmware properties, and single tone frequency/phase/amplitude control through IIO channels. Signed-off-by: Rodrigo Alencar --- MAINTAINERS | 1 + drivers/iio/frequency/Kconfig | 18 + drivers/iio/frequency/Makefile | 1 + drivers/iio/frequency/ad9910.c | 931 +++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 951 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 79b4180e2334..4967e4ef73dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1616,6 +1616,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/frequency/adi,ad9910.yaml +F: drivers/iio/frequency/ad9910.c =20 ANALOG DEVICES INC MAX22007 DRIVER M: Janani Sunil diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index 583cbdf4e8cd..180e74f62d11 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -23,6 +23,24 @@ config AD9523 =20 endmenu =20 +menu "Direct Digital Synthesis" + +config AD9910 + tristate "Analog Devices AD9910 Direct Digital Synthesizer" + depends on SPI + depends on GPIOLIB + help + Say yes here to build support for Analog Devices AD9910 + 1 GSPS, 14-Bit DDS with integrated DAC. + + Supports single tone mode with 8 configurable profiles + and digital ramp generation. + + To compile this driver as a module, choose M here: the + module will be called ad9910. + +endmenu + # # Phase-Locked Loop (PLL) frequency synthesizers # diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index 70d0e0b70e80..39271dd209ca 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -5,6 +5,7 @@ =20 # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AD9523) +=3D ad9523.o +obj-$(CONFIG_AD9910) +=3D ad9910.o obj-$(CONFIG_ADF4350) +=3D adf4350.o obj-$(CONFIG_ADF4371) +=3D adf4371.o obj-$(CONFIG_ADF4377) +=3D adf4377.o diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c new file mode 100644 index 000000000000..82b817c05975 --- /dev/null +++ b/drivers/iio/frequency/ad9910.c @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AD9910 SPI DDS (Direct Digital Synthesizer) driver + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Register addresses */ +#define AD9910_REG_CFR1 0x00 +#define AD9910_REG_CFR2 0x01 +#define AD9910_REG_CFR3 0x02 +#define AD9910_REG_AUX_DAC 0x03 +#define AD9910_REG_IO_UPDATE_RATE 0x04 +#define AD9910_REG_FTW 0x07 +#define AD9910_REG_POW 0x08 +#define AD9910_REG_ASF 0x09 +#define AD9910_REG_MULTICHIP_SYNC 0x0A +#define AD9910_REG_DRG_LIMIT 0x0B +#define AD9910_REG_DRG_STEP 0x0C +#define AD9910_REG_DRG_RATE 0x0D +#define AD9910_REG_PROFILE0 0x0E +#define AD9910_REG_PROFILE1 0x0F +#define AD9910_REG_PROFILE2 0x10 +#define AD9910_REG_PROFILE3 0x11 +#define AD9910_REG_PROFILE4 0x12 +#define AD9910_REG_PROFILE5 0x13 +#define AD9910_REG_PROFILE6 0x14 +#define AD9910_REG_PROFILE7 0x15 +#define AD9910_REG_RAM 0x16 + +#define AD9910_REG_NUM_CACHED 0x16 + +#define AD9910_REG_PROFILE(x) (AD9910_REG_PROFILE0 + (x)) +#define AD9910_REG_HIGH32_FLAG 0x100 +#define AD9910_REG_HIGH32_MSK GENMASK_ULL(63, 32) +#define AD9910_REG_LOW32_MSK GENMASK_ULL(31, 0) + +/* CFR1 bit definitions */ +#define AD9910_CFR1_RAM_ENABLE_MSK BIT(31) +#define AD9910_CFR1_RAM_PLAYBACK_DEST_MSK GENMASK(30, 29) +#define AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK BIT(23) +#define AD9910_CFR1_INV_SINC_EN_MSK BIT(22) +#define AD9910_CFR1_INT_PROFILE_CTL_MSK GENMASK(20, 17) +#define AD9910_CFR1_SELECT_SINE_MSK BIT(16) +#define AD9910_CFR1_LOAD_LRR_IO_UPDATE_MSK BIT(15) +#define AD9910_CFR1_AUTOCLR_DIG_RAMP_ACCUM_MSK BIT(14) +#define AD9910_CFR1_AUTOCLR_PHASE_ACCUM_MSK BIT(13) +#define AD9910_CFR1_CLEAR_DIG_RAMP_ACCUM_MSK BIT(12) +#define AD9910_CFR1_CLEAR_PHASE_ACCUM_MSK BIT(11) +#define AD9910_CFR1_LOAD_ARR_IO_UPDATE_MSK BIT(10) +#define AD9910_CFR1_OSK_ENABLE_MSK BIT(9) +#define AD9910_CFR1_SELECT_AUTO_OSK_MSK BIT(8) +#define AD9910_CFR1_DIGITAL_POWER_DOWN_MSK BIT(7) +#define AD9910_CFR1_DAC_POWER_DOWN_MSK BIT(6) +#define AD9910_CFR1_REFCLK_INPUT_POWER_DOWN_MSK BIT(5) +#define AD9910_CFR1_AUX_DAC_POWER_DOWN_MSK BIT(4) +#define AD9910_CFR1_SOFT_POWER_DOWN_MSK GENMASK(7, 4) +#define AD9910_CFR1_EXT_POWER_DOWN_CTL_MSK BIT(3) +#define AD9910_CFR1_SDIO_INPUT_ONLY_MSK BIT(1) +#define AD9910_CFR1_LSB_FIRST_MSK BIT(0) + +/* CFR2 bit definitions */ +#define AD9910_CFR2_AMP_SCALE_SINGLE_TONE_MSK BIT(24) +#define AD9910_CFR2_INTERNAL_IO_UPDATE_MSK BIT(23) +#define AD9910_CFR2_SYNC_CLK_EN_MSK BIT(22) +#define AD9910_CFR2_DRG_DEST_MSK GENMASK(21, 20) +#define AD9910_CFR2_DRG_ENABLE_MSK BIT(19) +#define AD9910_CFR2_DRG_NO_DWELL_HIGH_MSK BIT(18) +#define AD9910_CFR2_DRG_NO_DWELL_LOW_MSK BIT(17) +#define AD9910_CFR2_DRG_NO_DWELL_MSK GENMASK(18, 17) +#define AD9910_CFR2_READ_EFFECTIVE_FTW_MSK BIT(16) +#define AD9910_CFR2_IO_UPDATE_RATE_CTL_MSK GENMASK(15, 14) +#define AD9910_CFR2_PDCLK_ENABLE_MSK BIT(11) +#define AD9910_CFR2_PDCLK_INVERT_MSK BIT(10) +#define AD9910_CFR2_TXENABLE_INVERT_MSK BIT(9) +#define AD9910_CFR2_MATCHED_LATENCY_EN_MSK BIT(7) +#define AD9910_CFR2_DATA_ASM_HOLD_LAST_MSK BIT(6) +#define AD9910_CFR2_SYNC_TIMING_VAL_DISABLE_MSK BIT(5) +#define AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK BIT(4) +#define AD9910_CFR2_FM_GAIN_MSK GENMASK(3, 0) + +/* CFR3 bit definitions */ +#define AD9910_CFR3_OPEN_MSK 0x08070000 +#define AD9910_CFR3_DRV0_MSK GENMASK(29, 28) +#define AD9910_CFR3_VCO_SEL_MSK GENMASK(26, 24) +#define AD9910_CFR3_ICP_MSK GENMASK(21, 19) +#define AD9910_CFR3_REFCLK_DIV_BYPASS_MSK BIT(15) +#define AD9910_CFR3_REFCLK_DIV_RESETB_MSK BIT(14) +#define AD9910_CFR3_PFD_RESET_MSK BIT(10) +#define AD9910_CFR3_PLL_EN_MSK BIT(8) +#define AD9910_CFR3_N_MSK GENMASK(7, 1) + +/* Auxiliary DAC Control Register Bits */ +#define AD9910_AUX_DAC_FSC_MSK GENMASK(7, 0) + +/* ASF Register Bits */ +#define AD9910_ASF_RAMP_RATE_MSK GENMASK(31, 16) +#define AD9910_ASF_SCALE_FACTOR_MSK GENMASK(15, 2) +#define AD9910_ASF_STEP_SIZE_MSK GENMASK(1, 0) + +/* Multichip Sync Register Bits */ +#define AD9910_MC_SYNC_VALIDATION_DELAY_MSK GENMASK(31, 28) +#define AD9910_MC_SYNC_RECEIVER_ENABLE_MSK BIT(27) +#define AD9910_MC_SYNC_GENERATOR_ENABLE_MSK BIT(26) +#define AD9910_MC_SYNC_GENERATOR_POLARITY_MSK BIT(25) +#define AD9910_MC_SYNC_STATE_PRESET_MSK GENMASK(23, 18) +#define AD9910_MC_SYNC_OUTPUT_DELAY_MSK GENMASK(15, 11) +#define AD9910_MC_SYNC_INPUT_DELAY_MSK GENMASK(7, 3) + +/* Profile Register Format (Single Tone Mode) */ +#define AD9910_PROFILE_ST_ASF_MSK GENMASK_ULL(61, 48) +#define AD9910_PROFILE_ST_POW_MSK GENMASK_ULL(47, 32) +#define AD9910_PROFILE_ST_FTW_MSK AD9910_REG_LOW32_MSK + +/* Device constants */ +#define AD9910_PI_NANORAD 3141592653UL + +#define AD9910_MAX_SYSCLK_HZ (1000 * HZ_PER_MHZ) +#define AD9910_MAX_PHASE_MICRORAD (AD9910_PI_NANORAD / 500) + +#define AD9910_ASF_MAX (BIT(14) - 1) +#define AD9910_POW_MAX (BIT(16) - 1) +#define AD9910_NUM_PROFILES 8 + +/* PLL constants */ +#define AD9910_PLL_MIN_N 12 +#define AD9910_PLL_MAX_N 127 + +#define AD9910_PLL_IN_MIN_FREQ_HZ (3200 * HZ_PER_KHZ) +#define AD9910_PLL_IN_MAX_FREQ_HZ (60 * HZ_PER_MHZ) + +#define AD9910_PLL_OUT_MIN_FREQ_HZ (420 * HZ_PER_MHZ) +#define AD9910_PLL_OUT_MAX_FREQ_HZ (1000 * HZ_PER_MHZ) + +#define AD9910_VCO0_RANGE_AUTO_MAX_HZ (465 * HZ_PER_MHZ) +#define AD9910_VCO1_RANGE_AUTO_MAX_HZ (545 * HZ_PER_MHZ) +#define AD9910_VCO2_RANGE_AUTO_MAX_HZ (650 * HZ_PER_MHZ) +#define AD9910_VCO3_RANGE_AUTO_MAX_HZ (790 * HZ_PER_MHZ) +#define AD9910_VCO4_RANGE_AUTO_MAX_HZ (885 * HZ_PER_MHZ) +#define AD9910_VCO_RANGE_NUM 6 + +#define AD9910_REFCLK_OUT_DRV_DISABLED 0 + +#define AD9910_ICP_MIN_uA 212 +#define AD9910_ICP_MAX_uA 387 +#define AD9910_ICP_STEP_uA 25 + +#define AD9910_DAC_IOUT_MAX_uA 31590 +#define AD9910_DAC_IOUT_DEFAULT_uA 20070 +#define AD9910_DAC_IOUT_MIN_uA 8640 + +#define AD9910_REFDIV2_MIN_FREQ_HZ (120 * HZ_PER_MHZ) +#define AD9910_REFDIV2_MAX_FREQ_HZ (1900 * HZ_PER_MHZ) + +#define AD9910_SPI_DATA_IDX 1 +#define AD9910_SPI_DATA_LEN_MAX sizeof(__be64) +#define AD9910_SPI_MESSAGE_LEN_MAX (AD9910_SPI_DATA_IDX + AD9910_SPI_DATA_= LEN_MAX) +#define AD9910_SPI_READ BIT(7) +#define AD9910_SPI_ADDR_MASK GENMASK(4, 0) + +/** + * enum ad9910_channel - AD9910 channel identifiers in priority order + */ +enum ad9910_channel { + AD9910_CHANNEL_SINGLE_TONE, +}; + +enum { + AD9910_PROFILE, + AD9910_POWERDOWN, +}; + +struct ad9910_data { + u32 sysclk_freq_hz; + u32 dac_output_current; + + /* PLL configuration */ + u16 pll_charge_pump_current; + u8 pll_multiplier; + u8 pll_vco_range; + + bool ref_div2_en; + u8 refclk_out_drv; + + /* Feature flags */ + bool inverse_sinc_enable; + bool sine_output_enable; + bool sync_clk_enable; + bool pdclk_enable; + bool pdclk_invert; + bool tx_enable_invert; +}; + +struct ad9910_state { + struct spi_device *spi; + struct clk *refclk; + + struct gpio_desc *gpio_pwdown; + struct gpio_desc *gpio_update; + struct gpio_descs *gpio_profile; + + /* cached registers */ + union { + u64 val64; + u32 val32; + u16 val16; + } reg[AD9910_REG_NUM_CACHED]; + + /* + * Lock for accessing device registers and state variables. + */ + struct mutex lock; + + struct ad9910_data data; + u8 profile; + + /* + * DMA (thus cache coherency maintenance) requires the transfer + * buffers to live in their own cache lines. + */ + u8 buf[AD9910_SPI_MESSAGE_LEN_MAX] __aligned(IIO_DMA_MINALIGN); +}; + +static const char * const ad9910_power_supplies[] =3D { + "dvdd-io33", "avdd33", "dvdd18", "avdd18", +}; + +static const char * const ad9910_refclk_out_drv0[] =3D { + "disabled", "low", "medium", "high", +}; + +/** + * ad9910_rational_scale() - Perform scaling of input given a reference. + * @input: The input value to be scaled. + * @scale: The numerator of the scaling factor. + * @reference: The denominator of the scaling factor. + * + * Closest rounding with mul_u64_add_u64_div_u64 + * + * Return: The scaled value. + */ +#define ad9910_rational_scale(input, scale, reference) ({ \ + u64 _tmp =3D (reference); \ + mul_u64_add_u64_div_u64(input, scale, _tmp >> 1, _tmp); \ +}) + +static int ad9910_io_update(struct ad9910_state *st) +{ + if (st->gpio_update) { + gpiod_set_value_cansleep(st->gpio_update, 1); + udelay(1); + gpiod_set_value_cansleep(st->gpio_update, 0); + } + + return 0; +} + +static inline int ad9910_spi_read(struct ad9910_state *st, u8 reg, size_t = len) +{ + st->buf[0] =3D AD9910_SPI_READ | (reg & AD9910_SPI_ADDR_MASK); + return spi_write_then_read(st->spi, &st->buf[0], 1, + &st->buf[AD9910_SPI_DATA_IDX], len); +} + +static inline int ad9910_spi_write(struct ad9910_state *st, u8 reg, size_t= len, + bool update) +{ + int ret; + + st->buf[0] =3D reg & AD9910_SPI_ADDR_MASK; + ret =3D spi_write(st->spi, st->buf, AD9910_SPI_DATA_IDX + len); + if (!ret && update) + return ad9910_io_update(st); + + return ret; +} + +#define AD9910_REG_READ_FN(nb) \ +static inline int ad9910_reg##nb##_read(struct ad9910_state *st, \ + u8 reg, u##nb * data) \ +{ \ + int ret; \ + \ + ret =3D ad9910_spi_read(st, reg, sizeof(*data)); \ + if (ret) \ + return ret; \ + \ + *data =3D get_unaligned_be##nb(&st->buf[AD9910_SPI_DATA_IDX]); \ + return ret; \ +} + +AD9910_REG_READ_FN(16) +AD9910_REG_READ_FN(32) +AD9910_REG_READ_FN(64) + +#define AD9910_REG_WRITE_FN(nb) \ +static inline int ad9910_reg##nb##_write(struct ad9910_state *st, \ + u8 reg, u##nb data, \ + bool update) \ +{ \ + int ret; \ + \ + put_unaligned_be##nb(data, &st->buf[AD9910_SPI_DATA_IDX]); \ + ret =3D ad9910_spi_write(st, reg, sizeof(data), update); \ + if (ret) \ + return ret; \ + \ + st->reg[reg].val##nb =3D data; \ + return ret; \ +} + +AD9910_REG_WRITE_FN(16) +AD9910_REG_WRITE_FN(32) +AD9910_REG_WRITE_FN(64) + +#define AD9910_REG_UPDATE_FN(nb) \ +static int ad9910_reg##nb##_update(struct ad9910_state *st, \ + u8 reg, u##nb mask, \ + u##nb data, bool update) \ +{ \ + u##nb reg_val =3D (st->reg[reg].val##nb & ~mask) | (data & mask); \ + \ + if (reg_val =3D=3D st->reg[reg].val##nb && !update) \ + return 0; \ + \ + return ad9910_reg##nb##_write(st, reg, reg_val, update); \ +} + +AD9910_REG_UPDATE_FN(16) +AD9910_REG_UPDATE_FN(32) +AD9910_REG_UPDATE_FN(64) + +static int ad9910_profile_set(struct ad9910_state *st, u8 profile) +{ + DECLARE_BITMAP(values, BITS_PER_TYPE(profile)); + + if (profile >=3D AD9910_NUM_PROFILES) + return -EINVAL; + + st->profile =3D profile; + values[0] =3D profile; + gpiod_multi_set_value_cansleep(st->gpio_profile, values); + return 0; +} + +static int ad9910_powerdown_set(struct ad9910_state *st, bool enable) +{ + return gpiod_set_value_cansleep(st->gpio_pwdown, enable); +} + +static ssize_t ad9910_ext_info_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_PROFILE: + val =3D st->profile; + break; + case AD9910_POWERDOWN: + val =3D !!FIELD_GET(AD9910_CFR1_SOFT_POWER_DOWN_MSK, + st->reg[AD9910_REG_CFR1].val32); + break; + default: + return -EINVAL; + } + + return iio_format_value(buf, IIO_VAL_INT, 1, &val); +} + +static ssize_t ad9910_ext_info_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + u32 val32; + int ret; + + ret =3D kstrtou32(buf, 10, &val32); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_PROFILE: + if (val32 >=3D AD9910_NUM_PROFILES) + return -EINVAL; + ret =3D ad9910_profile_set(st, val32); + break; + case AD9910_POWERDOWN: + val32 =3D val32 ? AD9910_CFR1_SOFT_POWER_DOWN_MSK : 0; + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_SOFT_POWER_DOWN_MSK, + val32, true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + +#define AD9910_EXT_INFO(_name, _ident, _shared) { \ + .name =3D _name, \ + .read =3D ad9910_ext_info_read, \ + .write =3D ad9910_ext_info_write, \ + .private =3D _ident, \ + .shared =3D _shared, \ +} + +static const struct iio_chan_spec_ext_info ad9910_shared_ext_info[] =3D { + AD9910_EXT_INFO("profile", AD9910_PROFILE, IIO_SHARED_BY_TYPE), + AD9910_EXT_INFO("powerdown", AD9910_POWERDOWN, IIO_SHARED_BY_TYPE), + { }, +}; + +static const struct iio_chan_spec ad9910_channels[] =3D { + [AD9910_CHANNEL_SINGLE_TONE] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_SINGLE_TONE, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_FREQUENCY) | + BIT(IIO_CHAN_INFO_PHASE) | + BIT(IIO_CHAN_INFO_SCALE), + .ext_info =3D ad9910_shared_ext_info, + }, +}; + +static int ad9910_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + u64 tmp64; + u32 tmp32; + + guard(mutex)(&st->lock); + + switch (info) { + case IIO_CHAN_INFO_FREQUENCY: + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + tmp64 =3D (u64)tmp32 * st->data.sysclk_freq_hz; + *val =3D upper_32_bits(tmp64); + *val2 =3D upper_32_bits((u64)lower_32_bits(tmp64) * MICRO); + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_PHASE: + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + tmp32 =3D ((u64)tmp32 * AD9910_MAX_PHASE_MICRORAD) >> 16; + *val =3D tmp32 / MICRO; + *val2 =3D tmp32 % MICRO; + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SCALE: + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + *val =3D 0; + *val2 =3D (u64)tmp32 * MICRO >> 14; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int ad9910_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + u64 tmp64; + u32 tmp32; + u16 tmp16; + + guard(mutex)(&st->lock); + + switch (info) { + case IIO_CHAN_INFO_FREQUENCY: + if (val < 0 || val >=3D st->data.sysclk_freq_hz / 2) + return -EINVAL; + + tmp32 =3D ad9910_rational_scale((u64)val * MICRO + val2, BIT_ULL(32), + (u64)MICRO * st->data.sysclk_freq_hz); + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_FTW_MSK, + FIELD_PREP(AD9910_PROFILE_ST_FTW_MSK, tmp32), + true); + case IIO_CHAN_INFO_PHASE: + tmp64 =3D (u64)val * MICRO + val2; + if (val < 0 || val2 < 0 || tmp64 >=3D AD9910_MAX_PHASE_MICRORAD) + return -EINVAL; + + tmp32 =3D DIV_U64_ROUND_CLOSEST(tmp64 << 16, AD9910_MAX_PHASE_MICRORAD); + tmp16 =3D min(tmp32, AD9910_POW_MAX); + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_POW_MSK, + FIELD_PREP(AD9910_PROFILE_ST_POW_MSK, tmp16), + true); + case IIO_CHAN_INFO_SCALE: + if (val < 0 || val > 1 || (val =3D=3D 1 && val2 > 0)) + return -EINVAL; + + tmp64 =3D ((u64)val * MICRO + val2) << 14; + tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, MICRO); + tmp16 =3D min(tmp64, AD9910_ASF_MAX); + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_ASF_MSK, + FIELD_PREP(AD9910_PROFILE_ST_ASF_MSK, tmp16), + true); + default: + return -EINVAL; + } +} + +static int ad9910_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_FREQUENCY: + case IIO_CHAN_INFO_PHASE: + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int ad9910_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int ret; + u64 tmp64; + u32 tmp32; + u16 tmp16; + bool high32 =3D !!(reg & AD9910_REG_HIGH32_FLAG); + + reg &=3D ~AD9910_REG_HIGH32_FLAG; + if (reg >=3D AD9910_REG_RAM) + return -EINVAL; + + guard(mutex)(&st->lock); + + switch (reg) { + case AD9910_REG_DRG_LIMIT: + case AD9910_REG_DRG_STEP: + case AD9910_REG_PROFILE0: + case AD9910_REG_PROFILE1: + case AD9910_REG_PROFILE2: + case AD9910_REG_PROFILE3: + case AD9910_REG_PROFILE4: + case AD9910_REG_PROFILE5: + case AD9910_REG_PROFILE6: + case AD9910_REG_PROFILE7: + if (readval) { + ret =3D ad9910_reg64_read(st, reg, &tmp64); + if (ret < 0) + return ret; + + if (high32) + *readval =3D upper_32_bits(tmp64); + else + *readval =3D lower_32_bits(tmp64); + } else { + tmp64 =3D st->reg[reg].val64; + if (high32) + FIELD_MODIFY(AD9910_REG_HIGH32_MSK, &tmp64, writeval); + else + FIELD_MODIFY(AD9910_REG_LOW32_MSK, &tmp64, writeval); + + return ad9910_reg64_write(st, reg, tmp64, true); + } + break; + case AD9910_REG_POW: + if (!readval) + return ad9910_reg16_write(st, reg, writeval, true); + + ret =3D ad9910_reg16_read(st, reg, &tmp16); + if (ret < 0) + return ret; + *readval =3D tmp16; + break; + default: + if (!readval) + return ad9910_reg32_write(st, reg, writeval, true); + + ret =3D ad9910_reg32_read(st, reg, &tmp32); + if (ret < 0) + return ret; + *readval =3D tmp32; + break; + } + + return ret; +} + +static const struct iio_info ad9910_info =3D { + .read_raw =3D ad9910_read_raw, + .write_raw =3D ad9910_write_raw, + .write_raw_get_fmt =3D ad9910_write_raw_get_fmt, + .debugfs_reg_access =3D &ad9910_reg_access, +}; + +static int ad9910_set_dac_current(struct ad9910_state *st, bool update) +{ + u32 fsc_code; + + /* FSC =3D (86.4 / Rset) * (1 + CODE/256) where Rset =3D 10k ohms */ + fsc_code =3D DIV_ROUND_CLOSEST(st->data.dac_output_current, 90) - 96; + fsc_code &=3D 0xFFU; + + return ad9910_reg32_write(st, AD9910_REG_AUX_DAC, fsc_code, update); +} + +static int ad9910_cfg_sysclk(struct ad9910_state *st, bool update) +{ + u32 cp_index, cfr3 =3D AD9910_CFR3_OPEN_MSK; + + cfr3 |=3D FIELD_PREP(AD9910_CFR3_DRV0_MSK, st->data.refclk_out_drv); + st->data.sysclk_freq_hz =3D clk_get_rate(st->refclk); + + if (st->data.pll_multiplier) { + st->data.sysclk_freq_hz *=3D st->data.pll_multiplier; + if (st->data.sysclk_freq_hz < AD9910_PLL_OUT_MIN_FREQ_HZ || + st->data.sysclk_freq_hz > AD9910_PLL_OUT_MAX_FREQ_HZ) { + dev_err(&st->spi->dev, "invalid vco frequency: %u Hz\n", + st->data.sysclk_freq_hz); + return -ERANGE; + } + + if (st->data.pll_vco_range >=3D AD9910_VCO_RANGE_NUM) { + if (st->data.sysclk_freq_hz <=3D AD9910_VCO0_RANGE_AUTO_MAX_HZ) + st->data.pll_vco_range =3D 0; + else if (st->data.sysclk_freq_hz <=3D AD9910_VCO1_RANGE_AUTO_MAX_HZ) + st->data.pll_vco_range =3D 1; + else if (st->data.sysclk_freq_hz <=3D AD9910_VCO2_RANGE_AUTO_MAX_HZ) + st->data.pll_vco_range =3D 2; + else if (st->data.sysclk_freq_hz <=3D AD9910_VCO3_RANGE_AUTO_MAX_HZ) + st->data.pll_vco_range =3D 3; + else if (st->data.sysclk_freq_hz <=3D AD9910_VCO4_RANGE_AUTO_MAX_HZ) + st->data.pll_vco_range =3D 4; + else + st->data.pll_vco_range =3D 5; + dev_dbg(&st->spi->dev, "auto-selected VCO range: %u\n", + st->data.pll_vco_range); + } + + cp_index =3D st->data.pll_charge_pump_current - AD9910_ICP_MIN_uA; + cp_index =3D DIV_ROUND_CLOSEST(cp_index, AD9910_ICP_STEP_uA); + cfr3 |=3D FIELD_PREP(AD9910_CFR3_VCO_SEL_MSK, st->data.pll_vco_range) | + FIELD_PREP(AD9910_CFR3_ICP_MSK, cp_index) | + FIELD_PREP(AD9910_CFR3_N_MSK, st->data.pll_multiplier) | + AD9910_CFR3_PLL_EN_MSK; + } else { + cfr3 |=3D AD9910_CFR3_VCO_SEL_MSK | + AD9910_CFR3_ICP_MSK | + AD9910_CFR3_REFCLK_DIV_RESETB_MSK | + FIELD_PREP(AD9910_CFR3_REFCLK_DIV_BYPASS_MSK, !st->data.ref_div2_en) | + AD9910_CFR3_PFD_RESET_MSK; + if (st->data.ref_div2_en) + st->data.sysclk_freq_hz >>=3D 1; + } + + return ad9910_reg32_write(st, AD9910_REG_CFR3, cfr3, update); +} + +static int ad9910_parse_fw(struct ad9910_state *st) +{ + struct device *dev =3D &st->spi->dev; + u32 tmp; + int ret; + + ret =3D device_property_read_u32(dev, "adi,pll-multiplier", &tmp); + if (!ret) { + if (tmp < AD9910_PLL_MIN_N || tmp > AD9910_PLL_MAX_N) + return dev_err_probe(dev, -ERANGE, + "invalid PLL multiplier %u\n", tmp); + st->data.pll_multiplier =3D tmp; + + tmp =3D AD9910_VCO_RANGE_NUM; + ret =3D device_property_read_u32(dev, "adi,pll-vco-select", &tmp); + if (!ret && tmp >=3D AD9910_VCO_RANGE_NUM) + return dev_err_probe(dev, -ERANGE, + "invalid VCO range: %u\n", tmp); + st->data.pll_vco_range =3D tmp; + + tmp =3D AD9910_ICP_MAX_uA; + device_property_read_u32(dev, "adi,charge-pump-current-microamp", &tmp); + if (tmp < AD9910_ICP_MIN_uA || tmp > AD9910_ICP_MAX_uA) + return dev_err_probe(dev, -ERANGE, + "invalid charge pump current %u\n", tmp); + st->data.pll_charge_pump_current =3D tmp; + + st->data.refclk_out_drv =3D AD9910_REFCLK_OUT_DRV_DISABLED; + ret =3D device_property_match_property_string(dev, + "adi,refclk-out-drive-strength", + ad9910_refclk_out_drv0, + ARRAY_SIZE(ad9910_refclk_out_drv0)); + if (ret >=3D 0) + st->data.refclk_out_drv =3D ret; + } + + st->data.ref_div2_en =3D device_property_read_bool(dev, "adi,reference-di= v2-enable"); + st->data.inverse_sinc_enable =3D device_property_read_bool(dev, "adi,inve= rse-sinc-enable"); + st->data.sine_output_enable =3D device_property_read_bool(dev, "adi,sine-= output-enable"); + st->data.sync_clk_enable =3D !device_property_read_bool(dev, "adi,sync-cl= k-disable"); + st->data.pdclk_enable =3D !device_property_read_bool(dev, "adi,pdclk-disa= ble"); + st->data.pdclk_invert =3D device_property_read_bool(dev, "adi,pdclk-inver= t"); + st->data.tx_enable_invert =3D device_property_read_bool(dev, "adi,tx-enab= le-invert"); + + tmp =3D AD9910_DAC_IOUT_DEFAULT_uA; + device_property_read_u32(dev, "adi,dac-output-current-microamp", &tmp); + if (tmp < AD9910_DAC_IOUT_MIN_uA || tmp > AD9910_DAC_IOUT_MAX_uA) + return dev_err_probe(dev, -ERANGE, + "Invalid DAC output current %u uA\n", tmp); + st->data.dac_output_current =3D tmp; + + return 0; +} + +static int ad9910_setup(struct ad9910_state *st, struct reset_control *dev= _rst) +{ + u32 reg32; + int ret; + + ret =3D reset_control_deassert(dev_rst); + if (ret) + return ret; + + reg32 =3D AD9910_CFR1_SDIO_INPUT_ONLY_MSK; + reg32 |=3D FIELD_PREP(AD9910_CFR1_INV_SINC_EN_MSK, st->data.inverse_sinc_= enable) | + FIELD_PREP(AD9910_CFR1_SELECT_SINE_MSK, st->data.sine_output_enable); + + ret =3D ad9910_reg32_write(st, AD9910_REG_CFR1, reg32, false); + if (ret) + return ret; + + reg32 =3D AD9910_CFR2_AMP_SCALE_SINGLE_TONE_MSK; + reg32 |=3D AD9910_CFR2_SYNC_TIMING_VAL_DISABLE_MSK | + AD9910_CFR2_DRG_NO_DWELL_MSK | + AD9910_CFR2_DATA_ASM_HOLD_LAST_MSK | + FIELD_PREP(AD9910_CFR2_SYNC_CLK_EN_MSK, st->data.sync_clk_enable) | + FIELD_PREP(AD9910_CFR2_PDCLK_ENABLE_MSK, st->data.pdclk_enable) | + FIELD_PREP(AD9910_CFR2_PDCLK_INVERT_MSK, st->data.pdclk_invert) | + FIELD_PREP(AD9910_CFR2_TXENABLE_INVERT_MSK, st->data.tx_enable_invert); + + ret =3D ad9910_reg32_write(st, AD9910_REG_CFR2, reg32, false); + if (ret) + return ret; + + ret =3D ad9910_cfg_sysclk(st, false); + if (ret) + return ret; + + ret =3D ad9910_set_dac_current(st, false); + if (ret) + return ret; + + return ad9910_io_update(st); +} + +static void ad9910_power_down(void *data) +{ + struct ad9910_state *st =3D data; + + if (!ad9910_powerdown_set(st, true)) + return; + + ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_SOFT_POWER_DOWN_MSK, + AD9910_CFR1_SOFT_POWER_DOWN_MSK, + true); +} + +static int ad9910_probe(struct spi_device *spi) +{ + struct reset_control *dev_rst, *io_rst; + struct gpio_desc *io_rst_gpio; + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad9910_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + + spi_set_drvdata(spi, indio_dev); + + st->refclk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(st->refclk)) + return dev_err_probe(dev, PTR_ERR(st->refclk), + "Failed to get reference clock\n"); + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(ad9910_power_supplies), + ad9910_power_supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + indio_dev->name =3D "ad9910"; + indio_dev->info =3D &ad9910_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D ad9910_channels; + indio_dev->num_channels =3D ARRAY_SIZE(ad9910_channels); + + dev_rst =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(dev_rst)) + return dev_err_probe(dev, PTR_ERR(dev_rst), + "failed to get device reset control\n"); + + ret =3D reset_control_assert(dev_rst); + if (ret) + return dev_err_probe(dev, ret, + "failed to assert device reset control\n"); + + /* + * The IO RESET pin is not used in this driver, as we assume that all + * SPI transfers are complete, but if it is wired up, we need to make + * sure it is not floating. We can use either a reset controller or a + * GPIO for this. + */ + io_rst =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "io"= ); + if (IS_ERR(io_rst)) + return dev_err_probe(dev, PTR_ERR(io_rst), + "failed to get io reset control\n"); + + io_rst_gpio =3D devm_gpiod_get_index_optional(dev, "reset", 1, + GPIOD_OUT_LOW); + if (IS_ERR(io_rst_gpio)) + return dev_err_probe(dev, PTR_ERR(io_rst_gpio), + "failed to get io reset gpio\n"); + + st->gpio_pwdown =3D devm_gpiod_get_optional(dev, "powerdown", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_pwdown)) + return dev_err_probe(dev, PTR_ERR(st->gpio_pwdown), + "failed to get powerdown gpio\n"); + + st->gpio_update =3D devm_gpiod_get_optional(dev, "update", GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_update)) + return dev_err_probe(dev, PTR_ERR(st->gpio_update), + "failed to get update gpio\n"); + + st->gpio_profile =3D devm_gpiod_get_array_optional(dev, "profile", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_profile)) + return dev_err_probe(dev, PTR_ERR(st->gpio_profile), + "failed to get profile gpios\n"); + + ret =3D ad9910_parse_fw(st); + if (ret) + return ret; + + ret =3D ad9910_setup(st, dev_rst); + if (ret) + return dev_err_probe(dev, ret, "device setup failed\n"); + + ret =3D devm_add_action_or_reset(dev, ad9910_power_down, st); + if (ret) + return dev_err_probe(dev, ret, "failed to add power down action\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id ad9910_id[] =3D { + {"ad9910", 0}, + {} +}; +MODULE_DEVICE_TABLE(spi, ad9910_id); + +static const struct of_device_id ad9910_of_match[] =3D { + { .compatible =3D "adi,ad9910" }, + { } +}; +MODULE_DEVICE_TABLE(of, ad9910_of_match); + +static struct spi_driver ad9910_driver =3D { + .driver =3D { + .name =3D "ad9910", + .of_match_table =3D ad9910_of_match, + }, + .probe =3D ad9910_probe, + .id_table =3D ad9910_id, +}; +module_spi_driver(ad9910_driver); + +MODULE_AUTHOR("Rodrigo Alencar "); +MODULE_DESCRIPTION("Analog Devices AD9910 DDS driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Fri Apr 3 11:13:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2B8A2F363E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-3-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=8528; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=EK0WTQcP1PVBIImMgpG+WQS3qmLgwZLDh81TfAy8jIo=; b=9V6InTEI7nScWJlEQAoe/y073K7EEPKEx1EALAup/arUXNOlyxA2Lapd/0Igo6EUfzn29RNER YmWNekMl5D5DFA5orSqQ3WyT0jg+N2yn0gF8eZ7i6cfaZVCUldyJGxp X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add parallel port channel with frequency scale, frequency offset, phase offset, and amplitude offset extended attributes for configuring the parallel data path. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 167 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 164 insertions(+), 3 deletions(-) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index 82b817c05975..bb280972e84c 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -115,9 +115,13 @@ /* Auxiliary DAC Control Register Bits */ #define AD9910_AUX_DAC_FSC_MSK GENMASK(7, 0) =20 +/* POW Register Bits */ +#define AD9910_POW_PP_LSB_MSK GENMASK(7, 0) + /* ASF Register Bits */ #define AD9910_ASF_RAMP_RATE_MSK GENMASK(31, 16) #define AD9910_ASF_SCALE_FACTOR_MSK GENMASK(15, 2) +#define AD9910_ASF_SCALE_FACTOR_PP_LSB_MSK GENMASK(7, 2) #define AD9910_ASF_STEP_SIZE_MSK GENMASK(1, 0) =20 /* Multichip Sync Register Bits */ @@ -141,7 +145,9 @@ #define AD9910_MAX_PHASE_MICRORAD (AD9910_PI_NANORAD / 500) =20 #define AD9910_ASF_MAX (BIT(14) - 1) +#define AD9910_ASF_PP_LSB_MAX (BIT(6) - 1) #define AD9910_POW_MAX (BIT(16) - 1) +#define AD9910_POW_PP_LSB_MAX (BIT(8) - 1) #define AD9910_NUM_PROFILES 8 =20 /* PLL constants */ @@ -185,11 +191,16 @@ */ enum ad9910_channel { AD9910_CHANNEL_SINGLE_TONE, + AD9910_CHANNEL_PARALLEL_PORT, }; =20 enum { AD9910_PROFILE, AD9910_POWERDOWN, + AD9910_PP_FREQ_SCALE, + AD9910_PP_FREQ_OFFSET, + AD9910_PP_PHASE_OFFSET, + AD9910_PP_AMP_OFFSET, }; =20 struct ad9910_data { @@ -388,6 +399,10 @@ static ssize_t ad9910_ext_info_read(struct iio_dev *in= dio_dev, val =3D !!FIELD_GET(AD9910_CFR1_SOFT_POWER_DOWN_MSK, st->reg[AD9910_REG_CFR1].val32); break; + case AD9910_PP_FREQ_SCALE: + val =3D BIT(FIELD_GET(AD9910_CFR2_FM_GAIN_MSK, + st->reg[AD9910_REG_CFR2].val32)); + break; default: return -EINVAL; } @@ -423,6 +438,15 @@ static ssize_t ad9910_ext_info_write(struct iio_dev *i= ndio_dev, AD9910_CFR1_SOFT_POWER_DOWN_MSK, val32, true); break; + case AD9910_PP_FREQ_SCALE: + if (val32 > BIT(15) || !is_power_of_2(val32)) + return -EINVAL; + + val32 =3D FIELD_PREP(AD9910_CFR2_FM_GAIN_MSK, ilog2(val32)); + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_FM_GAIN_MSK, + val32, true); + break; default: return -EINVAL; } @@ -430,20 +454,126 @@ static ssize_t ad9910_ext_info_write(struct iio_dev = *indio_dev, return ret ?: len; } =20 -#define AD9910_EXT_INFO(_name, _ident, _shared) { \ +static ssize_t ad9910_pp_attrs_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int vals[2]; + u32 tmp32; + u64 tmp64; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_PP_FREQ_OFFSET: + tmp64 =3D (u64)st->reg[AD9910_REG_FTW].val32 * st->data.sysclk_freq_hz; + vals[0] =3D upper_32_bits(tmp64); + vals[1] =3D upper_32_bits((u64)lower_32_bits(tmp64) * MICRO); + break; + case AD9910_PP_PHASE_OFFSET: + tmp32 =3D FIELD_GET(AD9910_POW_PP_LSB_MSK, + st->reg[AD9910_REG_POW].val16); + tmp32 =3D (tmp32 * AD9910_MAX_PHASE_MICRORAD) >> 16; + vals[0] =3D tmp32 / MICRO; + vals[1] =3D tmp32 % MICRO; + break; + case AD9910_PP_AMP_OFFSET: + tmp32 =3D FIELD_GET(AD9910_ASF_SCALE_FACTOR_PP_LSB_MSK, + st->reg[AD9910_REG_ASF].val32); + vals[0] =3D 0; + vals[1] =3D (u64)tmp32 * MICRO >> 14; + break; + default: + return -EINVAL; + } + + return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), va= ls); +} + +static ssize_t ad9910_pp_attrs_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + u32 tmp32; + int ret; + + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_PP_FREQ_OFFSET: + if (val < 0 || val >=3D st->data.sysclk_freq_hz / 2) + return -EINVAL; + + tmp32 =3D ad9910_rational_scale((u64)val * MICRO + val2, BIT_ULL(32), + (u64)MICRO * st->data.sysclk_freq_hz); + ret =3D ad9910_reg32_write(st, AD9910_REG_FTW, tmp32, true); + break; + case AD9910_PP_PHASE_OFFSET: + if (val !=3D 0 || val2 < 0 || val2 >=3D (AD9910_MAX_PHASE_MICRORAD >> 8)) + return -EINVAL; + + tmp32 =3D DIV_ROUND_CLOSEST((u32)val2 << 16, AD9910_MAX_PHASE_MICRORAD); + tmp32 =3D min(tmp32, AD9910_POW_PP_LSB_MAX); + tmp32 =3D FIELD_PREP(AD9910_POW_PP_LSB_MSK, tmp32); + ret =3D ad9910_reg16_update(st, AD9910_REG_POW, + AD9910_POW_PP_LSB_MSK, + tmp32, true); + break; + case AD9910_PP_AMP_OFFSET: + if (val !=3D 0 || val2 < 0 || val2 >=3D (MICRO >> 8)) + return -EINVAL; + + tmp32 =3D DIV_ROUND_CLOSEST((u32)val2 << 14, MICRO); + tmp32 =3D min(tmp32, AD9910_ASF_PP_LSB_MAX); + tmp32 =3D FIELD_PREP(AD9910_ASF_SCALE_FACTOR_PP_LSB_MSK, tmp32); + ret =3D ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_SCALE_FACTOR_PP_LSB_MSK, + tmp32, true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + +#define AD9910_EXT_INFO_TMPL(_name, _ident, _shared, _fn_desc) { \ .name =3D _name, \ - .read =3D ad9910_ext_info_read, \ - .write =3D ad9910_ext_info_write, \ + .read =3D ad9910_ ## _fn_desc ## _read, \ + .write =3D ad9910_ ## _fn_desc ## _write, \ .private =3D _ident, \ .shared =3D _shared, \ } =20 +#define AD9910_EXT_INFO(_name, _ident, _shared) \ + AD9910_EXT_INFO_TMPL(_name, _ident, _shared, ext_info) + +#define AD9910_PP_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, pp_attrs) + static const struct iio_chan_spec_ext_info ad9910_shared_ext_info[] =3D { AD9910_EXT_INFO("profile", AD9910_PROFILE, IIO_SHARED_BY_TYPE), AD9910_EXT_INFO("powerdown", AD9910_POWERDOWN, IIO_SHARED_BY_TYPE), { }, }; =20 +static const struct iio_chan_spec_ext_info ad9910_pp_ext_info[] =3D { + AD9910_EXT_INFO("frequency_scale", AD9910_PP_FREQ_SCALE, IIO_SEPARATE), + AD9910_PP_EXT_INFO("frequency_offset", AD9910_PP_FREQ_OFFSET), + AD9910_PP_EXT_INFO("phase_offset", AD9910_PP_PHASE_OFFSET), + AD9910_PP_EXT_INFO("scale_offset", AD9910_PP_AMP_OFFSET), + { }, +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHANNEL_SINGLE_TONE] =3D { .type =3D IIO_ALTVOLTAGE, @@ -456,6 +586,14 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { BIT(IIO_CHAN_INFO_SCALE), .ext_info =3D ad9910_shared_ext_info, }, + [AD9910_CHANNEL_PARALLEL_PORT] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_PARALLEL_PORT, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), + .ext_info =3D ad9910_pp_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -469,6 +607,16 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, guard(mutex)(&st->lock); =20 switch (info) { + case IIO_CHAN_INFO_ENABLE: + switch (chan->channel) { + case AD9910_CHANNEL_PARALLEL_PORT: + *val =3D FIELD_GET(AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, + st->reg[AD9910_REG_CFR2].val32); + break; + default: + return -EINVAL; + } + return IIO_VAL_INT; case IIO_CHAN_INFO_FREQUENCY: tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, st->reg[AD9910_REG_PROFILE(st->profile)].val64); @@ -506,6 +654,17 @@ static int ad9910_write_raw(struct iio_dev *indio_dev, guard(mutex)(&st->lock); =20 switch (info) { + case IIO_CHAN_INFO_ENABLE: + val =3D val ? 1 : 0; + switch (chan->channel) { + case AD9910_CHANNEL_PARALLEL_PORT: + tmp32 =3D FIELD_PREP(AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, + tmp32, true); + default: + return -EINVAL; + } case IIO_CHAN_INFO_FREQUENCY: if (val < 0 || val >=3D st->data.sysclk_freq_hz / 2) return -EINVAL; @@ -548,6 +707,8 @@ static int ad9910_write_raw_get_fmt(struct iio_dev *ind= io_dev, long mask) { switch (mask) { + case IIO_CHAN_INFO_ENABLE: + return IIO_VAL_INT; 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Fri, 20 Feb 2026 16:46:27 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Fri, 20 Feb 2026 16:46:08 +0000 Subject: [PATCH RFC 4/8] iio: frequency: ad9910: expose sysclk_frequency device attribute Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-4-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=1404; i=rodrigo.alencar@analog.com; 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This value is important for userspace to calculate values to populate the Parallel Port or the RAM data buffer. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index bb280972e84c..a72e3685f676 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -789,10 +789,31 @@ static int ad9910_reg_access(struct iio_dev *indio_de= v, return ret; } =20 +static ssize_t sysclk_frequency_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(dev_to_iio_dev(dev)); + + return sysfs_emit(buf, "%u\n", st->data.sysclk_freq_hz); +} + +static IIO_DEVICE_ATTR_RO(sysclk_frequency, 0); + +static struct attribute *ad9910_attrs[] =3D { + &iio_dev_attr_sysclk_frequency.dev_attr.attr, + NULL +}; + +static const struct attribute_group ad9910_attrs_group =3D { + .attrs =3D ad9910_attrs, +}; + static const struct iio_info ad9910_info =3D { .read_raw =3D ad9910_read_raw, .write_raw =3D ad9910_write_raw, .write_raw_get_fmt =3D ad9910_write_raw_get_fmt, + .attrs =3D &ad9910_attrs_group, .debugfs_reg_access =3D &ad9910_reg_access, }; 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Fri, 20 Feb 2026 16:46:27 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Fri, 20 Feb 2026 16:46:09 +0000 Subject: [PATCH RFC 5/8] iio: frequency: ad9910: add digital ramp generator support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-5-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=17752; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=izJCqqe/mjPLHctBorpLyiMP1dZRqD1NyGEif4TXAjw=; b=2IVfzeWafZ9tnV0QCz+Ju0CiRp6gWOSDBaaJ6nWuDC33d72ygpNw8qEUfZvntliTvaroSZHLg hiOvY7N6QV3CXkJbrTeszMLhadA8sVEV5crFYdyhAWiXcXUzICTLTAA X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add DRG channel with destination selection (frequency, phase, or amplitude), operating mode control, configurable upper/lower limits, increment/decrement step sizes, and step rate settings for the digital ramp generator. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 454 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 454 insertions(+) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index a72e3685f676..84698bf2dc4e 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -133,6 +133,18 @@ #define AD9910_MC_SYNC_OUTPUT_DELAY_MSK GENMASK(15, 11) #define AD9910_MC_SYNC_INPUT_DELAY_MSK GENMASK(7, 3) =20 +/* Digital Ramp Limit Register */ +#define AD9910_DRG_LIMIT_UPPER_MSK AD9910_REG_HIGH32_MSK +#define AD9910_DRG_LIMIT_LOWER_MSK AD9910_REG_LOW32_MSK + +/* Digital Ramp Step Register */ +#define AD9910_DRG_STEP_DEC_MSK AD9910_REG_HIGH32_MSK +#define AD9910_DRG_STEP_INC_MSK AD9910_REG_LOW32_MSK + +/* Digital Ramp Rate Register */ +#define AD9910_DRG_RATE_DEC_MSK GENMASK(31, 16) +#define AD9910_DRG_RATE_INC_MSK GENMASK(15, 0) + /* Profile Register Format (Single Tone Mode) */ #define AD9910_PROFILE_ST_ASF_MSK GENMASK_ULL(61, 48) #define AD9910_PROFILE_ST_POW_MSK GENMASK_ULL(47, 32) @@ -148,8 +160,11 @@ #define AD9910_ASF_PP_LSB_MAX (BIT(6) - 1) #define AD9910_POW_MAX (BIT(16) - 1) #define AD9910_POW_PP_LSB_MAX (BIT(8) - 1) +#define AD9910_STEP_RATE_MAX (BIT(16) - 1) #define AD9910_NUM_PROFILES 8 =20 +#define AD9910_DRG_DEST_NUM 3 + /* PLL constants */ #define AD9910_PLL_MIN_N 12 #define AD9910_PLL_MAX_N 127 @@ -192,6 +207,32 @@ enum ad9910_channel { AD9910_CHANNEL_SINGLE_TONE, AD9910_CHANNEL_PARALLEL_PORT, + AD9910_CHANNEL_DRG, +}; + +/** + * enum ad9910_destination - AD9910 DDS core parameter destination + */ +enum ad9910_destination { + AD9910_DEST_FREQUENCY, + AD9910_DEST_PHASE, + AD9910_DEST_AMPLITUDE, + AD9910_DEST_POLAR, +}; + +/** + * enum ad9910_drg_oper_mode - Digital Ramp Generator Operating Mode + * + * @AD9910_DRG_OPER_MODE_BIDIR: Normal Ramp Generation + * @AD9910_DRG_OPER_MODE_RAMP_DOWN: No-dwell Low only operation + * @AD9910_DRG_OPER_MODE_RAMP_UP: No-dwell High only operation + * @AD9910_DRG_OPER_MODE_BIDIR_CONT: Both No-dwell High/Low operation + */ +enum ad9910_drg_oper_mode { + AD9910_DRG_OPER_MODE_BIDIR, + AD9910_DRG_OPER_MODE_RAMP_DOWN, + AD9910_DRG_OPER_MODE_RAMP_UP, + AD9910_DRG_OPER_MODE_BIDIR_CONT, }; =20 enum { @@ -201,6 +242,20 @@ enum { AD9910_PP_FREQ_OFFSET, AD9910_PP_PHASE_OFFSET, AD9910_PP_AMP_OFFSET, + AD9910_DRG_FREQ_UPPER_LIMIT, + AD9910_DRG_FREQ_LOWER_LIMIT, + AD9910_DRG_FREQ_INC_STEP, + AD9910_DRG_FREQ_DEC_STEP, + AD9910_DRG_PHASE_UPPER_LIMIT, + AD9910_DRG_PHASE_LOWER_LIMIT, + AD9910_DRG_PHASE_INC_STEP, + AD9910_DRG_PHASE_DEC_STEP, + AD9910_DRG_AMP_UPPER_LIMIT, + AD9910_DRG_AMP_LOWER_LIMIT, + AD9910_DRG_AMP_INC_STEP, + AD9910_DRG_AMP_DEC_STEP, + AD9910_DRG_INC_STEP_RATE, + AD9910_DRG_DEC_STEP_RATE, }; =20 struct ad9910_data { @@ -262,6 +317,20 @@ static const char * const ad9910_refclk_out_drv0[] =3D= { "disabled", "low", "medium", "high", }; =20 +static const char * const ad9910_destination_str[] =3D { + [AD9910_DEST_FREQUENCY] =3D "frequency", + [AD9910_DEST_PHASE] =3D "phase", + [AD9910_DEST_AMPLITUDE] =3D "amplitude", + [AD9910_DEST_POLAR] =3D "polar", +}; + +static const char * const ad9910_drg_oper_mode_str[] =3D { + [AD9910_DRG_OPER_MODE_BIDIR] =3D "bidirectional", + [AD9910_DRG_OPER_MODE_RAMP_DOWN] =3D "ramp_down", + [AD9910_DRG_OPER_MODE_RAMP_UP] =3D "ramp_up", + [AD9910_DRG_OPER_MODE_BIDIR_CONT] =3D "bidirectional_continuous", +}; + /** * ad9910_rational_scale() - Perform scaling of input given a reference. * @input: The input value to be scaled. @@ -381,6 +450,66 @@ static int ad9910_powerdown_set(struct ad9910_state *s= t, bool enable) return gpiod_set_value_cansleep(st->gpio_pwdown, enable); } =20 +static int ad9910_chan_destination_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + switch (chan->channel) { + case AD9910_CHANNEL_DRG: + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_DRG_DEST_MSK, + FIELD_PREP(AD9910_CFR2_DRG_DEST_MSK, val), + true); + default: + return -EINVAL; + } +} + +static int ad9910_chan_destination_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + switch (chan->channel) { + case AD9910_CHANNEL_DRG: + return FIELD_GET(AD9910_CFR2_DRG_DEST_MSK, + st->reg[AD9910_REG_CFR2].val32); + default: + return -EINVAL; + } +} + +static int ad9910_drg_oper_mode_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_DRG_NO_DWELL_MSK, + FIELD_PREP(AD9910_CFR2_DRG_NO_DWELL_MSK, val), + true); +} + +static int ad9910_drg_oper_mode_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + return FIELD_GET(AD9910_CFR2_DRG_NO_DWELL_MSK, + st->reg[AD9910_REG_CFR2].val32); +} + static ssize_t ad9910_ext_info_read(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, @@ -546,6 +675,264 @@ static ssize_t ad9910_pp_attrs_write(struct iio_dev *= indio_dev, return ret ?: len; } =20 +static ssize_t ad9910_step_rate_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int vals[2]; + u32 tmp32; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_INC_STEP_RATE: + tmp32 =3D FIELD_GET(AD9910_DRG_RATE_INC_MSK, + st->reg[AD9910_REG_DRG_RATE].val32); + break; + case AD9910_DRG_DEC_STEP_RATE: + tmp32 =3D FIELD_GET(AD9910_DRG_RATE_DEC_MSK, + st->reg[AD9910_REG_DRG_RATE].val32); + break; + default: + return -EINVAL; + } + + if (tmp32 =3D=3D 0) + return -ERANGE; + + tmp32 *=3D 4; + vals[0] =3D st->data.sysclk_freq_hz / tmp32; + vals[1] =3D div_u64((u64)(st->data.sysclk_freq_hz % tmp32) * MICRO, tmp32= ); + + return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), va= ls); +} + +static ssize_t ad9910_step_rate_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + u64 rate_val; + u64 sysclk_uhz; + int ret; + + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + sysclk_uhz =3D (u64)st->data.sysclk_freq_hz * MICROHZ_PER_HZ; + rate_val =3D ((u64)val * MICROHZ_PER_HZ + val2) * 4; + if (rate_val =3D=3D 0 || rate_val > sysclk_uhz) + return -EINVAL; + + rate_val =3D min(DIV64_U64_ROUND_CLOSEST(sysclk_uhz, rate_val), + AD9910_STEP_RATE_MAX); + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_INC_STEP_RATE: + ret =3D ad9910_reg32_update(st, AD9910_REG_DRG_RATE, + AD9910_DRG_RATE_INC_MSK, + FIELD_PREP(AD9910_DRG_RATE_INC_MSK, rate_val), + true); + break; + case AD9910_DRG_DEC_STEP_RATE: + ret =3D ad9910_reg32_update(st, AD9910_REG_DRG_RATE, + AD9910_DRG_RATE_DEC_MSK, + FIELD_PREP(AD9910_DRG_RATE_DEC_MSK, rate_val), true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + +static ssize_t ad9910_drg_attrs_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + unsigned int type; + int vals[2]; + u64 tmp64; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_AMP_UPPER_LIMIT: + tmp64 =3D FIELD_GET(AD9910_DRG_LIMIT_UPPER_MSK, + st->reg[AD9910_REG_DRG_LIMIT].val64); + break; + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + tmp64 =3D FIELD_GET(AD9910_DRG_LIMIT_LOWER_MSK, + st->reg[AD9910_REG_DRG_LIMIT].val64); + break; + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_AMP_INC_STEP: + tmp64 =3D FIELD_GET(AD9910_DRG_STEP_INC_MSK, + st->reg[AD9910_REG_DRG_STEP].val64); + break; + case AD9910_DRG_FREQ_DEC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + tmp64 =3D FIELD_GET(AD9910_DRG_STEP_DEC_MSK, + st->reg[AD9910_REG_DRG_STEP].val64); + break; + default: + return -EINVAL; + } + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_FREQ_DEC_STEP: + type =3D IIO_VAL_INT_PLUS_MICRO; + tmp64 *=3D st->data.sysclk_freq_hz; + vals[0] =3D upper_32_bits(tmp64); + vals[1] =3D upper_32_bits((u64)lower_32_bits(tmp64) * MICRO); + break; + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + type =3D IIO_VAL_INT_PLUS_NANO; + tmp64 *=3D AD9910_PI_NANORAD; + tmp64 >>=3D 31; + vals[0] =3D div_u64_rem(tmp64, NANO, &vals[1]); + break; + case AD9910_DRG_AMP_UPPER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + case AD9910_DRG_AMP_INC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + type =3D IIO_VAL_INT_PLUS_NANO; + vals[0] =3D 0; + vals[1] =3D tmp64 * NANO >> 32; + break; + default: + return -EINVAL; + } + + return iio_format_value(buf, type, ARRAY_SIZE(vals), vals); +} + +static ssize_t ad9910_drg_attrs_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + u64 tmp64; + int ret; + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_FREQ_DEC_STEP: + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + if (val >=3D st->data.sysclk_freq_hz / 2) + return -EINVAL; + + tmp64 =3D (u64)val * MICRO + val2; + tmp64 =3D ad9910_rational_scale(tmp64, BIT_ULL(32), + (u64)MICRO * st->data.sysclk_freq_hz); + break; + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + ret =3D iio_str_to_fixpoint(buf, NANO / 10, &val, &val2); + if (ret) + return ret; + + if (val < 0 || val2 < 0) + return -EINVAL; + + tmp64 =3D (u64)val * NANO + val2; + if (tmp64 > 2ULL * AD9910_PI_NANORAD) + return -EINVAL; + + tmp64 <<=3D 31; + tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, AD9910_PI_NANORAD); + break; + case AD9910_DRG_AMP_UPPER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + case AD9910_DRG_AMP_INC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + ret =3D iio_str_to_fixpoint(buf, NANO / 10, &val, &val2); + if (ret) + return ret; + + if (val < 0 || val > 1 || (val =3D=3D 1 && val2 > 0)) + return -EINVAL; + + tmp64 =3D ((u64)val * NANO + val2) << 32; + tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, NANO); + break; + default: + return -EINVAL; + } + + tmp64 =3D min(tmp64, U32_MAX); + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_DRG_FREQ_UPPER_LIMIT: + case AD9910_DRG_PHASE_UPPER_LIMIT: + case AD9910_DRG_AMP_UPPER_LIMIT: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_LIMIT, + AD9910_DRG_LIMIT_UPPER_MSK, + FIELD_PREP(AD9910_DRG_LIMIT_UPPER_MSK, tmp64), + true); + break; + case AD9910_DRG_FREQ_LOWER_LIMIT: + case AD9910_DRG_PHASE_LOWER_LIMIT: + case AD9910_DRG_AMP_LOWER_LIMIT: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_LIMIT, + AD9910_DRG_LIMIT_LOWER_MSK, + FIELD_PREP(AD9910_DRG_LIMIT_LOWER_MSK, tmp64), + true); + break; + case AD9910_DRG_FREQ_INC_STEP: + case AD9910_DRG_PHASE_INC_STEP: + case AD9910_DRG_AMP_INC_STEP: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_STEP, + AD9910_DRG_STEP_INC_MSK, + FIELD_PREP(AD9910_DRG_STEP_INC_MSK, tmp64), + true); + break; + case AD9910_DRG_FREQ_DEC_STEP: + case AD9910_DRG_PHASE_DEC_STEP: + case AD9910_DRG_AMP_DEC_STEP: + ret =3D ad9910_reg64_update(st, AD9910_REG_DRG_STEP, + AD9910_DRG_STEP_DEC_MSK, + FIELD_PREP(AD9910_DRG_STEP_DEC_MSK, tmp64), + true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + #define AD9910_EXT_INFO_TMPL(_name, _ident, _shared, _fn_desc) { \ .name =3D _name, \ .read =3D ad9910_ ## _fn_desc ## _read, \ @@ -560,6 +947,26 @@ static ssize_t ad9910_pp_attrs_write(struct iio_dev *i= ndio_dev, #define AD9910_PP_EXT_INFO(_name, _ident) \ AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, pp_attrs) =20 +#define AD9910_STEP_RATE_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, step_rate) + +#define AD9910_DRG_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, drg_attrs) + +static const struct iio_enum ad9910_drg_destination_enum =3D { + .items =3D ad9910_destination_str, + .num_items =3D AD9910_DRG_DEST_NUM, + .set =3D ad9910_chan_destination_set, + .get =3D ad9910_chan_destination_get, +}; + +static const struct iio_enum ad9910_drg_oper_mode_enum =3D { + .items =3D ad9910_drg_oper_mode_str, + .num_items =3D ARRAY_SIZE(ad9910_drg_oper_mode_str), + .set =3D ad9910_drg_oper_mode_set, + .get =3D ad9910_drg_oper_mode_get, +}; + static const struct iio_chan_spec_ext_info ad9910_shared_ext_info[] =3D { AD9910_EXT_INFO("profile", AD9910_PROFILE, IIO_SHARED_BY_TYPE), AD9910_EXT_INFO("powerdown", AD9910_POWERDOWN, IIO_SHARED_BY_TYPE), @@ -574,6 +981,28 @@ static const struct iio_chan_spec_ext_info ad9910_pp_e= xt_info[] =3D { { }, }; =20 +static const struct iio_chan_spec_ext_info ad9910_drg_ext_info[] =3D { + IIO_ENUM("destination", IIO_SEPARATE, &ad9910_drg_destination_enum), + IIO_ENUM_AVAILABLE("destination", IIO_SEPARATE, &ad9910_drg_destination_e= num), + IIO_ENUM("operating_mode", IIO_SEPARATE, &ad9910_drg_oper_mode_enum), + IIO_ENUM_AVAILABLE("operating_mode", IIO_SEPARATE, &ad9910_drg_oper_mode_= enum), + AD9910_DRG_EXT_INFO("frequency_max", AD9910_DRG_FREQ_UPPER_LIMIT), + AD9910_DRG_EXT_INFO("frequency_min", AD9910_DRG_FREQ_LOWER_LIMIT), + AD9910_DRG_EXT_INFO("frequency_increment", AD9910_DRG_FREQ_INC_STEP), + AD9910_DRG_EXT_INFO("frequency_decrement", AD9910_DRG_FREQ_DEC_STEP), + AD9910_DRG_EXT_INFO("phase_max", AD9910_DRG_PHASE_UPPER_LIMIT), + AD9910_DRG_EXT_INFO("phase_min", AD9910_DRG_PHASE_LOWER_LIMIT), + AD9910_DRG_EXT_INFO("phase_increment", AD9910_DRG_PHASE_INC_STEP), + AD9910_DRG_EXT_INFO("phase_decrement", AD9910_DRG_PHASE_DEC_STEP), + AD9910_DRG_EXT_INFO("scale_max", AD9910_DRG_AMP_UPPER_LIMIT), + AD9910_DRG_EXT_INFO("scale_min", AD9910_DRG_AMP_LOWER_LIMIT), + AD9910_DRG_EXT_INFO("scale_increment", AD9910_DRG_AMP_INC_STEP), + AD9910_DRG_EXT_INFO("scale_decrement", AD9910_DRG_AMP_DEC_STEP), + AD9910_STEP_RATE_EXT_INFO("increment_sampling_frequency", AD9910_DRG_INC_= STEP_RATE), + AD9910_STEP_RATE_EXT_INFO("decrement_sampling_frequency", AD9910_DRG_DEC_= STEP_RATE), + { }, +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHANNEL_SINGLE_TONE] =3D { .type =3D IIO_ALTVOLTAGE, @@ -594,6 +1023,15 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), .ext_info =3D ad9910_pp_ext_info, }, + [AD9910_CHANNEL_DRG] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_DRG, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), + .ext_info =3D ad9910_drg_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -613,6 +1051,10 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, *val =3D FIELD_GET(AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, st->reg[AD9910_REG_CFR2].val32); break; + case AD9910_CHANNEL_DRG: + *val =3D FIELD_GET(AD9910_CFR2_DRG_ENABLE_MSK, + st->reg[AD9910_REG_CFR2].val32); + break; default: return -EINVAL; } @@ -662,6 +1104,11 @@ static int ad9910_write_raw(struct iio_dev *indio_dev, return ad9910_reg32_update(st, AD9910_REG_CFR2, AD9910_CFR2_PARALLEL_DATA_PORT_EN_MSK, tmp32, true); + case AD9910_CHANNEL_DRG: + tmp32 =3D FIELD_PREP(AD9910_CFR2_DRG_ENABLE_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR2, + AD9910_CFR2_DRG_ENABLE_MSK, + tmp32, true); default: return -EINVAL; } @@ -972,6 +1419,13 @@ static int ad9910_setup(struct ad9910_state *st, stru= ct reset_control *dev_rst) if (ret) return ret; =20 + /* configure step rate with default values */ + reg32 =3D FIELD_PREP(AD9910_DRG_RATE_DEC_MSK, 1) | + FIELD_PREP(AD9910_DRG_RATE_INC_MSK, 1); + ret =3D ad9910_reg32_write(st, AD9910_REG_DRG_RATE, reg32, false); + if (ret) + return ret; + return ad9910_io_update(st); } =20 --=20 2.43.0 From nobody Fri Apr 3 11:13:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 405402FCBF5; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-6-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=24545; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=40I0rilF1cHROAoMlCMzfANWq5mVGiNIdWyQOhmms9c=; b=VvkTsGZI/KknPTpJ6PpEwHZMg41CzEw4eJh6QVnAG0FyZ116KzVuLojAIM9qIpfB/tOvbUrq4 XQ04+jWCktXBISaHrvtQcjZ1GujuE3GyKBkUl8/VOO2XsGau7FR9U56 X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add RAM channel with support for profile-based control. This includes: - RAM data loading via binary sysfs attribute (ram_data); - Per-profile RAM configuration (start/end address, step rate, operating mode, dwell control); - RAM destination control (frequency, phase, amplitude, polar); - RAM operating modes (direct switch, ramp up, bidirectional ramp, continuous bidirectional, continuous recirculate); - Profile switching for RAM playback; - Sampling frequency control via profile step rate; - ram_en-aware read/write paths that redirect single tone frequency/phase/amplitude access through reg_profile cache when RAM is active; When RAM is enabled, the DDS core parameters (frequency, phase, amplitude) for the single tone channel are sourced from a shadow register cache (reg_profile[]) since the profile registers are repurposed for RAM control. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 474 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 455 insertions(+), 19 deletions(-) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index 84698bf2dc4e..8fd7ebe7e6b0 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -150,6 +150,15 @@ #define AD9910_PROFILE_ST_POW_MSK GENMASK_ULL(47, 32) #define AD9910_PROFILE_ST_FTW_MSK AD9910_REG_LOW32_MSK =20 +/* Profile Register Format (RAM Mode) */ +#define AD9910_PROFILE_RAM_OPEN_MSK GENMASK_ULL(61, 57) +#define AD9910_PROFILE_RAM_STEP_RATE_MSK GENMASK_ULL(55, 40) +#define AD9910_PROFILE_RAM_END_ADDR_MSK GENMASK_ULL(39, 30) +#define AD9910_PROFILE_RAM_START_ADDR_MSK GENMASK_ULL(23, 14) +#define AD9910_PROFILE_RAM_NO_DWELL_HIGH_MSK BIT_ULL(5) +#define AD9910_PROFILE_RAM_ZERO_CROSSING_MSK BIT_ULL(3) +#define AD9910_PROFILE_RAM_MODE_CONTROL_MSK GENMASK_ULL(2, 0) + /* Device constants */ #define AD9910_PI_NANORAD 3141592653UL =20 @@ -164,6 +173,14 @@ #define AD9910_NUM_PROFILES 8 =20 #define AD9910_DRG_DEST_NUM 3 +#define AD9910_RAM_DEST_NUM 4 + +#define AD9910_RAM_SIZE_MAX_WORDS 1024 +#define AD9910_RAM_WORD_SIZE sizeof(u32) +#define AD9910_RAM_SIZE_MAX_BYTES (AD9910_RAM_SIZE_MAX_WORDS * AD9910_RAM_= WORD_SIZE) +#define AD9910_RAM_ADDR_MAX (AD9910_RAM_SIZE_MAX_WORDS - 1) + +#define AD9910_RAM_PROFILE_CTL_CONT_MSK BIT(4) =20 /* PLL constants */ #define AD9910_PLL_MIN_N 12 @@ -208,6 +225,7 @@ enum ad9910_channel { AD9910_CHANNEL_SINGLE_TONE, AD9910_CHANNEL_PARALLEL_PORT, AD9910_CHANNEL_DRG, + AD9910_CHANNEL_RAM, }; =20 /** @@ -235,6 +253,27 @@ enum ad9910_drg_oper_mode { AD9910_DRG_OPER_MODE_BIDIR_CONT, }; =20 +/** + * enum ad9910_ram_oper_mode - AD9910 RAM Playback Operating Mode + * + * @AD9910_RAM_MODE_DIRECT_SWITCH: Direct profile switching between profil= es + * @AD9910_RAM_MODE_RAMP_UP: Ramp up for current profile + * @AD9910_RAM_MODE_BIDIR: Ramp up/down for profile 0 + * @AD9910_RAM_MODE_BIDIR_CONT: Continuous ramp up/down for current profile + * @AD9910_RAM_MODE_RAMP_UP_CONT: Continuous ramp up for current profile + * @AD9910_RAM_MODE_SEQ: Sequenced playback of RAM profiles up to target p= rofile + * @AD9910_RAM_MODE_SEQ_CONT: Continuous sequenced playback of RAM profiles + */ +enum ad9910_ram_oper_mode { + AD9910_RAM_MODE_DIRECT_SWITCH, + AD9910_RAM_MODE_RAMP_UP, + AD9910_RAM_MODE_BIDIR, + AD9910_RAM_MODE_BIDIR_CONT, + AD9910_RAM_MODE_RAMP_UP_CONT, + AD9910_RAM_MODE_SEQ, + AD9910_RAM_MODE_SEQ_CONT, +}; + enum { AD9910_PROFILE, AD9910_POWERDOWN, @@ -256,6 +295,8 @@ enum { AD9910_DRG_AMP_DEC_STEP, AD9910_DRG_INC_STEP_RATE, AD9910_DRG_DEC_STEP_RATE, + AD9910_RAM_START_ADDR, + AD9910_RAM_END_ADDR, }; =20 struct ad9910_data { @@ -294,6 +335,13 @@ struct ad9910_state { u16 val16; } reg[AD9910_REG_NUM_CACHED]; =20 + /* + * alternate profile registers used to store RAM profile settings when + * RAM mode is disabled and Single Tone profile settings when RAM mode + * is enabled. + */ + u64 reg_profile[AD9910_NUM_PROFILES]; + /* * Lock for accessing device registers and state variables. */ @@ -331,6 +379,16 @@ static const char * const ad9910_drg_oper_mode_str[] = =3D { [AD9910_DRG_OPER_MODE_BIDIR_CONT] =3D "bidirectional_continuous", }; =20 +static const char * const ad9910_ram_oper_mode_str[] =3D { + [AD9910_RAM_MODE_DIRECT_SWITCH] =3D "direct_switch", + [AD9910_RAM_MODE_RAMP_UP] =3D "ramp_up", + [AD9910_RAM_MODE_BIDIR] =3D "bidirectional", + [AD9910_RAM_MODE_BIDIR_CONT] =3D "bidirectional_continuous", + [AD9910_RAM_MODE_RAMP_UP_CONT] =3D "ramp_up_continuous", + [AD9910_RAM_MODE_SEQ] =3D "sequenced", + [AD9910_RAM_MODE_SEQ_CONT] =3D "sequenced_continuous", +}; + /** * ad9910_rational_scale() - Perform scaling of input given a reference. * @input: The input value to be scaled. @@ -377,6 +435,18 @@ static inline int ad9910_spi_write(struct ad9910_state= *st, u8 reg, size_t len, return ret; } =20 +static inline int ad9910_ram_load(struct ad9910_state *st, void *data, + size_t count) +{ + struct spi_transfer t[] =3D { + { .tx_buf =3D st->buf, .len =3D 1, }, + { .tx_buf =3D data, .len =3D count, }, + }; + + st->buf[0] =3D AD9910_REG_RAM; + return spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); +} + #define AD9910_REG_READ_FN(nb) \ static inline int ad9910_reg##nb##_read(struct ad9910_state *st, \ u8 reg, u##nb * data) \ @@ -464,6 +534,14 @@ static int ad9910_chan_destination_set(struct iio_dev = *indio_dev, AD9910_CFR2_DRG_DEST_MSK, FIELD_PREP(AD9910_CFR2_DRG_DEST_MSK, val), true); + case AD9910_CHANNEL_RAM: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + return -EBUSY; + + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_RAM_PLAYBACK_DEST_MSK, + FIELD_PREP(AD9910_CFR1_RAM_PLAYBACK_DEST_MSK, val), + true); default: return -EINVAL; } @@ -480,6 +558,9 @@ static int ad9910_chan_destination_get(struct iio_dev *= indio_dev, case AD9910_CHANNEL_DRG: return FIELD_GET(AD9910_CFR2_DRG_DEST_MSK, st->reg[AD9910_REG_CFR2].val32); + case AD9910_CHANNEL_RAM: + return FIELD_GET(AD9910_CFR1_RAM_PLAYBACK_DEST_MSK, + st->reg[AD9910_REG_CFR1].val32); default: return -EINVAL; } @@ -510,6 +591,93 @@ static int ad9910_drg_oper_mode_get(struct iio_dev *in= dio_dev, st->reg[AD9910_REG_CFR2].val32); } =20 +static int ad9910_ram_oper_mode_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + u32 profile_ctl; + int ret; + + guard(mutex)(&st->lock); + + /* + * RAM sequenced modes use the internal profile control: + * - Sequence mode takes precedence over regular profile modes + * - Active profile defines the internal profile control target + * - Profile 0 cannot be used as sequenced mode target + * - Profile X cannot be set as sequenced mode target if another + * profile is currently set. + */ + profile_ctl =3D FIELD_GET(AD9910_CFR1_INT_PROFILE_CTL_MSK, + st->reg[AD9910_REG_CFR1].val32); + if (AD9910_RAM_PROFILE_CTL_CONT_MSK & profile_ctl) + profile_ctl =3D (profile_ctl & ~AD9910_RAM_PROFILE_CTL_CONT_MSK) + 1; + + if (val >=3D AD9910_RAM_MODE_SEQ) { + if (!st->profile) + return -EINVAL; + + if (profile_ctl && profile_ctl !=3D st->profile) + return -EBUSY; + + /* update profile control */ + profile_ctl =3D st->profile; + if (val =3D=3D AD9910_RAM_MODE_SEQ_CONT) + profile_ctl =3D AD9910_RAM_PROFILE_CTL_CONT_MSK | (profile_ctl - 1); + profile_ctl =3D FIELD_PREP(AD9910_CFR1_INT_PROFILE_CTL_MSK, profile_ctl); + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_INT_PROFILE_CTL_MSK, + profile_ctl, true); + } + + if (profile_ctl && profile_ctl =3D=3D st->profile) { + /* clear internal profile control */ + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_INT_PROFILE_CTL_MSK, + 0, true); + if (ret) + return ret; + } + + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32)) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + FIELD_PREP(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, val), + true); + + FIELD_MODIFY(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + &st->reg_profile[st->profile], val); + return 0; +} + +static int ad9910_ram_oper_mode_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + u32 profile_ctl; + bool seq_cont =3D false; + + guard(mutex)(&st->lock); + + profile_ctl =3D FIELD_GET(AD9910_CFR1_INT_PROFILE_CTL_MSK, + st->reg[AD9910_REG_CFR1].val32); + if (AD9910_RAM_PROFILE_CTL_CONT_MSK & profile_ctl) { + seq_cont =3D true; + profile_ctl =3D (profile_ctl & ~AD9910_RAM_PROFILE_CTL_CONT_MSK) + 1; + } + + if (profile_ctl && profile_ctl =3D=3D st->profile) + return (seq_cont) ? AD9910_RAM_MODE_SEQ_CONT : AD9910_RAM_MODE_SEQ; + + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32)) + return FIELD_GET(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + return FIELD_GET(AD9910_PROFILE_RAM_MODE_CONTROL_MSK, + st->reg_profile[st->profile]); +} + static ssize_t ad9910_ext_info_read(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, @@ -532,6 +700,22 @@ static ssize_t ad9910_ext_info_read(struct iio_dev *in= dio_dev, val =3D BIT(FIELD_GET(AD9910_CFR2_FM_GAIN_MSK, st->reg[AD9910_REG_CFR2].val32)); break; + case AD9910_RAM_START_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + val =3D FIELD_GET(AD9910_PROFILE_RAM_START_ADDR_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + val =3D FIELD_GET(AD9910_PROFILE_RAM_START_ADDR_MSK, + st->reg_profile[st->profile]); + break; + case AD9910_RAM_END_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + val =3D FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + val =3D FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, + st->reg_profile[st->profile]); + break; default: return -EINVAL; } @@ -576,6 +760,33 @@ static ssize_t ad9910_ext_info_write(struct iio_dev *i= ndio_dev, AD9910_CFR2_FM_GAIN_MSK, val32, true); break; + case AD9910_RAM_START_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + return -EBUSY; + + if (val32 > AD9910_RAM_ADDR_MAX) + return -EINVAL; + + if (val32 > FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, + st->reg_profile[st->profile])) + FIELD_MODIFY(AD9910_PROFILE_RAM_END_ADDR_MSK, + &st->reg_profile[st->profile], val32); + + FIELD_MODIFY(AD9910_PROFILE_RAM_START_ADDR_MSK, + &st->reg_profile[st->profile], val32); + break; + case AD9910_RAM_END_ADDR: + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32= )) + return -EBUSY; + + if (val32 > AD9910_RAM_ADDR_MAX || + val32 < FIELD_GET(AD9910_PROFILE_RAM_START_ADDR_MSK, + st->reg_profile[st->profile])) + return -EINVAL; + + FIELD_MODIFY(AD9910_PROFILE_RAM_END_ADDR_MSK, + &st->reg_profile[st->profile], val32); + break; default: return -EINVAL; } @@ -967,6 +1178,20 @@ static const struct iio_enum ad9910_drg_oper_mode_enu= m =3D { .get =3D ad9910_drg_oper_mode_get, }; =20 +static const struct iio_enum ad9910_ram_destination_enum =3D { + .items =3D ad9910_destination_str, + .num_items =3D AD9910_RAM_DEST_NUM, + .set =3D ad9910_chan_destination_set, + .get =3D ad9910_chan_destination_get, +}; + +static const struct iio_enum ad9910_ram_oper_mode_enum =3D { + .items =3D ad9910_ram_oper_mode_str, + .num_items =3D ARRAY_SIZE(ad9910_ram_oper_mode_str), + .set =3D ad9910_ram_oper_mode_set, + .get =3D ad9910_ram_oper_mode_get, +}; + static const struct iio_chan_spec_ext_info ad9910_shared_ext_info[] =3D { AD9910_EXT_INFO("profile", AD9910_PROFILE, IIO_SHARED_BY_TYPE), AD9910_EXT_INFO("powerdown", AD9910_POWERDOWN, IIO_SHARED_BY_TYPE), @@ -1003,6 +1228,16 @@ static const struct iio_chan_spec_ext_info ad9910_dr= g_ext_info[] =3D { { }, }; =20 +static const struct iio_chan_spec_ext_info ad9910_ram_ext_info[] =3D { + IIO_ENUM("destination", IIO_SEPARATE, &ad9910_ram_destination_enum), + IIO_ENUM_AVAILABLE("destination", IIO_SEPARATE, &ad9910_ram_destination_e= num), + IIO_ENUM("operating_mode", IIO_SEPARATE, &ad9910_ram_oper_mode_enum), + IIO_ENUM_AVAILABLE("operating_mode", IIO_SEPARATE, &ad9910_ram_oper_mode_= enum), + AD9910_EXT_INFO("address_start", AD9910_RAM_START_ADDR, IIO_SEPARATE), + AD9910_EXT_INFO("address_end", AD9910_RAM_END_ADDR, IIO_SEPARATE), + { }, +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHANNEL_SINGLE_TONE] =3D { .type =3D IIO_ALTVOLTAGE, @@ -1032,6 +1267,18 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE), .ext_info =3D ad9910_drg_ext_info, }, + [AD9910_CHANNEL_RAM] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_RAM, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_FREQUENCY) | + BIT(IIO_CHAN_INFO_PHASE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info =3D ad9910_ram_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -1040,10 +1287,13 @@ static int ad9910_read_raw(struct iio_dev *indio_de= v, { struct ad9910_state *st =3D iio_priv(indio_dev); u64 tmp64; - u32 tmp32; + u32 tmp32, ram_en; =20 guard(mutex)(&st->lock); =20 + ram_en =3D FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, + st->reg[AD9910_REG_CFR1].val32); + switch (info) { case IIO_CHAN_INFO_ENABLE: switch (chan->channel) { @@ -1055,30 +1305,77 @@ static int ad9910_read_raw(struct iio_dev *indio_de= v, *val =3D FIELD_GET(AD9910_CFR2_DRG_ENABLE_MSK, st->reg[AD9910_REG_CFR2].val32); break; + case AD9910_CHANNEL_RAM: + *val =3D ram_en; + break; default: return -EINVAL; } return IIO_VAL_INT; case IIO_CHAN_INFO_FREQUENCY: - tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, - st->reg[AD9910_REG_PROFILE(st->profile)].val64); + if (chan->channel =3D=3D AD9910_CHANNEL_SINGLE_TONE) { + if (!ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_FTW_MSK, + st->reg_profile[st->profile]); + } else { + tmp32 =3D st->reg[AD9910_REG_FTW].val32; + } tmp64 =3D (u64)tmp32 * st->data.sysclk_freq_hz; *val =3D upper_32_bits(tmp64); *val2 =3D upper_32_bits((u64)lower_32_bits(tmp64) * MICRO); return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_PHASE: - tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, - st->reg[AD9910_REG_PROFILE(st->profile)].val64); + if (chan->channel =3D=3D AD9910_CHANNEL_SINGLE_TONE) { + if (!ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_POW_MSK, + st->reg_profile[st->profile]); + } else { + tmp32 =3D st->reg[AD9910_REG_POW].val16; + } tmp32 =3D ((u64)tmp32 * AD9910_MAX_PHASE_MICRORAD) >> 16; *val =3D tmp32 / MICRO; *val2 =3D tmp32 % MICRO; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_SCALE: - tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, - st->reg[AD9910_REG_PROFILE(st->profile)].val64); + if (chan->channel =3D=3D AD9910_CHANNEL_SINGLE_TONE) { + if (!ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_ST_ASF_MSK, + st->reg_profile[st->profile]); + } else { + tmp32 =3D FIELD_GET(AD9910_ASF_SCALE_FACTOR_MSK, + st->reg[AD9910_REG_ASF].val32); + } *val =3D 0; *val2 =3D (u64)tmp32 * MICRO >> 14; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + switch (chan->channel) { + case AD9910_CHANNEL_RAM: + if (ram_en) + tmp32 =3D FIELD_GET(AD9910_PROFILE_RAM_STEP_RATE_MSK, + st->reg[AD9910_REG_PROFILE(st->profile)].val64); + else + tmp32 =3D FIELD_GET(AD9910_PROFILE_RAM_STEP_RATE_MSK, + st->reg_profile[st->profile]); + break; + default: + return -EINVAL; + } + if (!tmp32) + return -ERANGE; + tmp32 *=3D 4; + *val =3D st->data.sysclk_freq_hz / tmp32; + *val2 =3D div_u64((u64)(st->data.sysclk_freq_hz % tmp32) * MICRO, tmp32); + return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; } @@ -1092,9 +1389,13 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, u64 tmp64; u32 tmp32; u16 tmp16; + int ram_en, ret =3D 0; =20 guard(mutex)(&st->lock); =20 + ram_en =3D FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, + st->reg[AD9910_REG_CFR1].val32); + switch (info) { case IIO_CHAN_INFO_ENABLE: val =3D val ? 1 : 0; @@ -1109,6 +1410,26 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, return ad9910_reg32_update(st, AD9910_REG_CFR2, AD9910_CFR2_DRG_ENABLE_MSK, tmp32, true); + case AD9910_CHANNEL_RAM: + if (ram_en =3D=3D val) + return 0; + + /* switch profile configs */ + for (int i =3D 0; i < AD9910_NUM_PROFILES; i++) { + tmp64 =3D st->reg[AD9910_REG_PROFILE(i)].val64; + ret =3D ad9910_reg64_write(st, + AD9910_REG_PROFILE(i), + st->reg_profile[i], + false); + if (ret) + return ret; + st->reg_profile[i] =3D tmp64; + } + + tmp32 =3D FIELD_PREP(AD9910_CFR1_RAM_ENABLE_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_RAM_ENABLE_MSK, + tmp32, true); default: return -EINVAL; } @@ -1118,10 +1439,18 @@ static int ad9910_write_raw(struct iio_dev *indio_d= ev, =20 tmp32 =3D ad9910_rational_scale((u64)val * MICRO + val2, BIT_ULL(32), (u64)MICRO * st->data.sysclk_freq_hz); - return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), - AD9910_PROFILE_ST_FTW_MSK, - FIELD_PREP(AD9910_PROFILE_ST_FTW_MSK, tmp32), - true); + if (chan->channel !=3D AD9910_CHANNEL_SINGLE_TONE) + return ad9910_reg32_write(st, AD9910_REG_FTW, tmp32, true); + + if (!ram_en) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_FTW_MSK, + FIELD_PREP(AD9910_PROFILE_ST_FTW_MSK, tmp32), + true); + + FIELD_MODIFY(AD9910_PROFILE_ST_FTW_MSK, + &st->reg_profile[st->profile], tmp32); + break; case IIO_CHAN_INFO_PHASE: tmp64 =3D (u64)val * MICRO + val2; if (val < 0 || val2 < 0 || tmp64 >=3D AD9910_MAX_PHASE_MICRORAD) @@ -1129,10 +1458,19 @@ static int ad9910_write_raw(struct iio_dev *indio_d= ev, =20 tmp32 =3D DIV_U64_ROUND_CLOSEST(tmp64 << 16, AD9910_MAX_PHASE_MICRORAD); tmp16 =3D min(tmp32, AD9910_POW_MAX); - return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), - AD9910_PROFILE_ST_POW_MSK, - FIELD_PREP(AD9910_PROFILE_ST_POW_MSK, tmp16), - true); + + if (chan->channel !=3D AD9910_CHANNEL_SINGLE_TONE) + return ad9910_reg16_write(st, AD9910_REG_POW, tmp16, true); + + if (!ram_en) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_POW_MSK, + FIELD_PREP(AD9910_PROFILE_ST_POW_MSK, tmp16), + true); + + FIELD_MODIFY(AD9910_PROFILE_ST_POW_MSK, + &st->reg_profile[st->profile], tmp16); + break; case IIO_CHAN_INFO_SCALE: if (val < 0 || val > 1 || (val =3D=3D 1 && val2 > 0)) return -EINVAL; @@ -1140,13 +1478,51 @@ static int ad9910_write_raw(struct iio_dev *indio_d= ev, tmp64 =3D ((u64)val * MICRO + val2) << 14; tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, MICRO); tmp16 =3D min(tmp64, AD9910_ASF_MAX); - return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), - AD9910_PROFILE_ST_ASF_MSK, - FIELD_PREP(AD9910_PROFILE_ST_ASF_MSK, tmp16), - true); + + if (chan->channel !=3D AD9910_CHANNEL_SINGLE_TONE) + return ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_SCALE_FACTOR_MSK, + FIELD_PREP(AD9910_ASF_SCALE_FACTOR_MSK, tmp16), + true); + + if (!ram_en) + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_ST_ASF_MSK, + FIELD_PREP(AD9910_PROFILE_ST_ASF_MSK, tmp16), + true); + + FIELD_MODIFY(AD9910_PROFILE_ST_ASF_MSK, + &st->reg_profile[st->profile], tmp16); + break; + case IIO_CHAN_INFO_SAMP_FREQ: + tmp64 =3D ((u64)val * MICRO + val2) * 4; + if (!tmp64) + return -EINVAL; + + tmp64 =3D DIV64_U64_ROUND_CLOSEST((u64)st->data.sysclk_freq_hz * MICRO, = tmp64); + tmp32 =3D clamp(tmp64, 1U, AD9910_STEP_RATE_MAX); + + switch (chan->channel) { + case AD9910_CHANNEL_RAM: + if (ram_en) { + tmp64 =3D FIELD_PREP(AD9910_PROFILE_RAM_STEP_RATE_MSK, tmp32); + return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), + AD9910_PROFILE_RAM_STEP_RATE_MSK, + tmp64, true); + } + + FIELD_MODIFY(AD9910_PROFILE_RAM_STEP_RATE_MSK, + &st->reg_profile[st->profile], tmp32); + break; + default: + return -EINVAL; + } + break; default: return -EINVAL; } + + return ret; } =20 static int ad9910_write_raw_get_fmt(struct iio_dev *indio_dev, @@ -1159,6 +1535,7 @@ static int ad9910_write_raw_get_fmt(struct iio_dev *i= ndio_dev, case IIO_CHAN_INFO_FREQUENCY: case IIO_CHAN_INFO_PHASE: case IIO_CHAN_INFO_SCALE: + case IIO_CHAN_INFO_SAMP_FREQ: return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; @@ -1247,13 +1624,65 @@ static ssize_t sysclk_frequency_show(struct device = *dev, =20 static IIO_DEVICE_ATTR_RO(sysclk_frequency, 0); =20 +static ssize_t ram_data_write(struct file *filp, struct kobject *kobj, + const struct bin_attribute *attr, char *buf, + loff_t off, size_t count) +{ + struct ad9910_state *st =3D iio_priv(dev_to_iio_dev(kobj_to_dev(kobj))); + u64 tmp64, backup; + u32 start, end; + int ret, ret2; + + if (off + count > AD9910_RAM_SIZE_MAX_BYTES || !count || + off % AD9910_RAM_WORD_SIZE !=3D 0 || + count % AD9910_RAM_WORD_SIZE !=3D 0) + return -EINVAL; + + guard(mutex)(&st->lock); + + if (FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32)) + return -EBUSY; + + /* ensure profile is selected */ + ret =3D ad9910_profile_set(st, st->profile); + if (ret) + return ret; + + /* backup profile register */ + backup =3D st->reg[AD9910_REG_PROFILE(st->profile)].val64; + start =3D off / AD9910_RAM_WORD_SIZE; + end =3D (off + count) / AD9910_RAM_WORD_SIZE - 1; + tmp64 =3D AD9910_PROFILE_RAM_STEP_RATE_MSK | + FIELD_PREP(AD9910_PROFILE_RAM_START_ADDR_MSK, start) | + FIELD_PREP(AD9910_PROFILE_RAM_END_ADDR_MSK, end); + ret =3D ad9910_reg64_write(st, AD9910_REG_PROFILE(st->profile), tmp64, tr= ue); + if (ret) + return ret; + + /* write ram data and restore profile register */ + ret =3D ad9910_ram_load(st, buf, count); + ret2 =3D ad9910_reg64_write(st, AD9910_REG_PROFILE(st->profile), backup, = true); + if (!ret) + ret =3D ret2; + + return ret ?: count; +} + +static const BIN_ATTR_WO(ram_data, AD9910_RAM_SIZE_MAX_BYTES); + static struct attribute *ad9910_attrs[] =3D { &iio_dev_attr_sysclk_frequency.dev_attr.attr, NULL }; =20 +static const struct bin_attribute *const ad9910_bin_attrs[] =3D { + &bin_attr_ram_data, + NULL +}; + static const struct attribute_group ad9910_attrs_group =3D { .attrs =3D ad9910_attrs, + .bin_attrs =3D ad9910_bin_attrs, }; =20 static const struct iio_info ad9910_info =3D { @@ -1426,6 +1855,13 @@ static int ad9910_setup(struct ad9910_state *st, str= uct reset_control *dev_rst) if (ret) return ret; =20 + for (int i =3D 0; i < AD9910_NUM_PROFILES; i++) { + st->reg_profile[i] =3D AD9910_PROFILE_RAM_OPEN_MSK; + st->reg_profile[i] |=3D FIELD_PREP(AD9910_PROFILE_RAM_STEP_RATE_MSK, 1); + st->reg_profile[i] |=3D FIELD_PREP(AD9910_PROFILE_RAM_END_ADDR_MSK, + AD9910_RAM_ADDR_MAX); + } + return ad9910_io_update(st); } =20 --=20 2.43.0 From nobody Fri Apr 3 11:13:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C7E22FF641; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WwzkMNGT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 25FB7C19425; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771605988; bh=66S/3dHCal6dQuZeH2WCVD4Wt7NAb3fiSPC3kcxdERw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WwzkMNGT78L/wv3+TyDVm3ffRW7MsxFlZ2oYpS6zA+tKDYFx0trAM1F1jjn2ZmLGn BUm2WwOD7VXFZcUbU4bR4SCfIMUQgEOj8vwGqhqUMO+BA5iHn1bFb2sxGQMHqUv+cq 0jPaa4X6VKMvSNbFE2pUyP/tpLajvuAFq8gkSs6EecrNMDD31RyidInxIyzAtoOX1T xeyq/MldVPeRNbJLyOwjLPPxUxP7L7yMsEiDcwVP2Vpw1ULUjeZ+dn6KWbvIyULiEk yiNbZcPfbkGdpn2aFGUEM/ogRqlhwdjbMtCURKla8BAZuQnjC9RNzPBIGl1IAHVWe/ F9Q6jjm44al7A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19390C5ACD3; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Fri, 20 Feb 2026 16:46:11 +0000 Subject: [PATCH RFC 7/8] iio: frequency: ad9910: add output shift keying support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-7-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=8106; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=OhIk+av1p8HCXxsb5d7GcpUKKkjp1UH2L+GCFadESMQ=; b=i3OKD9TmkUNQdSTmJyqNiGktuMl+O+/tODsf38UqR9d4pEVJBgwH20Lr/26P638ClEwC2sx2B 6VsRhzJNHGQDaF3exJQi01mJgU4nFc/KtZNayreKw4xSmZcawXyPQ5Q X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add OSK channel with amplitude envelope control capabilities: - OSK enable/disable via IIO_CHAN_INFO_ENABLE; - Amplitude ramp rate control via IIO_CHAN_INFO_SAMP_FREQ; - Amplitude scale readback via IIO_CHAN_INFO_SCALE (ASF register); - Manual/external pin control via pinctrl_en ext_info attribute; - Automatic OSK step size configuration via scale_increment ext_info; attribute with selectable step sizes (61, 122, 244, 488 micro-units) The ASF register is initialized with a default amplitude ramp rate during device setup to ensure valid SAMP_FREQ readback. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 134 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 134 insertions(+) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index 8fd7ebe7e6b0..b1540b157a0e 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -226,6 +226,7 @@ enum ad9910_channel { AD9910_CHANNEL_PARALLEL_PORT, AD9910_CHANNEL_DRG, AD9910_CHANNEL_RAM, + AD9910_CHANNEL_OSK, }; =20 /** @@ -297,6 +298,8 @@ enum { AD9910_DRG_DEC_STEP_RATE, AD9910_RAM_START_ADDR, AD9910_RAM_END_ADDR, + AD9910_OSK_MANUAL_EXTCTL, + AD9910_OSK_AUTO_STEP, }; =20 struct ad9910_data { @@ -389,6 +392,10 @@ static const char * const ad9910_ram_oper_mode_str[] = =3D { [AD9910_RAM_MODE_SEQ_CONT] =3D "sequenced_continuous", }; =20 +static const u16 ad9910_osk_ustep[] =3D { + 0, 61, 122, 244, 488, +}; + /** * ad9910_rational_scale() - Perform scaling of input given a reference. * @input: The input value to be scaled. @@ -716,6 +723,10 @@ static ssize_t ad9910_ext_info_read(struct iio_dev *in= dio_dev, val =3D FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, st->reg_profile[st->profile]); break; + case AD9910_OSK_MANUAL_EXTCTL: + val =3D FIELD_GET(AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK, + st->reg[AD9910_REG_CFR1].val32); + break; default: return -EINVAL; } @@ -787,6 +798,12 @@ static ssize_t ad9910_ext_info_write(struct iio_dev *i= ndio_dev, FIELD_MODIFY(AD9910_PROFILE_RAM_END_ADDR_MSK, &st->reg_profile[st->profile], val32); break; + case AD9910_OSK_MANUAL_EXTCTL: + val32 =3D val32 ? AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK : 0; + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK, + val32, true); + break; default: return -EINVAL; } @@ -1144,6 +1161,80 @@ static ssize_t ad9910_drg_attrs_write(struct iio_dev= *indio_dev, return ret ?: len; } =20 +static ssize_t ad9910_osk_attrs_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int vals[2]; + bool auto_en; + u32 raw_val; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_OSK_AUTO_STEP: + auto_en =3D FIELD_GET(AD9910_CFR1_SELECT_AUTO_OSK_MSK, + st->reg[AD9910_REG_CFR1].val32); + raw_val =3D FIELD_GET(AD9910_ASF_STEP_SIZE_MSK, + st->reg[AD9910_REG_ASF].val32); + vals[0] =3D 0; + vals[1] =3D auto_en ? ad9910_osk_ustep[raw_val + 1] : 0; + + return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals); + default: + return -EINVAL; + } +} + +static ssize_t ad9910_osk_attrs_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + int ret; + u32 raw_val; + + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_OSK_AUTO_STEP: + if (val !=3D 0) + return -EINVAL; + + raw_val =3D find_closest(val2, ad9910_osk_ustep, + ARRAY_SIZE(ad9910_osk_ustep)); + if (raw_val) { + /* set OSK step and get automatic OSK enabled */ + raw_val =3D FIELD_PREP(AD9910_ASF_STEP_SIZE_MSK, + raw_val - 1); + ret =3D ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_STEP_SIZE_MSK, + raw_val, true); + if (ret) + return ret; + + raw_val =3D AD9910_CFR1_SELECT_AUTO_OSK_MSK; + } + + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_SELECT_AUTO_OSK_MSK, + raw_val, true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + #define AD9910_EXT_INFO_TMPL(_name, _ident, _shared, _fn_desc) { \ .name =3D _name, \ .read =3D ad9910_ ## _fn_desc ## _read, \ @@ -1164,6 +1255,9 @@ static ssize_t ad9910_drg_attrs_write(struct iio_dev = *indio_dev, #define AD9910_DRG_EXT_INFO(_name, _ident) \ AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, drg_attrs) =20 +#define AD9910_OSK_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, osk_attrs) + static const struct iio_enum ad9910_drg_destination_enum =3D { .items =3D ad9910_destination_str, .num_items =3D AD9910_DRG_DEST_NUM, @@ -1238,6 +1332,12 @@ static const struct iio_chan_spec_ext_info ad9910_ra= m_ext_info[] =3D { { }, }; =20 +static const struct iio_chan_spec_ext_info ad9910_osk_ext_info[] =3D { + AD9910_EXT_INFO("pinctrl_en", AD9910_OSK_MANUAL_EXTCTL, IIO_SEPARATE), + AD9910_OSK_EXT_INFO("scale_increment", AD9910_OSK_AUTO_STEP), + { }, +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHANNEL_SINGLE_TONE] =3D { .type =3D IIO_ALTVOLTAGE, @@ -1279,6 +1379,17 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { BIT(IIO_CHAN_INFO_SAMP_FREQ), .ext_info =3D ad9910_ram_ext_info, }, + [AD9910_CHANNEL_OSK] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_OSK, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info =3D ad9910_osk_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -1308,6 +1419,10 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, case AD9910_CHANNEL_RAM: *val =3D ram_en; break; + case AD9910_CHANNEL_OSK: + *val =3D FIELD_GET(AD9910_CFR1_OSK_ENABLE_MSK, + st->reg[AD9910_REG_CFR1].val32); + break; default: return -EINVAL; } @@ -1367,6 +1482,10 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, tmp32 =3D FIELD_GET(AD9910_PROFILE_RAM_STEP_RATE_MSK, st->reg_profile[st->profile]); break; + case AD9910_CHANNEL_OSK: + tmp32 =3D FIELD_GET(AD9910_ASF_RAMP_RATE_MSK, + st->reg[AD9910_REG_ASF].val32); + break; default: return -EINVAL; } @@ -1430,6 +1549,11 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, return ad9910_reg32_update(st, AD9910_REG_CFR1, AD9910_CFR1_RAM_ENABLE_MSK, tmp32, true); + case AD9910_CHANNEL_OSK: + tmp32 =3D FIELD_PREP(AD9910_CFR1_OSK_ENABLE_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_OSK_ENABLE_MSK, + tmp32, true); default: return -EINVAL; } @@ -1514,6 +1638,11 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, FIELD_MODIFY(AD9910_PROFILE_RAM_STEP_RATE_MSK, &st->reg_profile[st->profile], tmp32); break; + case AD9910_CHANNEL_OSK: + return ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_RAMP_RATE_MSK, + FIELD_PREP(AD9910_ASF_RAMP_RATE_MSK, tmp32), + true); default: return -EINVAL; } @@ -1849,6 +1978,11 @@ static int ad9910_setup(struct ad9910_state *st, str= uct reset_control *dev_rst) return ret; =20 /* configure step rate with default values */ + reg32 =3D FIELD_PREP(AD9910_ASF_RAMP_RATE_MSK, 1); + ret =3D ad9910_reg32_write(st, AD9910_REG_ASF, reg32, false); + if (ret) + return ret; + reg32 =3D FIELD_PREP(AD9910_DRG_RATE_DEC_MSK, 1) | FIELD_PREP(AD9910_DRG_RATE_INC_MSK, 1); ret =3D ad9910_reg32_write(st, AD9910_REG_DRG_RATE, reg32, false); --=20 2.43.0 From nobody Fri Apr 3 11:13:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6539B2FFDCB; Fri, 20 Feb 2026 16:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260220-ad9910-iio-driver-v1-8-3b264aa48a10@analog.com> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> In-Reply-To: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771605986; l=1464; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=XVRMytzjE0Xjg264u9puMX+fiQxZ2hkudN/VqdIWRLk=; b=5SaIsbhoNyh6zvARQPcFhGGl1gTCcLezdZHcHhu0tnqnvxY6Rl6ozdCQ2urKHFjRFx6uWdemu mCfxMLVBs8tAgqn63Km3Kna/REqHbpQRL+6EuIKW9WGWJAg+1J8Irlq X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add human-readable labels for all AD9910 IIO channels via the read_label callback: single_tone, parallel_port, digital_ramp_generator, ram_control, and output_shift_keying. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index b1540b157a0e..e983614805b4 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -1814,10 +1814,26 @@ static const struct attribute_group ad9910_attrs_gr= oup =3D { .bin_attrs =3D ad9910_bin_attrs, }; =20 +static const char * const ad9910_channel_str[] =3D { + [AD9910_CHANNEL_SINGLE_TONE] =3D "single_tone", + [AD9910_CHANNEL_PARALLEL_PORT] =3D "parallel_port", + [AD9910_CHANNEL_DRG] =3D "digital_ramp_generator", + [AD9910_CHANNEL_RAM] =3D "ram_control", + [AD9910_CHANNEL_OSK] =3D "output_shift_keying", +}; + +static int ad9910_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + char *label) +{ + return sprintf(label, "%s\n", ad9910_channel_str[chan->channel]); +} + static const struct iio_info ad9910_info =3D { .read_raw =3D ad9910_read_raw, .write_raw =3D ad9910_write_raw, .write_raw_get_fmt =3D ad9910_write_raw_get_fmt, + .read_label =3D ad9910_read_label, .attrs =3D &ad9910_attrs_group, .debugfs_reg_access =3D &ad9910_reg_access, }; --=20 2.43.0