From nobody Mon Apr 6 09:20:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED4402777F3; Fri, 20 Feb 2026 04:07:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771560471; cv=none; b=lPfD0USO9WAS991R0wZ4eRi9Ke9v6kyk0apKp4MRyurGNvuk6IWsM4G1mq3q6cnip9ZII4AhTcDRoTyLqD6EqT6PVdklzaSXD+9sQjC+sMjwbGlR3BpX443cqdmZVIUdOfodYE5osRFl3O9J1IRvQ7PjZZEn4TfIcpLxBOdY8hQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771560471; c=relaxed/simple; bh=kc6F+SBT+t6RBPoescqazJkCAj0W3LZVUOZACt/NSVo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n76ER3457DrQOhv0GxtxRUQ4s7ffp97VZQCl/mSjKyy3Q+hVbbyVqyzqRSPJS3N27AvLKc/9QG/sXaVwbORQ9fLVi780K5nWDcvlmTVE+h94kWR7BKA5Vb3SNCZxmZ45uHV97KhuVUCiXVeB/h3VbX472QGOpRa9nfD/vC77PLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ojTeck12; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ojTeck12" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9FE8AC4AF0B; Fri, 20 Feb 2026 04:07:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771560470; bh=kc6F+SBT+t6RBPoescqazJkCAj0W3LZVUOZACt/NSVo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ojTeck125QIyvfKidocpfUBrDapSZVV6C3gO/+67DSAQhnC0seVaAR6xueO+o8iRy Yy/DajFDjNbXKQ340pf6Iz+aHzpCCB0G/zwhZaKo+LWCNEOfjFlmAeJM77v57wHAP0 fmkOvDWkPma48C8xiuFSoxl7ciBFQjUcFnZuQNB3vusgoHwNhM9UtJW2Yc6YuDM9Pk xHVKCs3q3Ee19T6ZZNQoC8GcOvJBGli4w6t4Qcu3ro0WocAZrx18NpTiRCUVUrCy/Y 4zs3LOmrOq0TaWc0A0SC/HWBQP4/W/ELepOd0BDIr8QLgnFNAZ/zkAuXRrP7OgQ3Ep Sk9+U0/pcCa3A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91320C531FC; Fri, 20 Feb 2026 04:07:50 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Thu, 19 Feb 2026 22:07:40 -0600 Subject: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260219-sm8550-ddr-bw-scaling-v3-2-75c19152e921@gmail.com> References: <20260219-sm8550-ddr-bw-scaling-v3-0-75c19152e921@gmail.com> In-Reply-To: <20260219-sm8550-ddr-bw-scaling-v3-0-75c19152e921@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling , Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771560469; l=15161; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=8VtROm9THEXwYG/h6H8x8IE15M3GbTOmPIsXQU8MGbU=; b=lz9mCmf+kp9G6sYtHzt8wauRJ4COixJMcOmjUG3b0l2yR+i1u7hZYnjdOF6BWqII2lh22JGVV ten7fNbIHOED5UPfAhWYyvUg5MwEWolTRMx+Beb8WrN/c5l/z00azQA X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running a QCS8550 device. Also add the OSC L3 Cache controller node. Also add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Tested-by: Neil Armstrong # on SM8550-HDK Reviewed-by: Konrad Dybcio Signed-off-by: Aaron Kling Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0= fc36d25f3c2a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,13 @@ cpu0: cpu@0 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_0: l2-cache { compatible =3D "cache"; @@ -104,6 +112,13 @@ cpu1: cpu@100 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_100: l2-cache { compatible =3D "cache"; @@ -125,6 +140,13 @@ cpu2: cpu@200 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_200: l2-cache { compatible =3D "cache"; @@ -146,6 +168,13 @@ cpu3: cpu@300 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_300: l2-cache { compatible =3D "cache"; @@ -167,6 +196,13 @@ cpu4: cpu@400 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_400: l2-cache { compatible =3D "cache"; @@ -188,6 +224,13 @@ cpu5: cpu@500 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_500: l2-cache { compatible =3D "cache"; @@ -209,6 +252,13 @@ cpu6: cpu@600 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_600: l2-cache { compatible =3D "cache"; @@ -230,6 +280,13 @@ cpu7: cpu@700 { qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; + operating-points-v2 =3D <&cpu7_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_700: l2-cache { compatible =3D "cache"; @@ -397,6 +454,306 @@ memory@a0000000 { reg =3D <0 0xa0000000 0 0>; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-441600000 { + opp-hz =3D /bits/ 64 <441600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz =3D /bits/ 64 <556800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz =3D /bits/ 64 <672000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1056000 * 32)>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1152000 * 32)>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1689600 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-peak-kBps =3D <(600000 * 16) (1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz =3D /bits/ 64 <844800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1920000000 { + opp-hz =3D /bits/ 64 <1920000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2054400000 { + opp-hz =3D /bits/ 64 <2054400000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2323200000 { + opp-hz =3D /bits/ 64 <2323200000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2457600000 { + opp-hz =3D /bits/ 64 <2457600000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + opp-peak-kBps =3D <(933000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2803200000 { + opp-hz =3D /bits/ 64 <2803200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-864000000 { + opp-hz =3D /bits/ 64 <864000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1132800000 { + opp-hz =3D /bits/ 64 <1132800000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1478400000 { + opp-hz =3D /bits/ 64 <1478400000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1593600000 { + opp-hz =3D /bits/ 64 <1593600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1843200000 { + opp-hz =3D /bits/ 64 <1843200000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2092800000 { + opp-hz =3D /bits/ 64 <2092800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2227200000 { + opp-hz =3D /bits/ 64 <2227200000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2342400000 { + opp-hz =3D /bits/ 64 <2342400000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2476800000 { + opp-hz =3D /bits/ 64 <2476800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2726400000 { + opp-hz =3D /bits/ 64 <2726400000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1478400 * 32)>; + }; + + opp-2841600000 { + opp-hz =3D /bits/ 64 <2841600000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2956800000 { + opp-hz =3D /bits/ 64 <2956800000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-3187200000 { + opp-hz =3D /bits/ 64 <3187200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + pmu-a510 { compatible =3D "arm,cortex-a510-pmu"; interrupts =3D ; @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; =20 + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,sm8550-epss-l3", "qcom,epss-l3"; + reg =3D <0 0x17d90000 0 0x1000>; + + clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg =3D <0 0x17d91000 0 0x1000>, --=20 2.52.0