From nobody Fri Apr 3 09:29:01 2026 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C6B33ADA7 for ; Wed, 18 Feb 2026 23:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771456218; cv=none; b=ujEYZJ7qxyjFXe5cY9r8v/SB86cgNG8gUJ3drbjqKOzkAI/pNY7Shkz+Eqtvbf5AhxHmsI8BY0J2fXBpBdaGlWMkNtRIt/QkF/jsp6z/DbrhnS7AKxJLxa+ch02MsdXsYTKktXYCB+WiILDmj36aHiZzXqjio4v+3qSPaBkJ/mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771456218; c=relaxed/simple; bh=NMDuvD7HrMiDW7irrkEtcqX9feVJnOUeWUwcpv6qmIw=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=K01PJuVT0knraUdJD73Of60iskCjgejfw/qwwB7aqOt5MqfFHEGqkFXasSVw8gxpCgw6sU55+xXMl6+tKsATVZd06Wm4yp5YbVOabqBMDOXxOyFeEwg2Z5Rykv1h6IWXOpZLmeHVEf8HgPcdWGJxv+IHzML3TjOSyYOJqbvWF4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=iwMV5LUg; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="iwMV5LUg" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-c6de06e6c08so154715a12.3 for ; Wed, 18 Feb 2026 15:10:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1771456216; x=1772061016; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=LLLEX7R/aRYWwzEE41grxY+H/LHczaoT3FkuhfJMqq4=; b=iwMV5LUgopwy6STRvmLJJ/3+mGb94X2kjz10QcjvZ9ffN9nHnDV3Q7y+/EXo8LHQdO T1uLFMnHuzPEYatDar+qXL8TYbtKkwn4Xrvy2J/+L3ZDDzkuQSjyBNVuN4X1YwLDVDAg Ga3EpKcPlF2i8vkOq5d4XaOpsin/9KyixgXt5zWYbz/pSjefhKreyuA7PsVvW6bSbrdI B2E+Uxw9W0fqPrKesICRlMe61NlgLdD6KCYQR5bxUOI8G7hBYLGF9PjsJbOUVYn0bZnJ QowJX+9sf5N/eMxwxwmGwe1ixQDvZo1jIT77GIz5py09CGjJDNtRM9++nAJpG1MofN/t btNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771456216; x=1772061016; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LLLEX7R/aRYWwzEE41grxY+H/LHczaoT3FkuhfJMqq4=; b=GSaxXyncWcXaemDpXMne7LrM73sv+ExSHD52dxGIp33bTwfCbfh73GeoKFK6m3+ycG IddqE+UaXp8eGx9Mt3PQuNBP2She3mfDL3lD0A1rxOln6OcyEZ7CSXNHPhMakRLZdcLs nFCt9y0evoh0VXVWTBwAyj+JwgcB3iInYSE+q98L2lAuJ/f5/te0ZFqGs6GHIngD/gO3 SGYSmZVXGQ3N9sk6PM/GpvLFeSdwvQQzS3IYRsOL2MFXKbNAaV240IBa19KsrwGcZ5PR 0UTQmbY20IN0ygWYAJj/R5B5apO9nO3Quk9B92wpFpYip2/Mg6/BS3I0hMwxEC3tRSnx tTLg== X-Forwarded-Encrypted: i=1; AJvYcCXYSdP8qXdcVIvIMlclfGLbnsWDs8QWMWnlnPa+5+fwI1VR7GTyokp0HpUMt7K1o+ivSy/7KAfP7MpIfuE=@vger.kernel.org X-Gm-Message-State: AOJu0Yyl/fY7mUl1CQbeVmJq2YmTD8RhN7ft7vov//x5achRHR6K7hmK LVk8hZ9Rwo0FEaCp7gDRHVEtLDojTs3TC01dmd3QaGF19FJisWQcBca9YL25bg2Lq3bUEiG0B7h PAgiv7g== X-Received: from plw19.prod.google.com ([2002:a17:903:45d3:b0:2a7:6eb5:7e30]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:910:b0:2a9:4450:abb7 with SMTP id d9443c01a7336-2ad50f6378fmr28512385ad.39.1771456215835; Wed, 18 Feb 2026 15:10:15 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 18 Feb 2026 15:09:58 -0800 In-Reply-To: <20260218230958.2877682-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260218230958.2877682-1-seanjc@google.com> X-Mailer: git-send-email 2.53.0.345.g96ddfc5eaa-goog Message-ID: <20260218230958.2877682-9-seanjc@google.com> Subject: [PATCH v2 8/8] KVM: nSVM: Capture svm->nested.ctl as vmcb12_ctrl when preparing vmcb02 From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Yosry Ahmed Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Grab svm->nested.ctl as vmcb12_ctrl when preparing the vmcb02 controls to make it more obvious that much of the data is coming from vmcb12 (or rather, a snapshot of vmcb12 at the time of L1's VMRUN). Opportunistically reorder the variable definitions to create a pretty reverse fir tree. No functional change intended. Cc: Yosry Ahmed Signed-off-by: Sean Christopherson Reviewed-by: Yosry Ahmed --- arch/x86/kvm/svm/nested.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index bcd6304f3c0c..1814522db6b4 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -745,11 +745,11 @@ static void nested_vmcb02_prepare_control(struct vcpu= _svm *svm, u32 int_ctl_vmcb01_bits =3D V_INTR_MASKING_MASK; u32 int_ctl_vmcb12_bits =3D V_TPR_MASK | V_IRQ_INJECTION_BITS_MASK; =20 - struct kvm_vcpu *vcpu =3D &svm->vcpu; - struct vmcb *vmcb01 =3D svm->vmcb01.ptr; + struct vmcb_ctrl_area_cached *vmcb12_ctrl =3D &svm->nested.ctl; struct vmcb *vmcb02 =3D svm->nested.vmcb02.ptr; - u32 pause_count12; - u32 pause_thresh12; + struct vmcb *vmcb01 =3D svm->vmcb01.ptr; + struct kvm_vcpu *vcpu =3D &svm->vcpu; + u32 pause_count12, pause_thresh12; =20 nested_svm_transition_tlb_flush(vcpu); =20 @@ -762,7 +762,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm, */ =20 if (guest_cpu_cap_has(vcpu, X86_FEATURE_VGIF) && - (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK)) + (vmcb12_ctrl->int_ctl & V_GIF_ENABLE_MASK)) int_ctl_vmcb12_bits |=3D (V_GIF_MASK | V_GIF_ENABLE_MASK); else int_ctl_vmcb01_bits |=3D (V_GIF_MASK | V_GIF_ENABLE_MASK); @@ -820,10 +820,9 @@ static void nested_vmcb02_prepare_control(struct vcpu_= svm *svm, if (nested_npt_enabled(svm)) nested_svm_init_mmu_context(vcpu); =20 - vcpu->arch.tsc_offset =3D kvm_calc_nested_tsc_offset( - vcpu->arch.l1_tsc_offset, - svm->nested.ctl.tsc_offset, - svm->tsc_ratio_msr); + vcpu->arch.tsc_offset =3D kvm_calc_nested_tsc_offset(vcpu->arch.l1_tsc_of= fset, + vmcb12_ctrl->tsc_offset, + svm->tsc_ratio_msr); =20 vmcb02->control.tsc_offset =3D vcpu->arch.tsc_offset; =20 @@ -832,13 +831,13 @@ static void nested_vmcb02_prepare_control(struct vcpu= _svm *svm, nested_svm_update_tsc_ratio_msr(vcpu); =20 vmcb02->control.int_ctl =3D - (svm->nested.ctl.int_ctl & int_ctl_vmcb12_bits) | + (vmcb12_ctrl->int_ctl & int_ctl_vmcb12_bits) | (vmcb01->control.int_ctl & int_ctl_vmcb01_bits); =20 - vmcb02->control.int_vector =3D svm->nested.ctl.int_vector; - vmcb02->control.int_state =3D svm->nested.ctl.int_state; - vmcb02->control.event_inj =3D svm->nested.ctl.event_inj; - vmcb02->control.event_inj_err =3D svm->nested.ctl.event_inj_err; + vmcb02->control.int_vector =3D vmcb12_ctrl->int_vector; + vmcb02->control.int_state =3D vmcb12_ctrl->int_state; + vmcb02->control.event_inj =3D vmcb12_ctrl->event_inj; + vmcb02->control.event_inj_err =3D vmcb12_ctrl->event_inj_err; =20 /* * next_rip is consumed on VMRUN as the return address pushed on the @@ -849,7 +848,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm, * prior to injecting the event). */ if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS)) - vmcb02->control.next_rip =3D svm->nested.ctl.next_rip; + vmcb02->control.next_rip =3D vmcb12_ctrl->next_rip; else if (boot_cpu_has(X86_FEATURE_NRIPS)) vmcb02->control.next_rip =3D vmcb12_rip; =20 @@ -859,7 +858,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm, svm->soft_int_csbase =3D vmcb12_csbase; svm->soft_int_old_rip =3D vmcb12_rip; if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS)) - svm->soft_int_next_rip =3D svm->nested.ctl.next_rip; + svm->soft_int_next_rip =3D vmcb12_ctrl->next_rip; else svm->soft_int_next_rip =3D vmcb12_rip; } @@ -870,11 +869,11 @@ static void nested_vmcb02_prepare_control(struct vcpu= _svm *svm, vmcb02->control.virt_ext |=3D VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; =20 if (guest_cpu_cap_has(vcpu, X86_FEATURE_PAUSEFILTER)) - pause_count12 =3D svm->nested.ctl.pause_filter_count; + pause_count12 =3D vmcb12_ctrl->pause_filter_count; else pause_count12 =3D 0; if (guest_cpu_cap_has(vcpu, X86_FEATURE_PFTHRESHOLD)) - pause_thresh12 =3D svm->nested.ctl.pause_filter_thresh; + pause_thresh12 =3D vmcb12_ctrl->pause_filter_thresh; else pause_thresh12 =3D 0; if (kvm_pause_in_guest(svm->vcpu.kvm)) { @@ -888,7 +887,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm, vmcb02->control.pause_filter_thresh =3D vmcb01->control.pause_filter_thr= esh; =20 /* ... but ensure filtering is disabled if so requested. */ - if (vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_PAUSE)) { + if (vmcb12_is_intercept(vmcb12_ctrl, INTERCEPT_PAUSE)) { if (!pause_count12) vmcb02->control.pause_filter_count =3D 0; if (!pause_thresh12) @@ -905,7 +904,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm, * L2 is the "guest"). */ if (guest_cpu_cap_has(vcpu, X86_FEATURE_ERAPS)) - vmcb02->control.erap_ctl =3D (svm->nested.ctl.erap_ctl & + vmcb02->control.erap_ctl =3D (vmcb12_ctrl->erap_ctl & ERAP_CONTROL_ALLOW_LARGER_RAP) | ERAP_CONTROL_CLEAR_RAP; =20 --=20 2.53.0.345.g96ddfc5eaa-goog