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Wed, 18 Feb 2026 14:23:44 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties Date: Wed, 18 Feb 2026 14:23:35 +0100 Message-ID: <20260218132339.32157-3-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260218132339.32157-1-Max.Merchel@ew.tq-group.com> References: <20260218132339.32157-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay48-hz3.antispameurope.com with 4fGHJw6VYjz1kPGCB X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 24d8cc4ecc148cb0df8ddce9d33b9577 X-cloud-security: scantime:1.977 DKIM-Signature: a=rsa-sha256; bh=RDEB7Al8C9dMaYAoYH02KGoF+Zms3cmMuP6jo0DNw98=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771421041; v=1; b=Ou1pPpnnimxUTIx52eZaVDn4XmsVuJe7cvnvahHhMOwwfNqActNVSRr+UgOWlP8JXzHe6olZ NUB4/Upx9g8hwfWyvFBmvHbe7n3osmN3/tg21GKH+s+9z2Y3u7UYhdZCsPivi5w3CIJFsVXMJMa CBFIw2KRI2Phn8n/X0kMb+Iju+D4XQZVIIesR5oS0wofDDerUmkVf75XvC1SexmPeEtIYaC1z6P 6rhb0RzY1RfwzPI+A09HAjCrOFIx9Sq8BhkrXc/d3jPm+xJo0kor3AcEPAaK1Zo6wBluG+G4QOf 7hbHnqu+yo6zrg6Q6QBT9ISx+7DlxvbORFh/j/VpQEK0w== Content-Type: text/plain; charset="utf-8" Add boot phase properties for TQMa6UL[L] device tree. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi | 10 ++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi | 1 + 7 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi index 2dd635a615cb..4fa98e6a66d7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -26,6 +26,7 @@ &i2c4 { pinctrl-1 =3D <&pinctrl_i2c4_recovery>; scl-gpios =3D <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + bootph-pre-ram; status =3D "okay"; =20 pfuze3000: pmic@8 { @@ -140,9 +141,14 @@ rtc0: rtc@68 { }; }; =20 +&gpio1 { + bootph-pre-ram; +}; + &gpio4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pmic>; + bootph-pre-ram; =20 /* * PMIC & temperature sensor IRQ @@ -159,6 +165,7 @@ pmic-int-hog { &qspi { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_qspi>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -168,6 +175,7 @@ flash0: flash@0 { spi-rx-bus-width =3D <4>; spi-tx-bus-width =3D <1>; vcc-supply =3D <®_vldo4>; + bootph-pre-ram; =20 partitions { compatible =3D "fixed-partitions"; @@ -189,6 +197,7 @@ &usdhc2 { non-removable; no-sdio; no-sd; + bootph-all; status =3D "okay"; }; =20 @@ -212,5 +221,6 @@ pinctrl_pmic: pmicgrp { /* PMIC irq */ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi b/arch/arm/boot= /dts/nxp/imx/imx6ul-tqma6ul2.dtsi index e2e95dd92263..f81cd09fe0c7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi @@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi b/arch/arm/boo= t/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi index 4b87e2dc70dc..11c8f1af4173 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi @@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi b/arch/a= rm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi index 5afb9046c202..5c90d0a3ee2e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi @@ -39,5 +39,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi b/arch/= arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi index ba84a4f70ebd..133961ee7283 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi @@ -44,5 +44,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi b/arch/arm/bo= ot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi index 8541cb3f3b3e..1224ef132439 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi @@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi b/arch/arm/b= oot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi index be593d47e3b1..6dd1b359e086 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi @@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { --=20 2.43.0