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Wed, 18 Feb 2026 14:23:43 +0100 (CET) From: Max Merchel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Max Merchel , linux@ew.tq-group.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] ARM: dts: imx6ul/imx6ull: add boot phase properties Date: Wed, 18 Feb 2026 14:23:34 +0100 Message-ID: <20260218132339.32157-2-Max.Merchel@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260218132339.32157-1-Max.Merchel@ew.tq-group.com> References: <20260218132339.32157-1-Max.Merchel@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: max.merchel@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: max.merchel@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay39-hz1.antispameurope.com with 4fGHJw1fnTz18J6L X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 965d9ae517c88a7aee3ccb289887b696 X-cloud-security: scantime:2.251 DKIM-Signature: a=rsa-sha256; bh=mhpAHeK5WnP5K7fPONIfRy2XkHtMpwUTgs7kyE7vMb0=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1771421041; v=1; b=ACaJIYGPAx2VaX9RErRyBe8gO5jaBRwX6y4fDQMro6OFVnhaJ2VrV1HUyc4WTrcF2ELqkg5K IHMnxvaKnakZQGAufZs1iz1M+EvXCzEiAE6Yg647+zAehc/YVooMieOjCO7HToFTHOnlj56ar9v uUbngIKQGqKk1nLECxZVv8EBi58RS2ObVbhrIPVoxAYDCjAQeNNcwLZdBxgkLQTe2JacDB20iOA ufPWYtidWbv56PNVE7gS4br9LIulLCDUnikeNwyBIe2hcvoiAyJZiuKgWJ0S76iL8fMJSuYp2dJ CcU4/2+Sn3Be49Cuz3/qkGlYjaLG9iSgGE6VHWCwRvFEg== Content-Type: text/plain; charset="utf-8" Add boot phase properties from U-Boot device tree. Signed-off-by: Max Merchel --- arch/arm/boot/dts/nxp/imx/imx6ul.dtsi | 6 ++++++ arch/arm/boot/dts/nxp/imx/imx6ull.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/= imx/imx6ul.dtsi index 6eb80f867f50..c745f30a9b25 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -115,6 +115,7 @@ osc: clock-osc { #clock-cells =3D <0>; clock-frequency =3D <24000000>; clock-output-names =3D "osc"; + bootph-pre-ram; }; =20 ipp_di0: clock-di0 { @@ -143,6 +144,7 @@ soc: soc { compatible =3D "simple-bus"; interrupt-parent =3D <&gpc>; ranges; + bootph-pre-ram; =20 ocram: sram@900000 { compatible =3D "mmio-sram"; @@ -202,6 +204,7 @@ aips1: bus@2000000 { #size-cells =3D <1>; reg =3D <0x02000000 0x100000>; ranges; + bootph-pre-ram; =20 spba-bus@2000000 { compatible =3D "fsl,spba-bus", "simple-bus"; @@ -580,6 +583,7 @@ clks: clock-controller@20c4000 { #clock-cells =3D <1>; clocks =3D <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; clock-names =3D "ckil", "osc", "ipp_di0", "ipp_di1"; + bootph-pre-ram; }; =20 anatop: anatop@20c8000 { @@ -745,6 +749,7 @@ power-domain@0 { iomuxc: pinctrl@20e0000 { compatible =3D "fsl,imx6ul-iomuxc"; reg =3D <0x020e0000 0x4000>; + bootph-pre-ram; }; =20 gpr: iomuxc-gpr@20e4000 { @@ -826,6 +831,7 @@ aips2: bus@2100000 { #size-cells =3D <1>; reg =3D <0x02100000 0x100000>; ranges; + bootph-pre-ram; =20 crypto: crypto@2140000 { compatible =3D "fsl,imx6ul-caam", "fsl,sec-v4.0"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi b/arch/arm/boot/dts/nxp= /imx/imx6ull.dtsi index db0c339022ac..ba0ea10c7b74 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi @@ -57,6 +57,7 @@ aips3: bus@2200000 { #size-cells =3D <1>; reg =3D <0x02200000 0x100000>; ranges; + bootph-pre-ram; =20 dcp: crypto@2280000 { compatible =3D "fsl,imx6ull-dcp", "fsl,imx28-dcp"; --=20 2.43.0