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charset="utf-8" New binding document for Texas Instruments K3 Block Copy DMA (BCDMA) V2. BCDMA V2 is introduced as part of AM62L. Signed-off-by: Sai Sree Kartheek Adivi --- .../bindings/dma/ti/ti,am62l-dmss-bcdma.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-= bcdma.yaml diff --git a/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.y= aml b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml new file mode 100644 index 0000000000000..6fa08f22df375 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-25 Texas Instruments Incorporated +# Author: Sai Sree Kartheek Adivi +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/ti,am62l-dmss-bcdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 DMSS BCDMA V2 + +maintainers: + - Sai Sree Kartheek Adivi + +description: + The BCDMA V2 is intended to perform similar functions as the TR + mode channels of K3 UDMA-P. + BCDMA V2 includes block copy channels and Split channels. + + Block copy channels mainly used for memory to memory transfers, but with + optional triggers a block copy channel can service peripherals by access= ing + directly to memory mapped registers or area. + + Split channels can be used to service PSI-L based peripherals. + The peripherals can be PSI-L native or legacy, non PSI-L native peripher= als + with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric a= nd the + legacy peripheral. + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: ti,am62l-dmss-bcdma + + reg: + items: + - description: BCDMA Control & Status Registers region + - description: Block Copy Channel Realtime Registers region + - description: Channel Realtime Registers region + - description: Ring Realtime Registers region + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: chanrt + - const: ringrt + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + "#dma-cells": + const: 4 + description: | + cell 1: Trigger type for the channel + 0 - disable / no trigger + 1 - internal channel event + 2 - external signal + 3 - timer manager event + + cell 2: parameter for the trigger: + if cell 1 is 0 (disable / no trigger): + Unused, ignored + if cell 1 is 1 (internal channel event): + channel number whose TR event should trigger the current channel. + if cell 1 is 2 or 3 (external signal or timer manager event): + index of global interfaces that come into the DMA. + + Please refer to the device documentation for global interface in= dexes. + + cell 3: Channel number for the peripheral + + Please refer to the device documentation for the channel map. + + cell 4: ASEL value for the channel + + interrupt-map-mask: + items: + - const: 0x7ff + + interrupt-map: + description: | + Maps internal BCDMA channel IDs to the parent GIC IRQ lines. + +required: + - compatible + - reg + - reg-names + - "#address-cells" + - "#interrupt-cells" + - "#dma-cells" + - interrupt-map-mask + - interrupt-map + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dma-controller@485c4000 { + compatible =3D "ti,am62l-dmss-bcdma"; + reg =3D <0x485c4000 0x4000>, + <0x48880000 0x10000>, + <0x48800000 0x80000>, + <0x47000000 0x200000>; + reg-names =3D "gcfg", "bchanrt", "chanrt", "ringrt"; + + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + #dma-cells =3D <4>; + + interrupt-map-mask =3D <0x7ff>; + interrupt-map =3D <49 &gic500 0 0 GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <50 &gic500 0 0 GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; + }; --=20 2.34.1