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charset="utf-8" Handle absence of tisci with direct register writes. This will support platforms that do not have tisci firmware like AM62L. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/soc/ti/k3-ringacc.c | 188 ++++++++++++++++++++++++++---- include/linux/soc/ti/k3-ringacc.h | 17 +++ 2 files changed, 181 insertions(+), 24 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 7602b8a909b05..fd7c960a3fa2a 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -45,6 +45,53 @@ struct k3_ring_rt_regs { u32 hwindx; }; =20 +#define K3_RINGACC_RT_CFG_REGS_OFS 0x40 +#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0) +#define K3_DMARING_CFG_ASEL_SHIFT 16 +#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0) + +/** + * struct k3_ring_cfg_regs - The RA Configuration Registers region + * + * @ba_lo: Ring Base Address Low Register + * @ba_hi: Ring Base Address High Register + * @size: Ring Size Register + */ +struct k3_ring_cfg_regs { + u32 ba_lo; + u32 ba_hi; + u32 size; +}; + +#define K3_RINGACC_RT_INT_REGS_OFS 0x140 +#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0) +#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2) + +/** + * struct k3_ring_intr_regs { + * + * @enable_set: Ring Interrupt Enable Register + * @resv_1: Reserved + * @clr: Ring Interrupt Clear Register + * @resv_2: Reserved + * @status_set: Ring Interrupt Status Set Register + * @resv_3: Reserved + * @status: Ring Interrupt Status Register + * @resv_4: Reserved + * @status_masked: Ring Interrupt Status Masked Register + */ +struct k3_ring_intr_regs { + u32 enable_set; + u32 resv_1; + u32 clr; + u32 resv_2; + u32 status_set; + u32 resv_3; + u32 status; + u32 resv_4; + u32 status_masked; +}; + #define K3_RINGACC_RT_REGS_STEP 0x1000 #define K3_DMARING_RT_REGS_STEP 0x2000 #define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000 @@ -138,6 +185,8 @@ struct k3_ring_state { * struct k3_ring - RA Ring descriptor * * @rt: Ring control/status registers + * @cfg: Ring config registers + * @intr: Ring interrupt registers * @fifos: Ring queues registers * @proxy: Ring Proxy Datapath registers * @ring_mem_dma: Ring buffer dma address @@ -157,6 +206,8 @@ struct k3_ring_state { */ struct k3_ring { struct k3_ring_rt_regs __iomem *rt; + struct k3_ring_cfg_regs __iomem *cfg; + struct k3_ring_intr_regs __iomem *intr; struct k3_ring_fifo_regs __iomem *fifos; struct k3_ringacc_proxy_target_regs __iomem *proxy; dma_addr_t ring_mem_dma; @@ -466,15 +517,31 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring = *ring) struct k3_ringacc *ringacc =3D ring->parent; int ret; =20 - ring_cfg.nav_id =3D ringacc->tisci_dev_id; - ring_cfg.index =3D ring->ring_id; - ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; - ring_cfg.count =3D ring->size; + if (!ringacc->tisci) { + u32 reg; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ring->cfg) + return; + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + writel(reg, &ring->cfg->size); + + /* Ensure the register clear operation completes before writing new valu= e */ + wmb(); + reg |=3D ring->size; + writel(reg, &ring->cfg->size); + } else { + ring_cfg.nav_id =3D ringacc->tisci_dev_id; + ring_cfg.index =3D ring->ring_id; + ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; + ring_cfg.count =3D ring->size; + + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset(struct k3_ring *ring) @@ -500,10 +567,25 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct= k3_ring *ring, ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_MODE_VALID; ring_cfg.mode =3D mode; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ) @@ -575,10 +657,25 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *= ring) ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 int k3_ringacc_ring_free(struct k3_ring *ring) @@ -669,15 +766,30 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring) } EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num); =20 +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *ring2 =3D &ringacc->rings[ring->ring_id]; + + return readl(&ring2->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status); + +void k3_ringacc_ring_clear_irq(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *ring2 =3D &ringacc->rings[ring->ring_id]; + + writel(0xFF, &ring2->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq); + static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring) { struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; int ret; =20 - if (!ringacc->tisci) - return -EINVAL; - ring_cfg.nav_id =3D ringacc->tisci_dev_id; ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; @@ -688,6 +800,24 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *rin= g) ring_cfg.size =3D ring->elm_size; ring_cfg.asel =3D ring->asel; =20 + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_= SET_TR, + &ring->intr->enable_set); + return 0; + } + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", @@ -1346,8 +1476,11 @@ static int k3_ringacc_probe_dt(struct k3_ringacc *ri= ngacc) return PTR_ERR(ringacc->rm_gp_range); } =20 - return ti_sci_inta_msi_domain_alloc_irqs(ringacc->dev, - ringacc->rm_gp_range); + if (IS_ENABLED(CONFIG_TI_K3_UDMA)) + return ti_sci_inta_msi_domain_alloc_irqs(ringacc->dev, + ringacc->rm_gp_range); + else + return 0; } =20 static const struct k3_ringacc_soc_data k3_ringacc_soc_data_sr1 =3D { @@ -1480,9 +1613,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, =20 mutex_init(&ringacc->req_lock); =20 - base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); - if (IS_ERR(base_rt)) - return ERR_CAST(base_rt); + base_rt =3D data->base_rt; + if (!base_rt) { + base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); + if (IS_ERR(base_rt)) + return ERR_CAST(base_rt); + } =20 ringacc->rings =3D devm_kzalloc(dev, sizeof(*ringacc->rings) * @@ -1498,6 +1634,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, struct k3_ring *ring =3D &ringacc->rings[i]; =20 ring->rt =3D base_rt + K3_DMARING_RT_REGS_STEP * i; + ring->cfg =3D base_rt + K3_RINGACC_RT_CFG_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; + ring->intr =3D base_rt + K3_RINGACC_RT_INT_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; ring->parent =3D ringacc; ring->ring_id =3D i; ring->proxy_id =3D K3_RINGACC_PROXY_NOT_USED; diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 39b022b925986..9f2d141c988bd 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -158,6 +158,22 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring); */ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring); =20 +/** + * k3_ringacc_ring_get_irq_status - Get the irq status for the ring + * @ring: pointer on ring + * + * Returns the interrupt status + */ +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring); + +/** + * k3_ringacc_ring_clear_irq - Clear all interrupts + * @ring: pointer on ring + * + * Clears all the interrupts on the ring + */ +void k3_ringacc_ring_clear_irq(struct k3_ring *ring); + /** * k3_ringacc_ring_cfg - ring configure * @ring: pointer on ring @@ -262,6 +278,7 @@ struct k3_ringacc_init_data { const struct ti_sci_handle *tisci; u32 tisci_dev_id; u32 num_rings; + void __iomem *base_rt; }; =20 struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, --=20 2.34.1