From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8997314A62 for ; Wed, 18 Feb 2026 08:21:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402905; cv=none; b=EmSgc41Lp+I6FNPEjMFDxtYUXG1ChzkBUvR54df2yP4gEVooxhzpIX7mPAI6JD9QZYsUi7NZ92U5CGy3dbiudK55NuPQ1TRnRQxXdnrw+8ARytpD+bRf3XgohxIxj33KZNtRnfCtLFOZFMYr/1IAA55twM8JA/EcTUmx+YcR4Aw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402905; c=relaxed/simple; bh=xLsOnGu4DxeyAKhwjQJIuMFziEHsNA1NJifo2KMfBKk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bJz8R4KKYZSGy3XS/RTV5OqxTLBe8zE7hBJseE+i4Y3yZ3vfSpVFsAmjYyqIn3ipOqnyHRs5sBNIngW1pcZHXtMIzDndLMmBZ6W4STNGJkYTfDZgQyuEZcMxQqe31bfVciFC2oqGHoapgCMP/7xScFfc/WhM6/7+Nu7yrQdx0LU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id D9FD23E6E8; Wed, 18 Feb 2026 08:21:41 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 9B1FA3EA65; Wed, 18 Feb 2026 08:21:41 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id F4KLJJV2lWlqHQAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:21:41 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v3 01/16] x86/alternative: Support alt_replace_call() with instructions after call Date: Wed, 18 Feb 2026 09:21:18 +0100 Message-ID: <20260218082133.400602-2-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: D9FD23E6E8 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Today alt_replace_call() requires the initial indirect call not to be followed by any further instructions, including padding NOPs. In case any replacement is longer than 6 bytes, a subsequent replacement of the indirect call with a direct one will result in a crash. Fix that by crashing only if the original instruction is less than 6 bytes long or not a known indirect call. Signed-off-by: Juergen Gross --- V3: - new patch arch/x86/kernel/alternative.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 693b59b2f7d0..6d37672ba71f 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -534,6 +534,7 @@ noinstr void BUG_func(void) } EXPORT_SYMBOL(BUG_func); =20 +#define CALL_RIP_INSTRLEN 6 #define CALL_RIP_REL_OPCODE 0xff #define CALL_RIP_REL_MODRM 0x15 =20 @@ -551,7 +552,7 @@ static unsigned int alt_replace_call(u8 *instr, u8 *ins= n_buff, struct alt_instr BUG(); } =20 - if (a->instrlen !=3D 6 || + if (a->instrlen < CALL_RIP_INSTRLEN || instr[0] !=3D CALL_RIP_REL_OPCODE || instr[1] !=3D CALL_RIP_REL_MODRM) { pr_err("ALT_FLAG_DIRECT_CALL set for unrecognized indirect call\n"); @@ -563,7 +564,7 @@ static unsigned int alt_replace_call(u8 *instr, u8 *ins= n_buff, struct alt_instr #ifdef CONFIG_X86_64 /* ff 15 00 00 00 00 call *0x0(%rip) */ /* target address is stored at "next instruction + disp". */ - target =3D *(void **)(instr + a->instrlen + disp); + target =3D *(void **)(instr + CALL_RIP_INSTRLEN + disp); #else /* ff 15 00 00 00 00 call *0x0 */ /* target address is stored at disp. */ --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C69C3318B8A for ; Wed, 18 Feb 2026 08:21:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402911; cv=none; b=XuWmzfWqavPvjl9o0/jFSI1IvmIUhx20rP3EVhnCvX7zCPEd7zTXj9WPotjAubKevawk4pMWmyeQECcxGq5PbuC/iAZFWNPrtUNN7jcGKFf9M/Z4bCt6NXsnD3WGL43VVMX4U5yFvCWwSEbnNTOw8jaZY3jWdTPADSMN7/B/aL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402911; c=relaxed/simple; bh=jRfDVvtqJRuhkX75Z2GAn0Ti70bQQUP9txusTHgieIg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H+8gcUF+DQFbAwM0lGFMkcjf/B27k/XwuvbxlHb2xqQWyj7OK/XK3MfXJJUgP+Pxz5KAxu9DHNw7o1dIKftDZUI7geFGYTl5886SLVlgJrHAtY8725vQoMFkVNGl50n3PsqUKKHR5RuPX8LIgQ+gpejv32cWAUgvvQu5gi1b7xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 756EF3E6E9; Wed, 18 Feb 2026 08:21:47 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 251323EA65; Wed, 18 Feb 2026 08:21:47 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 3y3mB5t2lWnxHQAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:21:47 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe Subject: [PATCH v3 02/16] coco/tdx: Rename MSR access helpers Date: Wed, 18 Feb 2026 09:21:19 +0100 Message-ID: <20260218082133.400602-3-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 756EF3E6E9 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Content-Type: text/plain; charset="utf-8" In order to avoid a name clash with some general MSR access helpers after a future MSR infrastructure rework, rename the TDX specific helpers. Signed-off-by: Juergen Gross Reviewed-by: Kiryl Shutsemau Reviewed-by: H. Peter Anvin (Intel) Reviewed-by: Rick Edgecombe --- arch/x86/coco/tdx/tdx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 7b2833705d47..500166c1a161 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -468,7 +468,7 @@ static void __cpuidle tdx_safe_halt(void) raw_local_irq_enable(); } =20 -static int read_msr(struct pt_regs *regs, struct ve_info *ve) +static int tdx_read_msr(struct pt_regs *regs, struct ve_info *ve) { struct tdx_module_args args =3D { .r10 =3D TDX_HYPERCALL_STANDARD, @@ -489,7 +489,7 @@ static int read_msr(struct pt_regs *regs, struct ve_inf= o *ve) return ve_instr_len(ve); } =20 -static int write_msr(struct pt_regs *regs, struct ve_info *ve) +static int tdx_write_msr(struct pt_regs *regs, struct ve_info *ve) { struct tdx_module_args args =3D { .r10 =3D TDX_HYPERCALL_STANDARD, @@ -842,9 +842,9 @@ static int virt_exception_kernel(struct pt_regs *regs, = struct ve_info *ve) case EXIT_REASON_HLT: return handle_halt(ve); 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Peter Anvin" , Nikunj A Dadhania Subject: [PATCH v3 03/16] x86/sev: Replace call of native_wrmsr() with native_wrmsrq() Date: Wed, 18 Feb 2026 09:21:20 +0100 Message-ID: <20260218082133.400602-4-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[9]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" In sev_es_wr_ghcb_msr() the 64 bit MSR value is split into 2 32 bit values in order to call native_wrmsr(), which will combine the values into a 64 bit value again. Just use native_wrmsrq() instead. Signed-off-by: Juergen Gross Reviewed-by: Nikunj A Dadhania Reviewed-by: H. Peter Anvin (Intel) --- V2: - new patch --- arch/x86/coco/sev/internal.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/coco/sev/internal.h b/arch/x86/coco/sev/internal.h index b1d0c66a651a..7b76d779a722 100644 --- a/arch/x86/coco/sev/internal.h +++ b/arch/x86/coco/sev/internal.h @@ -77,12 +77,7 @@ static inline u64 sev_es_rd_ghcb_msr(void) =20 static __always_inline void sev_es_wr_ghcb_msr(u64 val) { - u32 low, high; - - low =3D (u32)(val); - high =3D (u32)(val >> 32); - - native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high); + native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val); } =20 enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt,= bool write); --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3259B318EDD for ; Wed, 18 Feb 2026 08:22:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402921; cv=none; b=kjEnQ/nAKfXUeRv+vGZ9pM3ptcN3N/RQlE1xZiK6SP4SI6DY1xmWn4BYtB9Ok5zY8pqEdjdrxFIzx4LQXiFgKXMEgpcrMxGl8Z2zHClVJnFXyFIzzk2xf9/Vyt7qBF1DqylQ2l9ZALKAiUIoZOJPFWb0WXvUmUS0TPLTVv7tqj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402921; c=relaxed/simple; bh=TH3DH5sZ3YyRQn+6E5BlnD/gSVwnhrm79PHvlpsEKiQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mUsSTOwIT2iJyttUiuV6r37/1ggrfr/Y9vAHZMO2cGhf9L9s2qYtmotFhyYTH4SA0OzXSKcs3v7r/hiYSneQaFeWLfSp1T3+Wfs5lPrcqXGTe7mPjZplTqdD6khyaIO1hL7Uh15/ClMv9nbg5AtenmC5jPCAAZaF//cAZ36JBJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=LxzG3ESO; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=LxzG3ESO; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="LxzG3ESO"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="LxzG3ESO" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 9597F5BCCC; Wed, 18 Feb 2026 08:21:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1771402918; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pu+C5dLQu/zzPEFzF00OQIZX29gA4v0cXo/52IprP4w=; b=LxzG3ESOgat3VqxxKOzEShuCAKqlv1ZCdstEbXVdOTndy+wHsGw1C+YomfAUSFl4B3byGH k0q4zkkQr3q93tR7l1c4SetJEJu1grJKgfLaSStRRFZlIrLrJ1IEyLMduNRZ5+ivsX6zMP NH15wDHHoQQQc0kXodAZPya6VeWS7AI= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1771402918; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pu+C5dLQu/zzPEFzF00OQIZX29gA4v0cXo/52IprP4w=; b=LxzG3ESOgat3VqxxKOzEShuCAKqlv1ZCdstEbXVdOTndy+wHsGw1C+YomfAUSFl4B3byGH k0q4zkkQr3q93tR7l1c4SetJEJu1grJKgfLaSStRRFZlIrLrJ1IEyLMduNRZ5+ivsX6zMP NH15wDHHoQQQc0kXodAZPya6VeWS7AI= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 3CE2B3EA65; Wed, 18 Feb 2026 08:21:58 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id EKTVDaZ2lWldHgAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:21:58 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org, linux-coco@lists.linux.dev Cc: Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe Subject: [PATCH v3 04/16] KVM: x86: Remove the KVM private read_msr() function Date: Wed, 18 Feb 2026 09:21:21 +0100 Message-ID: <20260218082133.400602-5-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[14]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" Instead of having a KVM private read_msr() function, just use rdmsrq(). Signed-off-by: Juergen Gross Reviewed-by: H. Peter Anvin (Intel) Acked-by: Sean Christopherson Reviewed-by: Rick Edgecombe --- V2: - remove the helper and use rdmsrq() directly (Sean Christopherson) --- arch/x86/include/asm/kvm_host.h | 10 ---------- arch/x86/kvm/vmx/tdx.c | 2 +- arch/x86/kvm/vmx/vmx.c | 6 +++--- 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index ff07c45e3c73..9034222a96e8 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2347,16 +2347,6 @@ static inline void kvm_load_ldt(u16 sel) asm("lldt %0" : : "rm"(sel)); } =20 -#ifdef CONFIG_X86_64 -static inline unsigned long read_msr(unsigned long msr) -{ - u64 value; - - rdmsrq(msr, value); - return value; -} -#endif - static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) { kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 5df9d32d2058..d9e371e39853 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -801,7 +801,7 @@ void tdx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) if (likely(is_64bit_mm(current->mm))) vt->msr_host_kernel_gs_base =3D current->thread.gsbase; else - vt->msr_host_kernel_gs_base =3D read_msr(MSR_KERNEL_GS_BASE); + rdmsrq(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base); =20 vt->guest_state_loaded =3D true; =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 967b58a8ab9d..3799cbbb4577 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1403,8 +1403,8 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcp= u) } else { savesegment(fs, fs_sel); savesegment(gs, gs_sel); - fs_base =3D read_msr(MSR_FS_BASE); - vt->msr_host_kernel_gs_base =3D read_msr(MSR_KERNEL_GS_BASE); + rdmsrq(MSR_FS_BASE, fs_base); + rdmsrq(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base); } =20 wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); @@ -1463,7 +1463,7 @@ static u64 vmx_read_guest_host_msr(struct vcpu_vmx *v= mx, u32 msr, u64 *cache) { preempt_disable(); if (vmx->vt.guest_state_loaded) - *cache =3D read_msr(msr); + rdmsrq(msr, *cache); preempt_enable(); return *cache; } --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Sean Christopherson , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v3 05/16] x86/msr: Minimize usage of native_*() msr access functions Date: Wed, 18 Feb 2026 09:21:22 +0100 Message-ID: <20260218082133.400602-6-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[20]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; URIBL_BLOCKED(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email,zytor.com:email]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spam-Level: X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1771402942379154100 Content-Type: text/plain; charset="utf-8" In order to prepare for some MSR access function reorg work, switch most users of native_{read|write}_msr[_safe]() to the more generic rdmsr*()/wrmsr*() variants. For now this will have some intermediate performance impact with paravirtualization configured when running on bare metal, but this is a prereq change for the planned direct inlining of the rdmsr/wrmsr instructions with this configuration. The main reason for this switch is the planned move of the MSR trace function invocation from the native_*() functions to the generic rdmsr*()/wrmsr*() variants. Without this switch the users of the native_*() functions would lose the related tracing entries. Note that the Xen related MSR access functions will not be switched, as these will be handled after the move of the trace hooks. Signed-off-by: Juergen Gross Acked-by: Sean Christopherson Acked-by: Wei Liu Reviewed-by: H. Peter Anvin (Intel) --- arch/x86/hyperv/ivm.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 7 +++++-- arch/x86/kernel/kvmclock.c | 2 +- arch/x86/kvm/svm/svm.c | 16 ++++++++-------- arch/x86/xen/pmu.c | 4 ++-- 5 files changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 651771534cae..1b2222036a0b 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -327,7 +327,7 @@ int hv_snp_boot_ap(u32 apic_id, unsigned long start_ip,= unsigned int cpu) asm volatile("movl %%ds, %%eax;" : "=3Da" (vmsa->ds.selector)); hv_populate_vmcb_seg(vmsa->ds, vmsa->gdtr.base); =20 - vmsa->efer =3D native_read_msr(MSR_EFER); + rdmsrq(MSR_EFER, vmsa->efer); =20 vmsa->cr4 =3D native_read_cr4(); vmsa->cr3 =3D __native_read_cr3(); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 579fb2c64cfd..9bebb1a1ebee 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -111,9 +111,12 @@ void hv_para_set_sint_proxy(bool enable) */ u64 hv_para_get_synic_register(unsigned int reg) { + u64 val; + if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) return ~0ULL; - return native_read_msr(reg); + rdmsrq(reg, val); + return val; } =20 /* @@ -123,7 +126,7 @@ void hv_para_set_synic_register(unsigned int reg, u64 v= al) { if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) return; - native_write_msr(reg, val); + wrmsrq(reg, val); } =20 u64 hv_get_msr(unsigned int reg) diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index b5991d53fc0e..1002bdd45c0f 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -197,7 +197,7 @@ static void kvm_setup_secondary_clock(void) void kvmclock_disable(void) { if (msr_kvm_system_time) - native_write_msr(msr_kvm_system_time, 0); + wrmsrq(msr_kvm_system_time, 0); } =20 static void __init kvmclock_init_mem(void) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 8f8bc863e214..1c0e7cae9e49 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -389,12 +389,12 @@ static void svm_init_erratum_383(void) return; =20 /* Use _safe variants to not break nested virtualization */ - if (native_read_msr_safe(MSR_AMD64_DC_CFG, &val)) + if (rdmsrq_safe(MSR_AMD64_DC_CFG, &val)) return; =20 val |=3D (1ULL << 47); =20 - native_write_msr_safe(MSR_AMD64_DC_CFG, val); + wrmsrq_safe(MSR_AMD64_DC_CFG, val); =20 erratum_383_found =3D true; } @@ -554,9 +554,9 @@ static int svm_enable_virtualization_cpu(void) u64 len, status =3D 0; int err; =20 - err =3D native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); + err =3D rdmsrq_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); if (!err) - err =3D native_read_msr_safe(MSR_AMD64_OSVW_STATUS, &status); + err =3D rdmsrq_safe(MSR_AMD64_OSVW_STATUS, &status); =20 if (err) osvw_status =3D osvw_len =3D 0; @@ -2029,7 +2029,7 @@ static bool is_erratum_383(void) if (!erratum_383_found) return false; =20 - if (native_read_msr_safe(MSR_IA32_MC0_STATUS, &value)) + if (rdmsrq_safe(MSR_IA32_MC0_STATUS, &value)) return false; =20 /* Bit 62 may or may not be set for this mce */ @@ -2040,11 +2040,11 @@ static bool is_erratum_383(void) =20 /* Clear MCi_STATUS registers */ for (i =3D 0; i < 6; ++i) - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); + wrmsrq_safe(MSR_IA32_MCx_STATUS(i), 0); =20 - if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { + if (!rdmsrq_safe(MSR_IA32_MCG_STATUS, &value)) { value &=3D ~(1ULL << 2); - native_write_msr_safe(MSR_IA32_MCG_STATUS, value); + wrmsrq_safe(MSR_IA32_MCG_STATUS, value); } =20 /* Flush tlb to evict multi-match entries */ diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 8f89ce0b67e3..d49a3bdc448b 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -323,7 +323,7 @@ static u64 xen_amd_read_pmc(int counter) u64 val; =20 msr =3D amd_counters_base + (counter * amd_msr_step); - native_read_msr_safe(msr, &val); + rdmsrq_safe(msr, &val); return val; } =20 @@ -349,7 +349,7 @@ static u64 xen_intel_read_pmc(int counter) else msr =3D MSR_IA32_PERFCTR0 + counter; =20 - native_read_msr_safe(msr, &val); + rdmsrq_safe(msr, &val); return val; } =20 --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A569831AF2D for ; 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Wed, 18 Feb 2026 08:22:09 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id Ia7YJLF2lWlsHgAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:22:09 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list Subject: [PATCH v3 06/16] x86/msr: Move MSR trace calls one function level up Date: Wed, 18 Feb 2026 09:21:23 +0100 Message-ID: <20260218082133.400602-7-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[12]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" In order to prepare paravirt inlining of the MSR access instructions move the calls of MSR trace functions one function level up. Introduce {read|write}_msr[_safe]() helpers allowing to have common definitions in msr.h doing the trace calls. Signed-off-by: Juergen Gross Reviewed-by: H. Peter Anvin (Intel) --- arch/x86/include/asm/msr.h | 102 ++++++++++++++++++++------------ arch/x86/include/asm/paravirt.h | 38 +++--------- 2 files changed, 73 insertions(+), 67 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 9c2ea29e12a9..71f41af11591 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -103,14 +103,7 @@ static __always_inline u64 native_rdmsrq(u32 msr) =20 static inline u64 native_read_msr(u32 msr) { - u64 val; - - val =3D __rdmsr(msr); - - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, val, 0); - - return val; + return __rdmsr(msr); } =20 static inline int native_read_msr_safe(u32 msr, u64 *p) @@ -123,8 +116,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) : [err] "=3Dr" (err), EAX_EDX_RET(val, low, high) : "c" (msr)); - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err); =20 *p =3D EAX_EDX_VAL(val, low, high); =20 @@ -135,9 +126,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) static inline void notrace native_write_msr(u32 msr, u64 val) { native_wrmsrq(msr, val); - - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, 0); } =20 /* Can be uninlined because referenced by paravirt */ @@ -151,8 +139,6 @@ static inline int notrace native_write_msr_safe(u32 msr= , u64 val) : [err] "=3Da" (err) : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, err); return err; } =20 @@ -173,59 +159,96 @@ static inline u64 native_read_pmc(int counter) #include #else #include +static __always_inline u64 read_msr(u32 msr) +{ + return native_read_msr(msr); +} + +static __always_inline int read_msr_safe(u32 msr, u64 *p) +{ + return native_read_msr_safe(msr, p); +} + +static __always_inline void write_msr(u32 msr, u64 val) +{ + native_write_msr(msr, val); +} + +static __always_inline int write_msr_safe(u32 msr, u64 val) +{ + return native_write_msr_safe(msr, val); +} + +static __always_inline u64 rdpmc(int counter) +{ + return native_read_pmc(counter); +} + +#endif /* !CONFIG_PARAVIRT_XXL */ + /* * Access to machine-specific registers (available on 586 and better only) * Note: the rd* operations modify the parameters directly (without using * pointer indirection), this allows gcc to optimize better */ =20 +#define rdmsrq(msr, val) \ +do { \ + (val) =3D read_msr(msr); \ + if (tracepoint_enabled(read_msr)) \ + do_trace_read_msr(msr, val, 0); \ +} while (0) + #define rdmsr(msr, low, high) \ do { \ - u64 __val =3D native_read_msr((msr)); \ + u64 __val; \ + rdmsrq(msr, __val); \ (void)((low) =3D (u32)__val); \ (void)((high) =3D (u32)(__val >> 32)); \ } while (0) =20 -static inline void wrmsr(u32 msr, u32 low, u32 high) +/* rdmsr with exception handling */ +static inline int rdmsrq_safe(u32 msr, u64 *p) { - native_write_msr(msr, (u64)high << 32 | low); -} + int err; =20 -#define rdmsrq(msr, val) \ - ((val) =3D native_read_msr((msr))) + err =3D read_msr_safe(msr, p); =20 -static inline void wrmsrq(u32 msr, u64 val) -{ - native_write_msr(msr, val); -} + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, *p, err); =20 -/* wrmsr with exception handling */ -static inline int wrmsrq_safe(u32 msr, u64 val) -{ - return native_write_msr_safe(msr, val); + return err; } =20 -/* rdmsr with exception handling */ #define rdmsr_safe(msr, low, high) \ ({ \ u64 __val; \ - int __err =3D native_read_msr_safe((msr), &__val); \ + int __err =3D rdmsrq_safe((msr), &__val); \ (*low) =3D (u32)__val; \ (*high) =3D (u32)(__val >> 32); \ __err; \ }) =20 -static inline int rdmsrq_safe(u32 msr, u64 *p) +static inline void wrmsrq(u32 msr, u64 val) { - return native_read_msr_safe(msr, p); + write_msr(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, 0); } =20 -static __always_inline u64 rdpmc(int counter) +/* wrmsr with exception handling */ +static inline int wrmsrq_safe(u32 msr, u64 val) { - return native_read_pmc(counter); -} + int err; =20 -#endif /* !CONFIG_PARAVIRT_XXL */ + err =3D write_msr_safe(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, err); + + return err; +} =20 /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) @@ -242,6 +265,11 @@ static __always_inline void wrmsrns(u32 msr, u64 val) : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))); } =20 +static inline void wrmsr(u32 msr, u32 low, u32 high) +{ + wrmsrq(msr, (u64)high << 32 | low); +} + /* * Dual u32 version of wrmsrq_safe(): */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index cdfe4007443e..6b3aed5c2309 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -150,46 +150,24 @@ static inline int paravirt_write_msr_safe(u32 msr, u6= 4 val) return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); } =20 -#define rdmsr(msr, val1, val2) \ -do { \ - u64 _l =3D paravirt_read_msr(msr); \ - val1 =3D (u32)_l; \ - val2 =3D _l >> 32; \ -} while (0) - -static __always_inline void wrmsr(u32 msr, u32 low, u32 high) +static __always_inline u64 read_msr(u32 msr) { - paravirt_write_msr(msr, (u64)high << 32 | low); + return paravirt_read_msr(msr); } =20 -#define rdmsrq(msr, val) \ -do { \ - val =3D paravirt_read_msr(msr); \ -} while (0) - -static inline void wrmsrq(u32 msr, u64 val) +static __always_inline int read_msr_safe(u32 msr, u64 *p) { - paravirt_write_msr(msr, val); + return paravirt_read_msr_safe(msr, p); } =20 -static inline int wrmsrq_safe(u32 msr, u64 val) +static __always_inline void write_msr(u32 msr, u64 val) { - return paravirt_write_msr_safe(msr, val); + paravirt_write_msr(msr, val); } =20 -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, a, b) \ -({ \ - u64 _l; \ - int _err =3D paravirt_read_msr_safe((msr), &_l); \ - (*a) =3D (u32)_l; \ - (*b) =3D (u32)(_l >> 32); \ - _err; \ -}) - -static __always_inline int rdmsrq_safe(u32 msr, u64 *p) +static __always_inline int write_msr_safe(u32 msr, u64 val) { - return paravirt_read_msr_safe(msr, p); + return paravirt_write_msr_safe(msr, val); } =20 static __always_inline u64 rdpmc(int counter) --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E5AC318EFE for ; Wed, 18 Feb 2026 08:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402938; cv=none; b=U1g10/r8H9zSLdyi7m9z1fXSD5pGpFJW6BABBGimP5KUROgJl7Rj7NObnNDY4gO1/mW8tvzoPECNVgNw4JFu0oQhgIWwihV7NJUImkcmBtBrFSF1bli8AczhQq9COCPiqmmVAhpztbjM2i7QYiz+Z1kNfmfdSce/wnx4uXqVFNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402938; c=relaxed/simple; bh=z5Utanc9sf7mnKnXQSWxSgOi1tLmk6n38LnXDzDJNSo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Wed, 18 Feb 2026 08:22:15 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id MrekDLd2lWlzHgAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:22:15 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v3 07/16] x86/opcode: Add immediate form MSR instructions Date: Wed, 18 Feb 2026 09:21:24 +0100 Message-ID: <20260218082133.400602-8-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[9]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" Add the instruction opcodes used by the immediate form WRMSRNS/RDMSR to x86-opcode-map. Signed-off-by: Xin Li (Intel) Signed-off-by: Juergen Gross Reviewed-by: H. Peter Anvin (Intel) --- V2: - new patch, taken from the RFC v2 MSR refactor series by Xin Li --- arch/x86/lib/x86-opcode-map.txt | 5 +++-- tools/arch/x86/lib/x86-opcode-map.txt | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.= txt index 2a4e69ecc2de..62f7c90b9a83 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -844,7 +844,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) |= CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | = WRUSSD/Q My,Gy (66) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy +f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) |= SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | = URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B) f9: MOVDIRI My,Gy @@ -1019,7 +1019,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPI= D Gy,Mdq (F3),(ev) f2: INVPCID Gy,Mdq (F3),(ev) f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es) f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es) -f6: Grp3_1 Eb (1A),(ev) +f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3)= ,(11B),(ev) f7: Grp3_2 Ev (1A),(es) f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Md= qq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev) f9: MOVDIRI My,Gy (ev) @@ -1108,6 +1108,7 @@ EndTable Table: VEX map 7 Referrer: AVXcode: 7 +f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B) f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B) EndTable =20 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86= -opcode-map.txt index 2a4e69ecc2de..62f7c90b9a83 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -844,7 +844,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) |= CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | = WRUSSD/Q My,Gy (66) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy +f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) |= SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | = URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B) f9: MOVDIRI My,Gy @@ -1019,7 +1019,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPI= D Gy,Mdq (F3),(ev) f2: INVPCID Gy,Mdq (F3),(ev) f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es) f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es) -f6: Grp3_1 Eb (1A),(ev) +f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3)= ,(11B),(ev) f7: Grp3_2 Ev (1A),(es) f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Md= qq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev) f9: MOVDIRI My,Gy (ev) @@ -1108,6 +1108,7 @@ EndTable Table: VEX map 7 Referrer: AVXcode: 7 +f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B) f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B) EndTable =20 --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B05D3191AF for ; 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Wed, 18 Feb 2026 08:22:20 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v3 08/16] x86/extable: Add support for immediate form MSR instructions Date: Wed, 18 Feb 2026 09:21:25 +0100 Message-ID: <20260218082133.400602-9-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 16F013E6E9 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, taken from the RFC v2 MSR refactor series by Xin Li V3: - use instruction decoder (Peter Zijlstra) --- arch/x86/mm/extable.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 2fdc1f1f5adb..22e14ff2d3e9 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -166,23 +166,48 @@ static bool ex_handler_uaccess(const struct exception= _table_entry *fixup, static bool ex_handler_msr(const struct exception_table_entry *fixup, struct pt_regs *regs, bool wrmsr, bool safe, int reg) { + struct insn insn; + bool imm_insn; + u32 msr; + + imm_insn =3D insn_decode_kernel(&insn, (void *)regs->ip) && + insn.vex_prefix.nbytes; + msr =3D imm_insn ? insn.immediate.value : (u32)regs->cx; + if (__ONCE_LITE_IF(!safe && wrmsr)) { - pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%08= x%08x) at rIP: 0x%lx (%pS)\n", - (unsigned int)regs->cx, (unsigned int)regs->dx, - (unsigned int)regs->ax, regs->ip, (void *)regs->ip); + /* + * To maintain consistency with existing RDMSR and WRMSR(NS) instruction= s, + * the register operand for immediate form MSR instructions is ALWAYS + * encoded as RAX in for reading or writing the MSR value. + */ + u64 msr_val =3D regs->ax; + + if (!imm_insn) { + /* + * On processors that support the Intel 64 architecture, the + * high-order 32 bits of each of RAX and RDX are ignored. + */ + msr_val &=3D 0xffffffff; + msr_val |=3D (u64)regs->dx << 32; + } + + pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%01= 6llx) at rIP: 0x%lx (%pS)\n", + msr, msr_val, regs->ip, (void *)regs->ip); show_stack_regs(regs); } =20 if (__ONCE_LITE_IF(!safe && !wrmsr)) { pr_warn("unchecked MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)= \n", - (unsigned int)regs->cx, regs->ip, (void *)regs->ip); + msr, regs->ip, (void *)regs->ip); show_stack_regs(regs); } =20 if (!wrmsr) { /* Pretend that the read succeeded and returned 0. */ regs->ax =3D 0; - regs->dx =3D 0; + + if (!imm_insn) + regs->dx =3D 0; } =20 if (safe) --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AE3E318B94 for ; Wed, 18 Feb 2026 08:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402950; cv=none; b=q+20zHYeDWaTfh4SxNV7JU29dvhuzcnQvilFIooACV/0486cNiFaQ3x1gTCuJooBZ7kqO3+hBM40t06u0HCuZhXcEOn/9n+XgaNS0faQjP3U+lGZydCNPQEIt0QsLyRknHdovGS/QSf0lcfmNo25dyEFfom1+P9VUR5MyqgbiS0= ARC-Message-Signature: i=1; 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Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Sean Christopherson , Paolo Bonzini , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Subject: [PATCH v3 09/16] x86/msr: Use the alternatives mechanism for WRMSR Date: Wed, 18 Feb 2026 09:21:26 +0100 Message-ID: <20260218082133.400602-10-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -5.30 X-Spam-Level: X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.999]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[17]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; FREEMAIL_CC(0.00)[suse.com,zytor.com,kernel.org,redhat.com,alien8.de,linux.intel.com,google.com,gmail.com]; RCVD_COUNT_TWO(0.00)[2]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; FROM_HAS_DN(0.00)[]; TAGGED_RCPT(0.00)[lkml]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" When available use one of the non-serializing WRMSR variants (WRMSRNS with or without an immediate operand specifying the MSR register) in __wrmsrq(). For the safe/unsafe variants make __wrmsrq() to be a common base function instead of duplicating the ALTERNATIVE*() macros. This requires to let native_wrmsr() use native_wrmsrq() instead of __wrmsrq(). While changing this, convert native_wrmsr() into an inline function. Replace the only call of wsrmsrns() with the now equivalent call to native_wrmsrq() and remove wsrmsrns(). The paravirt case will be handled later. Originally-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, partially taken from "[RFC PATCH v2 21/34] x86/msr: Utilize the alternatives mechanism to write MSR" by Xin Li. --- arch/x86/include/asm/fred.h | 2 +- arch/x86/include/asm/msr.h | 144 +++++++++++++++++++++++++++--------- arch/x86/kvm/vmx/vmx.c | 2 +- 3 files changed, 111 insertions(+), 37 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 2bb65677c079..71fc0c6e4e32 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -101,7 +101,7 @@ static __always_inline void fred_update_rsp0(void) unsigned long rsp0 =3D (unsigned long) task_stack_page(current) + THREAD_= SIZE; =20 if (cpu_feature_enabled(X86_FEATURE_FRED) && (__this_cpu_read(fred_rsp0) = !=3D rsp0)) { - wrmsrns(MSR_IA32_FRED_RSP0, rsp0); + native_wrmsrq(MSR_IA32_FRED_RSP0, rsp0); __this_cpu_write(fred_rsp0, rsp0); } } diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 71f41af11591..ba11c3375cbd 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -7,11 +7,11 @@ #ifndef __ASSEMBLER__ =20 #include -#include #include #include #include =20 +#include #include #include =20 @@ -56,6 +56,36 @@ static inline void do_trace_read_msr(u32 msr, u64 val, i= nt failed) {} static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {} #endif =20 +/* The GNU Assembler (Gas) with Binutils 2.40 adds WRMSRNS support */ +#if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >=3D 24000 +#define ASM_WRMSRNS "wrmsrns\n\t" +#else +#define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) +#endif + +/* The GNU Assembler (Gas) with Binutils 2.41 adds the .insn directive sup= port */ +#if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >=3D 24100 +#define ASM_WRMSRNS_IMM \ + " .insn VEX.128.F3.M7.W0 0xf6 /0, %[val], %[msr]%{:u32}\n\t" +#else +/* + * Note, clang also doesn't support the .insn directive. + * + * The register operand is encoded as %rax because all uses of the immedia= te + * form MSR access instructions reference %rax as the register operand. + */ +#define ASM_WRMSRNS_IMM \ + " .byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]" +#endif + +#define PREPARE_RDX_FOR_WRMSR \ + "mov %%rax, %%rdx\n\t" \ + "shr $0x20, %%rdx\n\t" + +#define PREPARE_RCX_RDX_FOR_WRMSR \ + "mov %[msr], %%ecx\n\t" \ + PREPARE_RDX_FOR_WRMSR + /* * __rdmsr() and __wrmsr() are the two primitives which are the bare minim= um MSR * accessors and should not have any tracing or other functionality piggyb= acking @@ -75,12 +105,76 @@ static __always_inline u64 __rdmsr(u32 msr) return EAX_EDX_VAL(val, low, high); } =20 -static __always_inline void __wrmsrq(u32 msr, u64 val) +static __always_inline bool __wrmsrq_variable(u32 msr, u64 val, int type) { - asm volatile("1: wrmsr\n" - "2:\n" - _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) - : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); +#ifdef CONFIG_X86_64 + BUILD_BUG_ON(__builtin_constant_p(msr)); +#endif + + /* + * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redundant + * DS prefix to avoid a trailing NOP. + */ + asm_inline volatile goto( + "1:\n" + ALTERNATIVE("ds wrmsr", + ASM_WRMSRNS, + X86_FEATURE_WRMSRNS) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) + + : + : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)), [type] "i" (type) + : "memory" + : badmsr); + + return false; + +badmsr: + return true; +} + +#ifdef CONFIG_X86_64 +/* + * Non-serializing WRMSR or its immediate form, when available. + * + * Otherwise, it falls back to a serializing WRMSR. + */ +static __always_inline bool __wrmsrq_constant(u32 msr, u64 val, int type) +{ + BUILD_BUG_ON(!__builtin_constant_p(msr)); + + asm_inline volatile goto( + "1:\n" + ALTERNATIVE_2(PREPARE_RCX_RDX_FOR_WRMSR + "2: ds wrmsr", + PREPARE_RCX_RDX_FOR_WRMSR + ASM_WRMSRNS, + X86_FEATURE_WRMSRNS, + ASM_WRMSRNS_IMM, + X86_FEATURE_MSR_IMM) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For WRMSRNS immediate */ + _ASM_EXTABLE_TYPE(2b, %l[badmsr], %c[type]) /* For WRMSR(NS) */ + + : + : [val] "a" (val), [msr] "i" (msr), [type] "i" (type) + : "memory", "ecx", "rdx" + : badmsr); + + return false; + +badmsr: + return true; +} +#endif + +static __always_inline bool __wrmsrq(u32 msr, u64 val, int type) +{ +#ifdef CONFIG_X86_64 + if (__builtin_constant_p(msr)) + return __wrmsrq_constant(msr, val, type); +#endif + + return __wrmsrq_variable(msr, val, type); } =20 #define native_rdmsr(msr, val1, val2) \ @@ -95,11 +189,15 @@ static __always_inline u64 native_rdmsrq(u32 msr) return __rdmsr(msr); } =20 -#define native_wrmsr(msr, low, high) \ - __wrmsrq((msr), (u64)(high) << 32 | (low)) +static __always_inline void native_wrmsrq(u32 msr, u64 val) +{ + __wrmsrq(msr, val, EX_TYPE_WRMSR); +} =20 -#define native_wrmsrq(msr, val) \ - __wrmsrq((msr), (val)) +static __always_inline void native_wrmsr(u32 msr, u32 low, u32 high) +{ + native_wrmsrq(msr, (u64)high << 32 | low); +} =20 static inline u64 native_read_msr(u32 msr) { @@ -131,15 +229,7 @@ static inline void notrace native_write_msr(u32 msr, u= 64 val) /* Can be uninlined because referenced by paravirt */ static inline int notrace native_write_msr_safe(u32 msr, u64 val) { - int err; - - asm volatile("1: wrmsr ; xor %[err],%[err]\n" - "2:\n\t" - _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %[err]) - : [err] "=3Da" (err) - : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) - : "memory"); - return err; + return __wrmsrq(msr, val, EX_TYPE_WRMSR_SAFE) ? -EIO : 0; } =20 extern int rdmsr_safe_regs(u32 regs[8]); @@ -158,7 +248,6 @@ static inline u64 native_read_pmc(int counter) #ifdef CONFIG_PARAVIRT_XXL #include #else -#include static __always_inline u64 read_msr(u32 msr) { return native_read_msr(msr); @@ -250,21 +339,6 @@ static inline int wrmsrq_safe(u32 msr, u64 val) return err; } =20 -/* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ -#define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) - -/* Non-serializing WRMSR, when available. Falls back to a serializing WRM= SR. */ -static __always_inline void wrmsrns(u32 msr, u64 val) -{ - /* - * WRMSR is 2 bytes. WRMSRNS is 3 bytes. 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Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v3 10/16] x86/msr: Use the alternatives mechanism for RDMSR Date: Wed, 18 Feb 2026 09:21:27 +0100 Message-ID: <20260218082133.400602-11-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[9]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" When available use the immediate variant of RDMSR in __rdmsr(). For the safe/unsafe variants make __rdmsr() to be a common base function instead of duplicating the ALTERNATIVE*() macros. Modify native_rdmsr() and native_read_msr() to use native_rdmsrq(). The paravirt case will be handled later. Originally-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, partially taken from "[RFC PATCH v2 22/34] x86/msr: Utilize the alternatives mechanism to read MSR" by Xin Li --- arch/x86/include/asm/msr.h | 116 ++++++++++++++++++++++++++++--------- 1 file changed, 89 insertions(+), 27 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index ba11c3375cbd..990268dea5ad 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -65,6 +65,8 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int f= ailed) {} =20 /* The GNU Assembler (Gas) with Binutils 2.41 adds the .insn directive sup= port */ #if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >=3D 24100 +#define ASM_RDMSR_IMM \ + " .insn VEX.128.F2.M7.W0 0xf6 /0, %[msr]%{:u32}, %[val]\n\t" #define ASM_WRMSRNS_IMM \ " .insn VEX.128.F3.M7.W0 0xf6 /0, %[val], %[msr]%{:u32}\n\t" #else @@ -74,10 +76,17 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int= failed) {} * The register operand is encoded as %rax because all uses of the immedia= te * form MSR access instructions reference %rax as the register operand. */ +#define ASM_RDMSR_IMM \ + " .byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]" #define ASM_WRMSRNS_IMM \ " .byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]" #endif =20 +#define RDMSR_AND_SAVE_RESULT \ + "rdmsr\n\t" \ + "shl $0x20, %%rdx\n\t" \ + "or %%rdx, %%rax\n\t" + #define PREPARE_RDX_FOR_WRMSR \ "mov %%rax, %%rdx\n\t" \ "shr $0x20, %%rdx\n\t" @@ -93,16 +102,76 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, in= t failed) {} * think of extending them - you will be slapped with a stinking trout or = a frozen * shark will reach you, wherever you are! You've been warned. */ -static __always_inline u64 __rdmsr(u32 msr) +static __always_inline bool __rdmsrq_variable(u32 msr, u64 *val, int type) + { +#ifdef CONFIG_X86_64 + BUILD_BUG_ON(__builtin_constant_p(msr)); + + asm_inline volatile goto( + "1:\n" + RDMSR_AND_SAVE_RESULT + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */ + + : [val] "=3Da" (*val) + : "c" (msr), [type] "i" (type) + : "rdx" + : badmsr); +#else + asm_inline volatile goto( + "1: rdmsr\n\t" + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */ + + : "=3DA" (*val) + : "c" (msr), [type] "i" (type) + : + : badmsr); +#endif + + return false; + +badmsr: + *val =3D 0; + + return true; +} + +#ifdef CONFIG_X86_64 +static __always_inline bool __rdmsrq_constant(u32 msr, u64 *val, int type) { - EAX_EDX_DECLARE_ARGS(val, low, high); + BUILD_BUG_ON(!__builtin_constant_p(msr)); =20 - asm volatile("1: rdmsr\n" - "2:\n" - _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR) - : EAX_EDX_RET(val, low, high) : "c" (msr)); + asm_inline volatile goto( + "1:\n" + ALTERNATIVE("mov %[msr], %%ecx\n\t" + "2:\n" + RDMSR_AND_SAVE_RESULT, + ASM_RDMSR_IMM, + X86_FEATURE_MSR_IMM) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR immediate */ + _ASM_EXTABLE_TYPE(2b, %l[badmsr], %c[type]) /* For RDMSR */ + + : [val] "=3Da" (*val) + : [msr] "i" (msr), [type] "i" (type) + : "ecx", "rdx" + : badmsr); =20 - return EAX_EDX_VAL(val, low, high); + return false; + +badmsr: + *val =3D 0; + + return true; +} +#endif + +static __always_inline bool __rdmsr(u32 msr, u64 *val, int type) +{ +#ifdef CONFIG_X86_64 + if (__builtin_constant_p(msr)) + return __rdmsrq_constant(msr, val, type); +#endif + + return __rdmsrq_variable(msr, val, type); } =20 static __always_inline bool __wrmsrq_variable(u32 msr, u64 val, int type) @@ -177,18 +246,22 @@ static __always_inline bool __wrmsrq(u32 msr, u64 val= , int type) return __wrmsrq_variable(msr, val, type); } =20 +static __always_inline u64 native_rdmsrq(u32 msr) +{ + u64 val; + + __rdmsr(msr, &val, EX_TYPE_RDMSR); + + return val; +} + #define native_rdmsr(msr, val1, val2) \ do { \ - u64 __val =3D __rdmsr((msr)); \ + u64 __val =3D native_rdmsrq((msr)); \ (void)((val1) =3D (u32)__val); \ (void)((val2) =3D (u32)(__val >> 32)); \ } while (0) =20 -static __always_inline u64 native_rdmsrq(u32 msr) -{ - return __rdmsr(msr); -} - static __always_inline void native_wrmsrq(u32 msr, u64 val) { __wrmsrq(msr, val, EX_TYPE_WRMSR); @@ -201,23 +274,12 @@ static __always_inline void native_wrmsr(u32 msr, u32= low, u32 high) =20 static inline u64 native_read_msr(u32 msr) { - return __rdmsr(msr); + return native_rdmsrq(msr); } =20 -static inline int native_read_msr_safe(u32 msr, u64 *p) +static inline int native_read_msr_safe(u32 msr, u64 *val) { - int err; - EAX_EDX_DECLARE_ARGS(val, low, high); - - asm volatile("1: rdmsr ; xor %[err],%[err]\n" - "2:\n\t" - _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) - : [err] "=3Dr" (err), EAX_EDX_RET(val, low, high) - : "c" (msr)); - - *p =3D EAX_EDX_VAL(val, low, high); - - return err; + return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; } =20 /* Can be uninlined because referenced by paravirt */ --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC6ED31BC95 for ; Wed, 18 Feb 2026 08:22:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402961; cv=none; b=W5fgBeqGqJ3wgRLdanHGalJDSZUd1/GlAm+dCp0xpehuldc7FvWm8/AC4Hw78P5+X5YFyEBUgWb1fsSmpUvLEb/w9yzPHyGsiWvmSEivnMGAuXJ/mfojLvEodDDnb1PV4PJuZvI6o5lZ5COV+w/ROK7c+FUUu1kErcw60AiMZ60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771402961; c=relaxed/simple; bh=SneiS0sm9MvHpQ9FzmFP16Mj8QcCFPP/d00dqRh/oXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PBr9ODif1Sv5Hcge9eU0vjtvwMqBOkA5SoNAoYqtPVPNp+hZt6sMPskuS+RpQa3nrpoKLnW7fTcIKNRdzVapsMvo6EQcAM6gGOsxIqVSlp3awteh0LmTcA9wOIzdUiQCuVBQhfTMgVM4sscv707SK1Anmj7GAgY7jLy9oYGmRWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id D01E63E6F2; Wed, 18 Feb 2026 08:22:37 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 90F483EA65; Wed, 18 Feb 2026 08:22:37 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id f90+Is12lWmpHgAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:22:37 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v3 11/16] x86/alternatives: Add ALTERNATIVE_4() Date: Wed, 18 Feb 2026 09:21:28 +0100 Message-ID: <20260218082133.400602-12-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: D01E63E6F2 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: Content-Type: text/plain; charset="utf-8" For supporting WRMSR with CONFIG_PARAVIRT_XXL using direct instruction replacement, ALTERNATIVE_4() is needed. Signed-off-by: Juergen Gross --- V3: - new patch --- arch/x86/include/asm/alternative.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alte= rnative.h index 03364510d5fe..119634eb3361 100644 --- a/arch/x86/include/asm/alternative.h +++ b/arch/x86/include/asm/alternative.h @@ -231,6 +231,12 @@ static inline int alternatives_text_reserved(void *sta= rt, void *end) ALTERNATIVE(ALTERNATIVE_2(oldinstr, newinstr1, ft_flags1, newinstr2, ft_f= lags2), \ newinstr3, ft_flags3) =20 +#define ALTERNATIVE_4(oldinstr, newinstr1, ft_flags1, newinstr2, ft_flags2= , \ + newinstr3, ft_flags3, newinstr4, ft_flags4) \ + ALTERNATIVE(ALTERNATIVE_3(oldinstr, newinstr1, ft_flags1, \ + newinstr2, ft_flags2, newinstr3, ft_flags3),\ + newinstr4, ft_flags4) + /* * Alternative instructions for different CPU types or capabilities. * --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771402978617134.5266712351164; Wed, 18 Feb 2026 00:22:58 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1235329.1538305 (Exim 4.92) (envelope-from ) id 1vscpZ-00010E-SL; Wed, 18 Feb 2026 08:22:45 +0000 Received: by outflank-mailman (output) from mailman id 1235329.1538305; Wed, 18 Feb 2026 08:22:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vscpZ-000107-PJ; Wed, 18 Feb 2026 08:22:45 +0000 Received: by outflank-mailman (input) for mailman id 1235329; Wed, 18 Feb 2026 08:22:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vscpY-0000J6-Vq for xen-devel@lists.xenproject.org; Wed, 18 Feb 2026 08:22:44 +0000 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ff90fd4c-0ca2-11f1-b164-2bf370ae4941; Wed, 18 Feb 2026 09:22:44 +0100 (CET) Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 85F953E704; Wed, 18 Feb 2026 08:22:43 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 1DE2A3EA65; Wed, 18 Feb 2026 08:22:43 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id aOkqBtN2lWkuHwAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:22:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ff90fd4c-0ca2-11f1-b164-2bf370ae4941 Authentication-Results: smtp-out1.suse.de; none From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Boris Ostrovsky , Josh Poimboeuf , Peter Zijlstra , xen-devel@lists.xenproject.org Subject: [PATCH v3 12/16] x86/paravirt: Split off MSR related hooks into new header Date: Wed, 18 Feb 2026 09:21:29 +0100 Message-ID: <20260218082133.400602-13-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 85F953E704 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-ZM-MESSAGEID: 1771402981020154100 Content-Type: text/plain; charset="utf-8" Move the WRMSR, RDMSR and RDPMC related parts of paravirt.h and paravirt_types.h into a new header file paravirt-msr.h. Signed-off-by: Juergen Gross --- V3: - new patch --- arch/x86/include/asm/msr.h | 2 +- arch/x86/include/asm/paravirt-msr.h | 46 +++++++++++++++++++++++++++ arch/x86/include/asm/paravirt.h | 45 -------------------------- arch/x86/include/asm/paravirt_types.h | 13 -------- arch/x86/kernel/paravirt.c | 14 +++++--- arch/x86/xen/enlighten_pv.c | 11 ++++--- tools/objtool/check.c | 1 + 7 files changed, 63 insertions(+), 69 deletions(-) create mode 100644 arch/x86/include/asm/paravirt-msr.h diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 990268dea5ad..66f57265f2f8 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -308,7 +308,7 @@ static inline u64 native_read_pmc(int counter) } =20 #ifdef CONFIG_PARAVIRT_XXL -#include +#include #else static __always_inline u64 read_msr(u32 msr) { diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/par= avirt-msr.h new file mode 100644 index 000000000000..b299864b438a --- /dev/null +++ b/arch/x86/include/asm/paravirt-msr.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_PARAVIRT_MSR_H +#define _ASM_X86_PARAVIRT_MSR_H + +#include + +struct pv_msr_ops { + /* Unsafe MSR operations. These will warn or panic on failure. */ + u64 (*read_msr)(u32 msr); + void (*write_msr)(u32 msr, u64 val); + + /* Safe MSR operations. Returns 0 or -EIO. */ + int (*read_msr_safe)(u32 msr, u64 *val); + int (*write_msr_safe)(u32 msr, u64 val); + + u64 (*read_pmc)(int counter); +} __no_randomize_layout; + +extern struct pv_msr_ops pv_ops_msr; + +static __always_inline u64 read_msr(u32 msr) +{ + return PVOP_CALL1(u64, pv_ops_msr, read_msr, msr); +} + +static __always_inline void write_msr(u32 msr, u64 val) +{ + PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); +} + +static __always_inline int read_msr_safe(u32 msr, u64 *val) +{ + return PVOP_CALL2(int, pv_ops_msr, read_msr_safe, msr, val); +} + +static __always_inline int write_msr_safe(u32 msr, u64 val) +{ + return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); +} + +static __always_inline u64 rdpmc(int counter) +{ + return PVOP_CALL1(u64, pv_ops_msr, read_pmc, counter); +} + +#endif /* _ASM_X86_PARAVIRT_MSR_H */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index 6b3aed5c2309..fcda593dd5c9 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -130,51 +130,6 @@ static inline void __write_cr4(unsigned long x) PVOP_VCALL1(pv_ops, cpu.write_cr4, x); } =20 -static inline u64 paravirt_read_msr(u32 msr) -{ - return PVOP_CALL1(u64, pv_ops, cpu.read_msr, msr); -} - -static inline void paravirt_write_msr(u32 msr, u64 val) -{ - PVOP_VCALL2(pv_ops, cpu.write_msr, msr, val); -} - -static inline int paravirt_read_msr_safe(u32 msr, u64 *val) -{ - return PVOP_CALL2(int, pv_ops, cpu.read_msr_safe, msr, val); -} - -static inline int paravirt_write_msr_safe(u32 msr, u64 val) -{ - return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); -} - -static __always_inline u64 read_msr(u32 msr) -{ - return paravirt_read_msr(msr); -} - -static __always_inline int read_msr_safe(u32 msr, u64 *p) -{ - return paravirt_read_msr_safe(msr, p); -} - -static __always_inline void write_msr(u32 msr, u64 val) -{ - paravirt_write_msr(msr, val); -} - -static __always_inline int write_msr_safe(u32 msr, u64 val) -{ - return paravirt_write_msr_safe(msr, val); -} - -static __always_inline u64 rdpmc(int counter) -{ - return PVOP_CALL1(u64, pv_ops, cpu.read_pmc, counter); -} - static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned en= tries) { PVOP_VCALL2(pv_ops, cpu.alloc_ldt, ldt, entries); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index 4f5ae0068aab..1e7188247c1f 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -67,19 +67,6 @@ struct pv_cpu_ops { void (*cpuid)(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); =20 - /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(u32 msr); - void (*write_msr)(u32 msr, u64 val); - - /* - * Safe MSR operations. - * Returns 0 or -EIO. - */ - int (*read_msr_safe)(u32 msr, u64 *val); - int (*write_msr_safe)(u32 msr, u64 val); - - u64 (*read_pmc)(int counter); - void (*start_context_switch)(struct task_struct *prev); void (*end_context_switch)(struct task_struct *next); #endif diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 792fa96b3233..089a87ac1582 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -109,11 +109,6 @@ struct paravirt_patch_template pv_ops =3D { .cpu.read_cr0 =3D native_read_cr0, .cpu.write_cr0 =3D native_write_cr0, .cpu.write_cr4 =3D native_write_cr4, - .cpu.read_msr =3D native_read_msr, - .cpu.write_msr =3D native_write_msr, - .cpu.read_msr_safe =3D native_read_msr_safe, - .cpu.write_msr_safe =3D native_write_msr_safe, - .cpu.read_pmc =3D native_read_pmc, .cpu.load_tr_desc =3D native_load_tr_desc, .cpu.set_ldt =3D native_set_ldt, .cpu.load_gdt =3D native_load_gdt, @@ -215,6 +210,15 @@ struct paravirt_patch_template pv_ops =3D { }; =20 #ifdef CONFIG_PARAVIRT_XXL +struct pv_msr_ops pv_ops_msr =3D { + .read_msr =3D native_read_msr, + .write_msr =3D native_write_msr, + .read_msr_safe =3D native_read_msr_safe, + .write_msr_safe =3D native_write_msr_safe, + .read_pmc =3D native_read_pmc, +}; +EXPORT_SYMBOL(pv_ops_msr); + NOKPROBE_SYMBOL(native_load_idt); #endif =20 diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 0a6a50f3e9a9..b94437f26cc0 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1366,11 +1366,6 @@ asmlinkage __visible void __init xen_start_kernel(st= ruct start_info *si) pv_ops.cpu.read_cr0 =3D xen_read_cr0; pv_ops.cpu.write_cr0 =3D xen_write_cr0; pv_ops.cpu.write_cr4 =3D xen_write_cr4; - pv_ops.cpu.read_msr =3D xen_read_msr; - pv_ops.cpu.write_msr =3D xen_write_msr; - pv_ops.cpu.read_msr_safe =3D xen_read_msr_safe; - pv_ops.cpu.write_msr_safe =3D xen_write_msr_safe; - pv_ops.cpu.read_pmc =3D xen_read_pmc; pv_ops.cpu.load_tr_desc =3D paravirt_nop; pv_ops.cpu.set_ldt =3D xen_set_ldt; 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Wed, 18 Feb 2026 08:22:48 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v3 13/16] x86/paravirt: Prepare support of MSR instruction interfaces Date: Wed, 18 Feb 2026 09:21:30 +0100 Message-ID: <20260218082133.400602-14-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 242CD3E6E8 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Content-Type: text/plain; charset="utf-8" Make the paravirt callee-save infrastructure more generic by allowing arbitrary register interfaces via prologue and epilogue helper macros. Signed-off-by: Juergen Gross --- V3: - carved out from patch 5 of V1 --- arch/x86/include/asm/paravirt_types.h | 43 ++++++++++++++--------- arch/x86/include/asm/qspinlock_paravirt.h | 4 +-- 2 files changed, 29 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index 1e7188247c1f..999a5abe54ed 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -457,27 +457,38 @@ extern struct paravirt_patch_template pv_ops; #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" #else +/* Save and restore caller-save registers, except %rax, %rcx and %rdx. */ +#define PV_SAVE_COMMON_CALLER_REGS \ + "push %rsi;" \ + "push %rdi;" \ + "push %r8;" \ + "push %r9;" \ + "push %r10;" \ + "push %r11;" + +#define PV_RESTORE_COMMON_CALLER_REGS \ + "pop %r11;" \ + "pop %r10;" \ + "pop %r9;" \ + "pop %r8;" \ + "pop %rdi;" \ + "pop %rsi;" + /* save and restore all caller-save registers, except return value */ #define PV_SAVE_ALL_CALLER_REGS \ "push %rcx;" \ "push %rdx;" \ - "push %rsi;" \ - "push %rdi;" \ - "push %r8;" \ - "push %r9;" \ - "push %r10;" \ - "push %r11;" + PV_SAVE_COMMON_CALLER_REGS + #define PV_RESTORE_ALL_CALLER_REGS \ - "pop %r11;" \ - "pop %r10;" \ - "pop %r9;" \ - "pop %r8;" \ - "pop %rdi;" \ - "pop %rsi;" \ + PV_RESTORE_COMMON_CALLER_REGS \ "pop %rdx;" \ "pop %rcx;" #endif =20 +#define PV_PROLOGUE_ALL(func) PV_SAVE_ALL_CALLER_REGS +#define PV_EPILOGUE_ALL(func) PV_RESTORE_ALL_CALLER_REGS + /* * Generate a thunk around a function which saves all caller-save * registers except for the return value. This allows C functions to @@ -491,7 +502,7 @@ extern struct paravirt_patch_template pv_ops; * functions. */ #define PV_THUNK_NAME(func) "__raw_callee_save_" #func -#define __PV_CALLEE_SAVE_REGS_THUNK(func, section) \ +#define __PV_CALLEE_SAVE_REGS_THUNK(func, section, helper) \ extern typeof(func) __raw_callee_save_##func; \ \ asm(".pushsection " section ", \"ax\";" \ @@ -501,16 +512,16 @@ extern struct paravirt_patch_template pv_ops; PV_THUNK_NAME(func) ":" \ ASM_ENDBR \ FRAME_BEGIN \ - PV_SAVE_ALL_CALLER_REGS \ + PV_PROLOGUE_##helper(func) \ "call " #func ";" \ - PV_RESTORE_ALL_CALLER_REGS \ + PV_EPILOGUE_##helper(func) \ FRAME_END \ ASM_RET \ ".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \ ".popsection") =20 #define PV_CALLEE_SAVE_REGS_THUNK(func) \ - __PV_CALLEE_SAVE_REGS_THUNK(func, ".text") + __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", ALL) =20 /* Get a reference to a callee-save function */ #define PV_CALLEE_SAVE(func) \ diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/a= sm/qspinlock_paravirt.h index 0a985784be9b..002b17f0735e 100644 --- a/arch/x86/include/asm/qspinlock_paravirt.h +++ b/arch/x86/include/asm/qspinlock_paravirt.h @@ -14,7 +14,7 @@ void __lockfunc __pv_queued_spin_unlock_slowpath(struct q= spinlock *lock, u8 lock */ #ifdef CONFIG_64BIT =20 -__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.t= ext"); +__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.t= ext", ALL); #define __pv_queued_spin_unlock __pv_queued_spin_unlock =20 /* @@ -61,7 +61,7 @@ DEFINE_ASM_FUNC(__raw_callee_save___pv_queued_spin_unlock, #else /* CONFIG_64BIT */ =20 extern void __lockfunc __pv_queued_spin_unlock(struct qspinlock *lock); -__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock, ".spinlock.text"); +__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock, ".spinlock.text", ALL= ); =20 #endif /* CONFIG_64BIT */ #endif --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v3 14/16] x86/paravirt: Switch MSR access pv_ops functions to instruction interfaces Date: Wed, 18 Feb 2026 09:21:31 +0100 Message-ID: <20260218082133.400602-15-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[14]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1771402988819158500 Content-Type: text/plain; charset="utf-8" In order to prepare for inlining RDMSR/WRMSR instructions via alternatives directly when running not in a Xen PV guest, switch the interfaces of the MSR related pvops callbacks to ones similar of the related instructions. In order to prepare for supporting the immediate variants of RDMSR/WRMSR use a 64-bit interface instead of the 32-bit one of RDMSR/WRMSR. Signed-off-by: Juergen Gross --- V3: - former patch 5 of V1 has been split - use 64-bit interface (Xin Li) --- arch/x86/include/asm/paravirt-msr.h | 49 ++++++++++++++++++++++++----- arch/x86/kernel/paravirt.c | 36 ++++++++++++++++++--- arch/x86/xen/enlighten_pv.c | 45 +++++++++++++++++++------- 3 files changed, 107 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/par= avirt-msr.h index b299864b438a..4ce690b05600 100644 --- a/arch/x86/include/asm/paravirt-msr.h +++ b/arch/x86/include/asm/paravirt-msr.h @@ -6,36 +6,69 @@ =20 struct pv_msr_ops { /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(u32 msr); - void (*write_msr)(u32 msr, u64 val); + struct paravirt_callee_save read_msr; + struct paravirt_callee_save write_msr; =20 /* Safe MSR operations. Returns 0 or -EIO. */ - int (*read_msr_safe)(u32 msr, u64 *val); - int (*write_msr_safe)(u32 msr, u64 val); + struct paravirt_callee_save read_msr_safe; + struct paravirt_callee_save write_msr_safe; =20 u64 (*read_pmc)(int counter); } __no_randomize_layout; =20 extern struct pv_msr_ops pv_ops_msr; =20 +#define PV_PROLOGUE_MSR(func) \ + PV_SAVE_COMMON_CALLER_REGS \ + PV_PROLOGUE_MSR_##func + +#define PV_EPILOGUE_MSR(func) PV_RESTORE_COMMON_CALLER_REGS + +#define PV_CALLEE_SAVE_REGS_MSR_THUNK(func) \ + __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", MSR) + static __always_inline u64 read_msr(u32 msr) { - return PVOP_CALL1(u64, pv_ops_msr, read_msr, msr); + u64 val; + + asm volatile(PARAVIRT_CALL + : "=3Da" (val), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, read_msr), "c" (msr) + : "rdx"); + + return val; } =20 static __always_inline void write_msr(u32 msr, u64 val) { - PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); + asm volatile(PARAVIRT_CALL + : ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, write_msr), "c" (msr), "a" (val) + : "memory", "rdx"); } =20 static __always_inline int read_msr_safe(u32 msr, u64 *val) { - return PVOP_CALL2(int, pv_ops_msr, read_msr_safe, msr, val); + int err; + + asm volatile(PARAVIRT_CALL + : [err] "=3Dd" (err), "=3Da" (*val), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, read_msr_safe), "c" (msr)); + + return err ? -EIO : 0; } =20 static __always_inline int write_msr_safe(u32 msr, u64 val) { - return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); + int err; + + asm volatile(PARAVIRT_CALL + : [err] "=3Da" (err), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, write_msr_safe), + "c" (msr), "a" (val) + : "memory", "rdx"); + + return err ? -EIO : 0; } =20 static __always_inline u64 rdpmc(int counter) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 089a87ac1582..c0d78e4536c9 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -49,12 +49,40 @@ unsigned long pv_native_save_fl(void); void pv_native_irq_disable(void); void pv_native_irq_enable(void); unsigned long pv_native_read_cr2(void); +void pv_native_rdmsr(void); +void pv_native_wrmsr(void); +void pv_native_rdmsr_safe(void); +void pv_native_wrmsr_safe(void); =20 DEFINE_ASM_FUNC(_paravirt_ident_64, "mov %rdi, %rax", .text); DEFINE_ASM_FUNC(pv_native_save_fl, "pushf; pop %rax", .noinstr.text); DEFINE_ASM_FUNC(pv_native_irq_disable, "cli", .noinstr.text); DEFINE_ASM_FUNC(pv_native_irq_enable, "sti", .noinstr.text); DEFINE_ASM_FUNC(pv_native_read_cr2, "mov %cr2, %rax", .noinstr.text); +DEFINE_ASM_FUNC(pv_native_rdmsr, + "1: rdmsr\n" + "shl $32, %rdx; or %rdx, %rax\n" + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR), .noinstr.text); +DEFINE_ASM_FUNC(pv_native_wrmsr, + "mov %rax, %rdx; shr $32, %rdx\n" + "1: wrmsr\n" + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR), .noinstr.text); +DEFINE_ASM_FUNC(pv_native_rdmsr_safe, + "1: rdmsr\n" + "shl $32, %rdx; or %rdx, %rax\n" + "xor %edx, %edx\n" + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %%edx), + .noinstr.text); +DEFINE_ASM_FUNC(pv_native_wrmsr_safe, + "mov %rax, %rdx; shr $32, %rdx\n" + "1: wrmsr\n" + "xor %eax, %eax\n" + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %%eax), + .noinstr.text); #endif =20 static noinstr void pv_native_safe_halt(void) @@ -211,10 +239,10 @@ struct paravirt_patch_template pv_ops =3D { =20 #ifdef CONFIG_PARAVIRT_XXL struct pv_msr_ops pv_ops_msr =3D { - .read_msr =3D native_read_msr, - .write_msr =3D native_write_msr, - .read_msr_safe =3D native_read_msr_safe, - .write_msr_safe =3D native_write_msr_safe, + .read_msr =3D __PV_IS_CALLEE_SAVE(pv_native_rdmsr), + .write_msr =3D __PV_IS_CALLEE_SAVE(pv_native_wrmsr), + .read_msr_safe =3D __PV_IS_CALLEE_SAVE(pv_native_rdmsr_safe), + .write_msr_safe =3D __PV_IS_CALLEE_SAVE(pv_native_wrmsr_safe), .read_pmc =3D native_read_pmc, }; EXPORT_SYMBOL(pv_ops_msr); diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index b94437f26cc0..fed312a17033 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1154,15 +1154,32 @@ static void xen_do_write_msr(u32 msr, u64 val, int = *err) } } =20 -static int xen_read_msr_safe(u32 msr, u64 *val) +/* + * Prototypes for functions called via PV_CALLEE_SAVE_REGS_THUNK() in order + * to avoid warnings with "-Wmissing-prototypes". + */ +struct xen_rdmsr_safe_ret { + u64 val; + int err; +}; +struct xen_rdmsr_safe_ret xen_read_msr_safe(u32 msr); +int xen_write_msr_safe(u32 msr, u64 val); +u64 xen_read_msr(u32 msr); +void xen_write_msr(u32 msr, u64 val); +#define PV_PROLOGUE_RDMSR "mov %ecx, %edi;" +#define PV_PROLOGUE_WRMSR "mov %ecx, %edi; mov %rax, %rsi;" + +__visible struct xen_rdmsr_safe_ret xen_read_msr_safe(u32 msr) { - int err =3D 0; + struct xen_rdmsr_safe_ret ret =3D { 0, 0 }; =20 - *val =3D xen_do_read_msr(msr, &err); - return err; + ret.val =3D xen_do_read_msr(msr, &ret.err); + return ret; } +#define PV_PROLOGUE_MSR_xen_read_msr_safe PV_PROLOGUE_RDMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_read_msr_safe); =20 -static int xen_write_msr_safe(u32 msr, u64 val) +__visible int xen_write_msr_safe(u32 msr, u64 val) { int err =3D 0; =20 @@ -1170,20 +1187,26 @@ static int xen_write_msr_safe(u32 msr, u64 val) =20 return err; } +#define PV_PROLOGUE_MSR_xen_write_msr_safe PV_PROLOGUE_WRMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_write_msr_safe); =20 -static u64 xen_read_msr(u32 msr) +__visible u64 xen_read_msr(u32 msr) { int err =3D 0; =20 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); } +#define PV_PROLOGUE_MSR_xen_read_msr PV_PROLOGUE_RDMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_read_msr); =20 -static void xen_write_msr(u32 msr, u64 val) +__visible void xen_write_msr(u32 msr, u64 val) { int err; =20 xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL); } +#define PV_PROLOGUE_MSR_xen_write_msr PV_PROLOGUE_WRMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_write_msr); =20 /* This is called once we have the cpu_possible_mask */ void __init xen_setup_vcpu_info_placement(void) @@ -1386,10 +1409,10 @@ asmlinkage __visible void __init xen_start_kernel(s= truct start_info *si) pv_ops.cpu.start_context_switch =3D xen_start_context_switch; pv_ops.cpu.end_context_switch =3D xen_end_context_switch; =20 - pv_ops_msr.read_msr =3D xen_read_msr; - pv_ops_msr.write_msr =3D xen_write_msr; - pv_ops_msr.read_msr_safe =3D xen_read_msr_safe; - pv_ops_msr.write_msr_safe =3D xen_write_msr_safe; + pv_ops_msr.read_msr =3D PV_CALLEE_SAVE(xen_read_msr); + pv_ops_msr.write_msr =3D PV_CALLEE_SAVE(xen_write_msr); + pv_ops_msr.read_msr_safe =3D PV_CALLEE_SAVE(xen_read_msr_safe); + pv_ops_msr.write_msr_safe =3D PV_CALLEE_SAVE(xen_write_msr_safe); pv_ops_msr.read_pmc =3D xen_read_pmc; =20 xen_init_irq_ops(); --=20 2.53.0 From nobody Fri Apr 3 04:33:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771402998279784.6558049930558; Wed, 18 Feb 2026 00:23:18 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1235333.1538325 (Exim 4.92) (envelope-from ) id 1vscps-0001gm-Dt; Wed, 18 Feb 2026 08:23:04 +0000 Received: by outflank-mailman (output) from mailman id 1235333.1538325; Wed, 18 Feb 2026 08:23:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vscps-0001ge-AO; Wed, 18 Feb 2026 08:23:04 +0000 Received: by outflank-mailman (input) for mailman id 1235333; Wed, 18 Feb 2026 08:23:02 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vscpq-0001cj-Pa for xen-devel@lists.xenproject.org; Wed, 18 Feb 2026 08:23:02 +0000 Received: from smtp-out1.suse.de (smtp-out1.suse.de [2a07:de40:b251:101:10:150:64:1]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 098ffe0e-0ca3-11f1-9ccf-f158ae23cfc8; Wed, 18 Feb 2026 09:23:00 +0100 (CET) Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 59ECA3E6F0; Wed, 18 Feb 2026 08:23:00 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 109203EA65; Wed, 18 Feb 2026 08:23:00 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id FfbiAuR2lWlFHwAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:23:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 098ffe0e-0ca3-11f1-9ccf-f158ae23cfc8 Authentication-Results: smtp-out1.suse.de; none From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v3 15/16] x86/msr: Reduce number of low level MSR access helpers Date: Wed, 18 Feb 2026 09:21:32 +0100 Message-ID: <20260218082133.400602-16-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 59ECA3E6F0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-ZM-MESSAGEID: 1771403001085154100 Content-Type: text/plain; charset="utf-8" Some MSR access helpers are redundant now, so remove the no longer needed ones. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 15 ++------------- arch/x86/xen/enlighten_pv.c | 4 ++-- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 66f57265f2f8..84e82c0bb9b1 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -272,22 +272,11 @@ static __always_inline void native_wrmsr(u32 msr, u32= low, u32 high) native_wrmsrq(msr, (u64)high << 32 | low); } =20 -static inline u64 native_read_msr(u32 msr) -{ - return native_rdmsrq(msr); -} - static inline int native_read_msr_safe(u32 msr, u64 *val) { return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; } =20 -/* Can be uninlined because referenced by paravirt */ -static inline void notrace native_write_msr(u32 msr, u64 val) -{ - native_wrmsrq(msr, val); -} - /* Can be uninlined because referenced by paravirt */ static inline int notrace native_write_msr_safe(u32 msr, u64 val) { @@ -312,7 +301,7 @@ static inline u64 native_read_pmc(int counter) #else static __always_inline u64 read_msr(u32 msr) { - return native_read_msr(msr); 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Wed, 18 Feb 2026 08:23:05 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id B81EJel2lWlLHwAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:23:05 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v3 16/16] x86/paravirt: Use alternatives for MSR access with paravirt Date: Wed, 18 Feb 2026 09:21:33 +0100 Message-ID: <20260218082133.400602-17-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[12]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; URIBL_BLOCKED(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spam-Level: Content-Type: text/plain; charset="utf-8" When not running as Xen PV guest, patch in the optimal MSR instructions via alternative and use direct calls otherwise. This will especially have positive effects for performance when not running as a Xen PV guest with paravirtualization enabled, as there will be no call overhead for MSR access functions any longer. Signed-off-by: Juergen Gross --- V3: - new patch --- arch/x86/include/asm/paravirt-msr.h | 101 ++++++++++++++++++++++---- arch/x86/include/asm/paravirt_types.h | 1 + 2 files changed, 86 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/par= avirt-msr.h index 4ce690b05600..122a7525ae17 100644 --- a/arch/x86/include/asm/paravirt-msr.h +++ b/arch/x86/include/asm/paravirt-msr.h @@ -27,33 +27,103 @@ extern struct pv_msr_ops pv_ops_msr; #define PV_CALLEE_SAVE_REGS_MSR_THUNK(func) \ __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", MSR) =20 +#define ASM_CLRERR "xor %[err],%[err]\n" + +#define PV_RDMSR_VAR(__msr, __val, __type, __func, __err) \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_2(PARAVIRT_CALL, \ + RDMSR_AND_SAVE_RESULT ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Dd" (__err), [val] "=3Da" (__val), \ + ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), "c" (__msr) \ + : "cc") + +#define PV_RDMSR_CONST(__msr, __val, __type, __func, __err) \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_3(PARAVIRT_CALL, \ + RDMSR_AND_SAVE_RESULT ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ASM_RDMSR_IMM ASM_CLRERR, X86_FEATURE_MSR_IMM, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Dd" (__err), [val] "=3Da" (__val), \ + ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + "c" (__msr), [msr] "i" (__msr) \ + : "cc") + +#define PV_WRMSR_VAR(__msr, __val, __type, __func, __err) \ +({ \ + unsigned long rdx =3D rdx; \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_3(PARAVIRT_CALL, \ + "wrmsr;" ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ASM_WRMSRNS ASM_CLRERR, X86_FEATURE_WRMSRNS, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Da" (__err), "=3Dd" (rdx), ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + "0" (__val), "1" ((__val) >> 32), "c" (__msr) \ + : "memory", "cc"); \ +}) + +#define PV_WRMSR_CONST(__msr, __val, __type, __func, __err) \ +({ \ + unsigned long rdx =3D rdx; \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_4(PARAVIRT_CALL, \ + "wrmsr;" ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ASM_WRMSRNS ASM_CLRERR, X86_FEATURE_WRMSRNS, \ + ASM_WRMSRNS_IMM ASM_CLRERR, X86_FEATURE_MSR_IMM,\ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Da" (__err), "=3Dd" (rdx), ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + [val] "0" (__val), "1" ((__val) >> 32), \ + "c" (__msr), [msr] "i" (__msr) \ + : "memory", "cc"); \ +}) + static __always_inline u64 read_msr(u32 msr) { u64 val; + int err; =20 - asm volatile(PARAVIRT_CALL - : "=3Da" (val), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, read_msr), "c" (msr) - : "rdx"); + if (__builtin_constant_p(msr)) + PV_RDMSR_CONST(msr, val, EX_TYPE_RDMSR, read_msr, err); + else + PV_RDMSR_VAR(msr, val, EX_TYPE_RDMSR, read_msr, err); =20 return val; } =20 static __always_inline void write_msr(u32 msr, u64 val) { - asm volatile(PARAVIRT_CALL - : ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, write_msr), "c" (msr), "a" (val) - : "memory", "rdx"); + int err; + + if (__builtin_constant_p(msr)) + PV_WRMSR_CONST(msr, val, EX_TYPE_WRMSR, write_msr, err); + else + PV_WRMSR_VAR(msr, val, EX_TYPE_WRMSR, write_msr, err); } =20 static __always_inline int read_msr_safe(u32 msr, u64 *val) { int err; =20 - asm volatile(PARAVIRT_CALL - : [err] "=3Dd" (err), "=3Da" (*val), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, read_msr_safe), "c" (msr)); + if (__builtin_constant_p(msr)) + PV_RDMSR_CONST(msr, *val, EX_TYPE_RDMSR_SAFE, read_msr_safe, err); + else + PV_RDMSR_VAR(msr, *val, EX_TYPE_RDMSR_SAFE, read_msr_safe, err); =20 return err ? -EIO : 0; } @@ -62,11 +132,10 @@ static __always_inline int write_msr_safe(u32 msr, u64= val) { int err; =20 - asm volatile(PARAVIRT_CALL - : [err] "=3Da" (err), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, write_msr_safe), - "c" (msr), "a" (val) - : "memory", "rdx"); + if (__builtin_constant_p(msr)) + PV_WRMSR_CONST(msr, val, EX_TYPE_WRMSR_SAFE, write_msr_safe, err); + else + PV_WRMSR_VAR(msr, val, EX_TYPE_WRMSR_SAFE, write_msr_safe, err); =20 return err ? -EIO : 0; } diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index 999a5abe54ed..bdaecc54c6ee 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -451,6 +451,7 @@ extern struct paravirt_patch_template pv_ops; #endif /* __ASSEMBLER__ */ =20 #define ALT_NOT_XEN ALT_NOT(X86_FEATURE_XENPV) +#define ALT_XEN_CALL ALT_DIRECT_CALL(X86_FEATURE_XENPV) =20 #ifdef CONFIG_X86_32 /* save and restore all caller-save registers, except return value */ --=20 2.53.0