From nobody Sun Apr 5 16:31:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8804B309EEC; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; cv=none; b=iIWbxcEAZX8cigY/M5nimiqWapXY45T8xTt1ypZd8/tPXFGm5y0ArGV4Z9jbqIXboGeZoCt+DZ8K18VADudVCSewfJtX+F8L32YhN24UgUy/lRsZBn624KSl6lb63/jcCA+K7yKsI0YT4g2Z9ctQZYOPursxqBW5/dAFNYUBiSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; c=relaxed/simple; bh=G4D4eRDmZ3zLHtlTCwr9vTCHs+6N4+BLBkJbK4k9c60=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HBCGOuiFos+TCgh/VvxLqMhz/Qy3VbceZ7WP/ShGsvIiDABzDXdp5af5hwhx8MPqud4AktnYpDIpAiFzIYn22wq/diR0L2GogTxttnG8UtjOW06DSVppx7w1OhSNSDFf8/rymNJFCbgFk9DcuKx7kXY2aHTa4+JVQcXlF88XLk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zl3KfNDD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zl3KfNDD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 44957C19422; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771438581; bh=G4D4eRDmZ3zLHtlTCwr9vTCHs+6N4+BLBkJbK4k9c60=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Zl3KfNDDB05MFHoPcXpiHwFUE6yAa3bnGJLRaSnJKVd9/ikGw7tWJ3WpvanB8k12K o3sJ/hvRFymmbE7v1M3ocOGGDHZDoN5WwAL8afVkqTdq163PZ4JHQuRe2h0Fuwenw5 ojnI1hdpswe90xfgwnKqbH5NuwD/i5CQxzu1MC1KxJAKMCjosqtEsoORq59VSvpGhm Io/yVyXu5BOYLv/IsKQKDY+JHZn0HQfIrLWCXww6MptqNCwlwHg1oy7EQye6B3B09g oJTDMKEguLqVGcSNz1tlgJp4PJ6T6GPwt9lNp7GCddjFsqFOrhfO6VEt77lJfdgjrA D/wX3RDb2Jx9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B28E9A04A; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 18 Feb 2026 12:16:19 -0600 Subject: [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260218-sm8550-ddr-bw-scaling-v2-2-43a2b6d47e70@gmail.com> References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771438580; l=5920; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=nk9umh4fIRgNVJ6t2hcRpym0E82gtFPD4gJGRGEKYHg=; b=NjfB+RLobCH+wF7j8pY/opYwu72NwoTx17WwnloJp7L4GXxbDxuQ3/jsWDJ8hRM7O6du4eJlK I7nhOyjxF/AA1pHCN867VGSvUoYwD3YMVgBzGspthBJT+aF157uxFLc X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the OSC L3 Cache controller node. Also add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 59 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..e6cb8bf40f9f8ed6d02db124056= c5814af32fa08 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,12 @@ cpu0: cpu@0 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_0: l2-cache { compatible =3D "cache"; @@ -104,6 +111,12 @@ cpu1: cpu@100 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_100: l2-cache { compatible =3D "cache"; @@ -125,6 +138,12 @@ cpu2: cpu@200 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_200: l2-cache { compatible =3D "cache"; @@ -146,6 +165,12 @@ cpu3: cpu@300 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_300: l2-cache { compatible =3D "cache"; @@ -167,6 +192,12 @@ cpu4: cpu@400 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_400: l2-cache { compatible =3D "cache"; @@ -188,6 +219,12 @@ cpu5: cpu@500 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_500: l2-cache { compatible =3D "cache"; @@ -209,6 +246,12 @@ cpu6: cpu@600 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_600: l2-cache { compatible =3D "cache"; @@ -230,6 +273,12 @@ cpu7: cpu@700 { qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_700: l2-cache { compatible =3D "cache"; @@ -5437,6 +5486,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; =20 + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,sm8550-epss-l3", "qcom,epss-l3"; + reg =3D <0 0x17d90000 0 0x1000>; + + clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg =3D <0 0x17d91000 0 0x1000>, --=20 2.52.0