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The MSM8960 platform shares the same RPM clock definitions as APQ8064, so extend the existing conditional schema to treat qcom,rpmcc-msm8960 the same as qcom,rpmcc-apq8064. Signed-off-by: Antony Kurniawan Soemardi --- Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Docu= mentation/devicetree/bindings/clock/qcom,rpmcc.yaml index ab97d4b7dba8bc8d38903b399d2bd4bda087db8a..f84d08199e47f45ecb176d350ee= b7df8c3ff506b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -36,6 +36,7 @@ properties: - qcom,rpmcc-msm8937 - qcom,rpmcc-msm8940 - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8960 - qcom,rpmcc-msm8974 - qcom,rpmcc-msm8976 - qcom,rpmcc-msm8992 @@ -90,7 +91,9 @@ allOf: properties: compatible: contains: - const: qcom,rpmcc-apq8064 + enum: + - qcom,rpmcc-apq8064 + - qcom,rpmcc-msm8960 then: properties: clocks: --=20 2.34.1 From nobody Fri Apr 17 14:59:27 2026 Received: from dormouse.ash.relay.mailchannels.net (dormouse.ash.relay.mailchannels.net [23.83.222.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4DFC2848BB; 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pk=65wTy06fJl2/h/EJwjr704YG+yjHFhZObJBWzzK+N00= Date: Wed, 18 Feb 2026 06:59:08 +0000 (UTC) X-CM-Analysis: v=2.4 cv=GMJaEfNK c=1 sm=1 tr=0 ts=6995633f a=QVpbo7x4j/ax8PIbKattOw==:117 a=QVpbo7x4j/ax8PIbKattOw==:17 a=IkcTkHD0fZMA:10 a=wxLWbCv9AAAA:8 a=Gjla_oY5Z_Fy-GYXBTcA:9 a=QEXdDO2ut3YA:10 a=QJY96suAAestDpCc5Gi9:22 X-CM-Envelope: MS4xfBW7MvezkzdNDYgaPmkHEKwVlhXyiWFRef1AjUlhGEuz/PNKZoeOhgrqWk44JyHrH/oW0g6ZBgKMrxRTeQz8wzPMTfd9orWYUS8cwU+4uwTIznrxVdxH QZXKzXa8FVTP+MuBW4XMkDUX9q9IDWMjetYV9VZNT2Kdl0RAaL/tIYzmnJZ/BtycsI1Cd0taGC1vOZYmFUcKMAjf6236aoOFQvPcx7vZ7K+9xexNDfV8lxfm gp7OzRKWFucO6w6UysD+HFKuKIC9ZkFWX5MtO5Uz352lCsotFgBM783JShd6PlgGoyZch4/fQntt/g1E9iXwcYaWrPOk/AwJ50BUhZJIwQp5PxfaCBe5hkn4 tgO8dioBFQEjk8NJuX5SBy4y89YreZvhSpqdGBlflW4pbSrkhqayWzjeo0r+yDNwE9x+riNMzS5YaAKSWdsHR7/e8nGRH8TNwB/irWhVkhAOC/TB5JZS39PT ZTPyt4xBzsTaLiLaDznKvemwslA90JyoMAJpP3D1t2RYNzeFvTd7WJTR6aWtYFnVSzxW6GyRP5y4IeQmtlR6Y5yX6lD/el554FZAtYF98jcC3BmwdojA+dUu zZY/r2g0cMn9U4ZgTrju7BLH/hbEEFjBaxhTO9AULC1Tow== X-AuthUser: linux@smankusors.com Add compat for Smart Peripheral System (SPS) Interrupt Controller (SIC) present on Qualcomm MSM8960 SoC. Signed-off-by: Antony Kurniawan Soemardi --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index e57add2bacd30b0582e037ae69dd9f2b55d13066..39a24c3ff9cfb543d46ef30a21e= dbd074e22a0de 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -106,6 +106,7 @@ select: - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic + - qcom,msm8960-sps-sic - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos @@ -219,6 +220,7 @@ properties: - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic + - qcom,msm8960-sps-sic - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos --=20 2.34.1