From nobody Sun Apr 5 13:04:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE0412F90DB; Tue, 17 Feb 2026 21:44:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771364684; cv=none; b=PYZIm41D5/Hr5b2l64EtdVqmhIN8AAcX4bF0RQpcucBEg1k9x3RkVh3tNn9ExylrGwDQ96fL8V2S3L5QnFvG70tziwIYz6fm8n4YXxfE4x0V/57IlJ+SDjO2qvEqZzYdkCK3oF//mPR8vIkrlpTMv7AjLTHNq9xChdE+rCz/p4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771364684; c=relaxed/simple; bh=llZUjlDMs25pO5tBk7X48ivlpnyYwNP0g+Z4tYEfbN4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CUjRPRLRpbdwwe+pmL69U+C1ztS0Bk+eYQnyWfSnICHvSQZXtvcN7kuz11DVFTiyqmJqU59S+5YIrguD84/pgPO0E+GizA0salHjnVdC2AHcphV2XOzDHP1UHZiMaXLOU2FUkwNc+V1clhIQfGh5Fca/thGlGClp2BW136nDEG8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bIPsKrdj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bIPsKrdj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F124C4CEF7; Tue, 17 Feb 2026 21:44:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771364684; bh=llZUjlDMs25pO5tBk7X48ivlpnyYwNP0g+Z4tYEfbN4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bIPsKrdjMM58zDt2bRZdcQYmAqDCDUeAcAcW+F2TmBN98HikhDDQ7IY+l9zsKQ7TT LhSYgqJQfEvjiNFurjb/Jh4qu8OmUiOZfV6dKSktQleoijUxCqINYnlczqq+9jOzHS seRHmmOYNrVsbjCYRDdyu13d5f46/i1FMEW9JM+kWjtfRChEGcszTpokqcGbzFjg4W j6O85nCgcRsgDpBXHe/wNhvZcU6mTWlb8tz8M/qR8MsY5XPACxN2rLmF8sP/vhinKk YvYpzNP8qK9gh5+qNGV7iX6u8stoSsyaj40s6UczlNe+Om7m1h29sNmht4c1XOa1NT DO0zevMKtHuaA== From: Bjorn Helgaas To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon Cc: Robin Murphy , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v1 1/2] iommu/vt-d: Remove dmar_readl() and dmar_readq() Date: Tue, 17 Feb 2026 15:44:37 -0600 Message-ID: <20260217214438.3395039-2-bhelgaas@google.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260217214438.3395039-1-bhelgaas@google.com> References: <20260217214438.3395039-1-bhelgaas@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" dmar_readl() and dmar_readq() do nothing other than expand to the generic readl() and readq(), and the dmar_read*() wrappers are used inconsistently. Remove the dmar_read*() wrappers and use readl() and readq() directly. Signed-off-by: Bjorn Helgaas Reviewed-by: Samiullah Khawaja --- drivers/iommu/intel/debugfs.c | 18 +++++++++--------- drivers/iommu/intel/dmar.c | 22 +++++++++++----------- drivers/iommu/intel/iommu.c | 10 +++++----- drivers/iommu/intel/iommu.h | 2 -- drivers/iommu/intel/irq_remapping.c | 2 +- drivers/iommu/intel/perfmon.c | 28 ++++++++++++++-------------- drivers/iommu/intel/prq.c | 12 ++++++------ 7 files changed, 46 insertions(+), 48 deletions(-) diff --git a/drivers/iommu/intel/debugfs.c b/drivers/iommu/intel/debugfs.c index 617fd81a80f0..21e4e465ca58 100644 --- a/drivers/iommu/intel/debugfs.c +++ b/drivers/iommu/intel/debugfs.c @@ -133,13 +133,13 @@ static int iommu_regset_show(struct seq_file *m, void= *unused) */ raw_spin_lock_irqsave(&iommu->register_lock, flag); for (i =3D 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) { - value =3D dmar_readl(iommu->reg + iommu_regs_32[i].offset); + value =3D readl(iommu->reg + iommu_regs_32[i].offset); seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", iommu_regs_32[i].regs, iommu_regs_32[i].offset, value); } for (i =3D 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) { - value =3D dmar_readq(iommu->reg + iommu_regs_64[i].offset); + value =3D readq(iommu->reg + iommu_regs_64[i].offset); seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", iommu_regs_64[i].regs, iommu_regs_64[i].offset, value); @@ -247,7 +247,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct int= el_iommu *iommu, u16 bus) tbl_wlk.ctx_entry =3D context; m->private =3D &tbl_wlk; =20 - if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { + if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { pasid_dir_ptr =3D context->lo & VTD_PAGE_MASK; pasid_dir_size =3D get_pasid_dir_size(context); pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size); @@ -285,7 +285,7 @@ static int dmar_translation_struct_show(struct seq_file= *m, void *unused) =20 rcu_read_lock(); for_each_active_iommu(iommu, drhd) { - sts =3D dmar_readl(iommu->reg + DMAR_GSTS_REG); + sts =3D readl(iommu->reg + DMAR_GSTS_REG); if (!(sts & DMA_GSTS_TES)) { seq_printf(m, "DMA Remapping is not enabled on %s\n", iommu->name); @@ -364,13 +364,13 @@ static int domain_translation_struct_show(struct seq_= file *m, if (seg !=3D iommu->segment) continue; =20 - sts =3D dmar_readl(iommu->reg + DMAR_GSTS_REG); + sts =3D readl(iommu->reg + DMAR_GSTS_REG); if (!(sts & DMA_GSTS_TES)) { seq_printf(m, "DMA Remapping is not enabled on %s\n", iommu->name); continue; } - if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) + if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) scalable =3D true; else scalable =3D false; @@ -538,8 +538,8 @@ static int invalidation_queue_show(struct seq_file *m, = void *unused) raw_spin_lock_irqsave(&qi->q_lock, flags); seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n", (u64)virt_to_phys(qi->desc), - dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, - dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); + readq(iommu->reg + DMAR_IQH_REG) >> shift, + readq(iommu->reg + DMAR_IQT_REG) >> shift); invalidation_queue_entry_show(m, iommu); raw_spin_unlock_irqrestore(&qi->q_lock, flags); seq_putc(m, '\n'); @@ -620,7 +620,7 @@ static int ir_translation_struct_show(struct seq_file *= m, void *unused) seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", iommu->name); =20 - sts =3D dmar_readl(iommu->reg + DMAR_GSTS_REG); + sts =3D readl(iommu->reg + DMAR_GSTS_REG); if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { irta =3D virt_to_phys(iommu->ir_table->base); seq_printf(m, " IR table address:%llx\n", irta); diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index ec975c73cfe6..96d9878b9eb6 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -899,8 +899,8 @@ dmar_validate_one_drhd(struct acpi_dmar_header *entry, = void *arg) return -EINVAL; } =20 - cap =3D dmar_readq(addr + DMAR_CAP_REG); - ecap =3D dmar_readq(addr + DMAR_ECAP_REG); + cap =3D readq(addr + DMAR_CAP_REG); + ecap =3D readq(addr + DMAR_ECAP_REG); =20 if (arg) iounmap(addr); @@ -982,8 +982,8 @@ static int map_iommu(struct intel_iommu *iommu, struct = dmar_drhd_unit *drhd) goto release; } =20 - iommu->cap =3D dmar_readq(iommu->reg + DMAR_CAP_REG); - iommu->ecap =3D dmar_readq(iommu->reg + DMAR_ECAP_REG); + iommu->cap =3D readq(iommu->reg + DMAR_CAP_REG); + iommu->ecap =3D readq(iommu->reg + DMAR_ECAP_REG); =20 if (iommu->cap =3D=3D (uint64_t)-1 && iommu->ecap =3D=3D (uint64_t)-1) { err =3D -EINVAL; @@ -1017,8 +1017,8 @@ static int map_iommu(struct intel_iommu *iommu, struc= t dmar_drhd_unit *drhd) int i; =20 for (i =3D 0; i < DMA_MAX_NUM_ECMDCAP; i++) { - iommu->ecmdcap[i] =3D dmar_readq(iommu->reg + DMAR_ECCAP_REG + - i * DMA_ECMD_REG_STEP); + iommu->ecmdcap[i] =3D readq(iommu->reg + DMAR_ECCAP_REG + + i * DMA_ECMD_REG_STEP); } } =20 @@ -1239,8 +1239,8 @@ static const char *qi_type_string(u8 type) =20 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault) { - unsigned int head =3D dmar_readl(iommu->reg + DMAR_IQH_REG); - u64 iqe_err =3D dmar_readq(iommu->reg + DMAR_IQER_REG); + unsigned int head =3D readl(iommu->reg + DMAR_IQH_REG); + u64 iqe_err =3D readq(iommu->reg + DMAR_IQER_REG); struct qi_desc *desc =3D iommu->qi->desc + head; =20 if (fault & DMA_FSTS_IQE) @@ -1322,7 +1322,7 @@ static int qi_check_fault(struct intel_iommu *iommu, = int index, int wait_index) * SID field is valid only when the ITE field is Set in FSTS_REG * see Intel VT-d spec r4.1, section 11.4.9.9 */ - iqe_err =3D dmar_readq(iommu->reg + DMAR_IQER_REG); + iqe_err =3D readq(iommu->reg + DMAR_IQER_REG); ite_sid =3D DMAR_IQER_REG_ITESID(iqe_err); =20 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); @@ -1981,8 +1981,8 @@ irqreturn_t dmar_fault(int irq, void *dev_id) source_id =3D dma_frcd_source_id(data); =20 pasid_present =3D dma_frcd_pasid_present(data); - guest_addr =3D dmar_readq(iommu->reg + reg + - fault_index * PRIMARY_FAULT_REG_LEN); + guest_addr =3D readq(iommu->reg + reg + + fault_index * PRIMARY_FAULT_REG_LEN); guest_addr =3D dma_frcd_page_addr(guest_addr); } =20 diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 705828b06e32..64284938e1ce 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -769,7 +769,7 @@ static void __iommu_flush_context(struct intel_iommu *i= ommu, =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, - dmar_readq, (!(val & DMA_CCMD_ICC)), val); + readq, (!(val & DMA_CCMD_ICC)), val); =20 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } @@ -811,7 +811,7 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16= did, u64 addr, =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, tlb_offset + 8, - dmar_readq, (!(val & DMA_TLB_IVT)), val); + readq, (!(val & DMA_TLB_IVT)), val); =20 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); =20 @@ -1533,7 +1533,7 @@ static int copy_translation_tables(struct intel_iommu= *iommu) int bus, ret; bool new_ext, ext; =20 - rtaddr_reg =3D dmar_readq(iommu->reg + DMAR_RTADDR_REG); + rtaddr_reg =3D readq(iommu->reg + DMAR_RTADDR_REG); ext =3D !!(rtaddr_reg & DMA_RTADDR_SMT); new_ext =3D !!sm_supported(iommu); =20 @@ -4185,7 +4185,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ec= md, u64 oa, u64 ob) =20 raw_spin_lock_irqsave(&iommu->register_lock, flags); =20 - res =3D dmar_readq(iommu->reg + DMAR_ECRSP_REG); + res =3D readq(iommu->reg + DMAR_ECRSP_REG); if (res & DMA_ECMD_ECRSP_IP) { ret =3D -EBUSY; goto err; @@ -4201,7 +4201,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ec= md, u64 oa, u64 ob) dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); =20 - IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq, + IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq, !(res & DMA_ECMD_ECRSP_IP), res); =20 if (res & DMA_ECMD_ECRSP_IP) { diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 599913fb65d5..dbd8d196d154 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -148,9 +148,7 @@ =20 #define OFFSET_STRIDE (9) =20 -#define dmar_readq(a) readq(a) #define dmar_writeq(a,v) writeq(v,a) -#define dmar_readl(a) readl(a) #define dmar_writel(a, v) writel(v, a) =20 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index ecb591e98565..3fce6efea524 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -422,7 +422,7 @@ static int iommu_load_old_irte(struct intel_iommu *iomm= u) u64 irta; =20 /* Check whether the old ir-table has the same size as ours */ - irta =3D dmar_readq(iommu->reg + DMAR_IRTA_REG); + irta =3D readq(iommu->reg + DMAR_IRTA_REG); if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) !=3D INTR_REMAP_TABLE_REG_SIZE) return -EINVAL; diff --git a/drivers/iommu/intel/perfmon.c b/drivers/iommu/intel/perfmon.c index 75f493bcb353..30bd684612ad 100644 --- a/drivers/iommu/intel/perfmon.c +++ b/drivers/iommu/intel/perfmon.c @@ -307,7 +307,7 @@ static void iommu_pmu_event_update(struct perf_event *e= vent) =20 again: prev_count =3D local64_read(&hwc->prev_count); - new_count =3D dmar_readq(iommu_event_base(iommu_pmu, hwc->idx)); + new_count =3D readq(iommu_event_base(iommu_pmu, hwc->idx)); if (local64_xchg(&hwc->prev_count, new_count) !=3D prev_count) goto again; =20 @@ -340,7 +340,7 @@ static void iommu_pmu_start(struct perf_event *event, i= nt flags) hwc->state =3D 0; =20 /* Always reprogram the period */ - count =3D dmar_readq(iommu_event_base(iommu_pmu, hwc->idx)); + count =3D readq(iommu_event_base(iommu_pmu, hwc->idx)); local64_set((&hwc->prev_count), count); =20 /* @@ -496,7 +496,7 @@ static void iommu_pmu_counter_overflow(struct iommu_pmu= *iommu_pmu) * Two counters may be overflowed very close. Always check * whether there are more to handle. */ - while ((status =3D dmar_readq(iommu_pmu->overflow))) { + while ((status =3D readq(iommu_pmu->overflow))) { for_each_set_bit(i, (unsigned long *)&status, iommu_pmu->num_cntr) { /* * Find the assigned event of the counter. @@ -518,7 +518,7 @@ static irqreturn_t iommu_pmu_irq_handler(int irq, void = *dev_id) { struct intel_iommu *iommu =3D dev_id; =20 - if (!dmar_readl(iommu->reg + DMAR_PERFINTRSTS_REG)) + if (!readl(iommu->reg + DMAR_PERFINTRSTS_REG)) return IRQ_NONE; =20 iommu_pmu_counter_overflow(iommu->pmu); @@ -555,7 +555,7 @@ static int __iommu_pmu_register(struct intel_iommu *iom= mu) static inline void __iomem * get_perf_reg_address(struct intel_iommu *iommu, u32 offset) { - u32 off =3D dmar_readl(iommu->reg + offset); + u32 off =3D readl(iommu->reg + offset); =20 return iommu->reg + off; } @@ -574,7 +574,7 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) if (!cap_ecmds(iommu->cap)) return -ENODEV; =20 - perfcap =3D dmar_readq(iommu->reg + DMAR_PERFCAP_REG); + perfcap =3D readq(iommu->reg + DMAR_PERFCAP_REG); /* The performance monitoring is not supported. */ if (!perfcap) return -ENODEV; @@ -617,8 +617,8 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) for (i =3D 0; i < iommu_pmu->num_eg; i++) { u64 pcap; =20 - pcap =3D dmar_readq(iommu->reg + DMAR_PERFEVNTCAP_REG + - i * IOMMU_PMU_CAP_REGS_STEP); + pcap =3D readq(iommu->reg + DMAR_PERFEVNTCAP_REG + + i * IOMMU_PMU_CAP_REGS_STEP); iommu_pmu->evcap[i] =3D pecap_es(pcap); } =20 @@ -651,9 +651,9 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) * Width. */ for (i =3D 0; i < iommu_pmu->num_cntr; i++) { - cap =3D dmar_readl(iommu_pmu->cfg_reg + - i * IOMMU_PMU_CFG_OFFSET + - IOMMU_PMU_CFG_CNTRCAP_OFFSET); + cap =3D readl(iommu_pmu->cfg_reg + + i * IOMMU_PMU_CFG_OFFSET + + IOMMU_PMU_CFG_CNTRCAP_OFFSET); if (!iommu_cntrcap_pcc(cap)) continue; =20 @@ -675,9 +675,9 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) =20 /* Override with per-counter event capabilities */ for (j =3D 0; j < iommu_cntrcap_egcnt(cap); j++) { - cap =3D dmar_readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET + - IOMMU_PMU_CFG_CNTREVCAP_OFFSET + - (j * IOMMU_PMU_OFF_REGS_STEP)); + cap =3D readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET + + IOMMU_PMU_CFG_CNTREVCAP_OFFSET + + (j * IOMMU_PMU_OFF_REGS_STEP)); iommu_pmu->cntr_evcap[i][iommu_event_group(cap)] =3D iommu_event_select= (cap); /* * Some events may only be supported by a specific counter. diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c index ff63c228e6e1..c28fbd5c14a7 100644 --- a/drivers/iommu/intel/prq.c +++ b/drivers/iommu/intel/prq.c @@ -81,8 +81,8 @@ void intel_iommu_drain_pasid_prq(struct device *dev, u32 = pasid) */ prq_retry: reinit_completion(&iommu->prq_complete); - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; while (head !=3D tail) { struct page_req_dsc *req; =20 @@ -208,8 +208,8 @@ static irqreturn_t prq_event_thread(int irq, void *d) */ writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG); =20 - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; handled =3D (head !=3D tail); while (head !=3D tail) { req =3D &iommu->prq[head / sizeof(*req)]; @@ -268,8 +268,8 @@ static irqreturn_t prq_event_thread(int irq, void *d) if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) { pr_info_ratelimited("IOMMU: %s: PRQ overflow detected\n", iommu->name); - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; if (head =3D=3D tail) { iopf_queue_discard_partial(iommu->iopf_queue); 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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mZWXgH8f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mZWXgH8f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0A21C4CEF7; Tue, 17 Feb 2026 21:44:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771364685; bh=4yTaEXfbRHgMUg/EPCb/UmCBX1c5hSX7ilmhvdL8UrA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mZWXgH8f0cfyyBf7AGzr5A10XexziIiLwycqNYQbYqM6L1yIMNBkV/b8HpfFGyIMO Wh3QZpKApOcSHaA0yGvXNdy+AooT4xJNLP0dT0+qr1K7TsWzuwx93GKYqrP0qMU1t5 vUYbOLc9pw543wGgaumfL9yWzd0sj5j1C1QKI/xJwEwQL8Wu2rIxO5KlzBvOJe9PmM vBf0ePdWRnsFtWXe2C9e7aDXvMSBXFbK71kJ1W1FGXyjCq7BBS7W7ta5LjyzRj0ZTt fX62ocZwUBaOZWN0wf4WpeAFdiHkoxCXjHQOVeJF0ZBce516NBDspvduHzSfYqOsVI WULipiHcSFc+A== From: Bjorn Helgaas To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon Cc: Robin Murphy , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v1 2/2] iommu/vt-d: Remove dmar_writel() and dmar_writeq() Date: Tue, 17 Feb 2026 15:44:38 -0600 Message-ID: <20260217214438.3395039-3-bhelgaas@google.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260217214438.3395039-1-bhelgaas@google.com> References: <20260217214438.3395039-1-bhelgaas@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" dmar_writel() and dmar_writeq() do nothing other than expand to the generic writel() and writeq(), and the dmar_write*() wrappers are used inconsistently. Remove the dmar_write*() wrappers and use writel() and writeq() directly. Signed-off-by: Bjorn Helgaas Reviewed-by: Samiullah Khawaja --- drivers/iommu/intel/dmar.c | 2 +- drivers/iommu/intel/iommu.c | 12 ++++++------ drivers/iommu/intel/iommu.h | 3 --- drivers/iommu/intel/irq_remapping.c | 4 ++-- drivers/iommu/intel/perfmon.c | 22 +++++++++++----------- drivers/iommu/intel/prq.c | 14 +++++++------- 6 files changed, 27 insertions(+), 30 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 96d9878b9eb6..44d8361d2480 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1662,7 +1662,7 @@ static void __dmar_enable_qi(struct intel_iommu *iomm= u) /* write zero to the tail reg */ writel(0, iommu->reg + DMAR_IQT_REG); =20 - dmar_writeq(iommu->reg + DMAR_IQA_REG, val); + writeq(val, iommu->reg + DMAR_IQA_REG); =20 iommu->gcmd |=3D DMA_GCMD_QIE; writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 64284938e1ce..e75ce8d28be6 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -697,7 +697,7 @@ static void iommu_set_root_entry(struct intel_iommu *io= mmu) addr |=3D DMA_RTADDR_SMT; =20 raw_spin_lock_irqsave(&iommu->register_lock, flag); - dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); + writeq(addr, iommu->reg + DMAR_RTADDR_REG); =20 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); =20 @@ -765,7 +765,7 @@ static void __iommu_flush_context(struct intel_iommu *i= ommu, val |=3D DMA_CCMD_ICC; =20 raw_spin_lock_irqsave(&iommu->register_lock, flag); - dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); + writeq(val, iommu->reg + DMAR_CCMD_REG); =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, @@ -806,8 +806,8 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16= did, u64 addr, raw_spin_lock_irqsave(&iommu->register_lock, flag); /* Note: Only uses first TLB reg currently */ if (val_iva) - dmar_writeq(iommu->reg + tlb_offset, val_iva); - dmar_writeq(iommu->reg + tlb_offset + 8, val); + writeq(val_iva, iommu->reg + tlb_offset); + writeq(val, iommu->reg + tlb_offset + 8); =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, tlb_offset + 8, @@ -4198,8 +4198,8 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ec= md, u64 oa, u64 ob) * - It's not invoked in any critical path. The extra MMIO * write doesn't bring any performance concerns. */ - dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); - dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); + writeq(ob, iommu->reg + DMAR_ECEO_REG); + writeq(ecmd | (oa << DMA_ECMD_OA_SHIFT), iommu->reg + DMAR_ECMD_REG); =20 IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq, !(res & DMA_ECMD_ECRSP_IP), res); diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index dbd8d196d154..10331364c0ef 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -148,9 +148,6 @@ =20 #define OFFSET_STRIDE (9) =20 -#define dmar_writeq(a,v) writeq(v,a) -#define dmar_writel(a, v) writel(v, a) - #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) #define DMAR_VER_MINOR(v) ((v) & 0x0f) =20 diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index 3fce6efea524..ad3a8a42f70c 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -465,8 +465,8 @@ static void iommu_set_irq_remapping(struct intel_iommu = *iommu, int mode) =20 raw_spin_lock_irqsave(&iommu->register_lock, flags); =20 - dmar_writeq(iommu->reg + DMAR_IRTA_REG, - (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); + writeq((addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE, + iommu->reg + DMAR_IRTA_REG); =20 /* Set interrupt-remapping table pointer */ writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); diff --git a/drivers/iommu/intel/perfmon.c b/drivers/iommu/intel/perfmon.c index 30bd684612ad..84f5ef2c42d8 100644 --- a/drivers/iommu/intel/perfmon.c +++ b/drivers/iommu/intel/perfmon.c @@ -99,20 +99,20 @@ IOMMU_PMU_ATTR(filter_page_table, "config2:32-36", IOMM= U_PMU_FILTER_PAGE_TABLE); #define iommu_pmu_set_filter(_name, _config, _filter, _idx, _econfig) \ { \ if ((iommu_pmu->filter & _filter) && iommu_pmu_en_##_name(_econfig)) { \ - dmar_writel(iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ - IOMMU_PMU_CFG_SIZE + \ - (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET, \ - iommu_pmu_get_##_name(_config) | IOMMU_PMU_FILTER_EN);\ + writel(iommu_pmu_get_##_name(_config) | IOMMU_PMU_FILTER_EN, \ + iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ + IOMMU_PMU_CFG_SIZE + \ + (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET); \ } \ } =20 #define iommu_pmu_clear_filter(_filter, _idx) \ { \ if (iommu_pmu->filter & _filter) { \ - dmar_writel(iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ - IOMMU_PMU_CFG_SIZE + \ - (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET, \ - 0); \ + writel(0, \ + iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ + IOMMU_PMU_CFG_SIZE + \ + (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET); \ } \ } =20 @@ -411,7 +411,7 @@ static int iommu_pmu_assign_event(struct iommu_pmu *iom= mu_pmu, hwc->idx =3D idx; =20 /* config events */ - dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config); + writeq(hwc->config, iommu_config_base(iommu_pmu, idx)); =20 iommu_pmu_set_filter(requester_id, event->attr.config1, IOMMU_PMU_FILTER_REQUESTER_ID, idx, @@ -510,7 +510,7 @@ static void iommu_pmu_counter_overflow(struct iommu_pmu= *iommu_pmu) iommu_pmu_event_update(event); } =20 - dmar_writeq(iommu_pmu->overflow, status); + writeq(status, iommu_pmu->overflow); } } =20 @@ -524,7 +524,7 @@ static irqreturn_t iommu_pmu_irq_handler(int irq, void = *dev_id) iommu_pmu_counter_overflow(iommu->pmu); =20 /* Clear the status bit */ - dmar_writel(iommu->reg + DMAR_PERFINTRSTS_REG, DMA_PERFINTRSTS_PIS); + writel(DMA_PERFINTRSTS_PIS, iommu->reg + DMAR_PERFINTRSTS_REG); =20 return IRQ_HANDLED; } diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c index c28fbd5c14a7..1460b57db129 100644 --- a/drivers/iommu/intel/prq.c +++ b/drivers/iommu/intel/prq.c @@ -259,7 +259,7 @@ static irqreturn_t prq_event_thread(int irq, void *d) head =3D (head + sizeof(*req)) & PRQ_RING_MASK; } =20 - dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); + writeq(tail, iommu->reg + DMAR_PQH_REG); =20 /* * Clear the page request overflow bit and wake up all threads that @@ -325,9 +325,9 @@ int intel_iommu_enable_prq(struct intel_iommu *iommu) iommu->name); goto free_iopfq; } - dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORD= ER); + writeq(0ULL, iommu->reg + DMAR_PQH_REG); + writeq(0ULL, iommu->reg + DMAR_PQT_REG); + writeq(virt_to_phys(iommu->prq) | PRQ_ORDER, iommu->reg + DMAR_PQA_REG); =20 init_completion(&iommu->prq_complete); =20 @@ -348,9 +348,9 @@ int intel_iommu_enable_prq(struct intel_iommu *iommu) =20 int intel_iommu_finish_prq(struct intel_iommu *iommu) { - dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); + writeq(0ULL, iommu->reg + DMAR_PQH_REG); + writeq(0ULL, iommu->reg + DMAR_PQT_REG); + writeq(0ULL, iommu->reg + DMAR_PQA_REG); =20 if (iommu->pr_irq) { free_irq(iommu->pr_irq, iommu); --=20 2.51.0