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charset="utf-8" Add iommu-map property which helps when each channel requires its own stream ID for the transfer. Use iommu-map to specify separate stream ID for each channel. This enables each channel to be in its own iommu domain and keeps the memory isolated from other devices sharing the same DMA controller. Signed-off-by: Akhil R --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.= yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 0dabe9bbb219..542e9cb9f641 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -14,6 +14,7 @@ description: | maintainers: - Jon Hunter - Rajesh Gumasta + - Akhil R =20 allOf: - $ref: dma-controller.yaml# @@ -51,6 +52,13 @@ properties: iommus: maxItems: 1 =20 + iommu-map: + description: | + The mapping of DMA controller channels to IOMMU stream IDs. Each ent= ry in the map specifies the + relationship between a DMA channel and its corresponding IOMMU strea= m ID. The format is: + "". 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charset="utf-8" In Tegra264 and Tegra234, GPCDMA reset control is not exposed to Linux and is handled by BPMP. In Tegra234 BPMP supported a dummy reset which just return success on reset without doing an actual reset. This as well is not supported in Tegra264 BPMP. Therefore mark 'reset' and 'reset-names' property as required only for devices prior to Tegra234. Signed-off-by: Akhil R --- .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.= yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 542e9cb9f641..9457d406428f 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -16,9 +16,6 @@ maintainers: - Rajesh Gumasta - Akhil R =20 -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: @@ -68,12 +65,24 @@ required: - compatible - reg - interrupts - - resets - - reset-names - "#dma-cells" - iommus - dma-channel-mask =20 +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-gpcdma + - nvidia,tegra194-gpcdma + then: + required: + - resets + - reset-names + additionalProperties: false =20 examples: --=20 2.50.1 From nobody Fri Apr 3 04:39:50 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012027.outbound.protection.outlook.com [40.107.209.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FA2A36EA9C; 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charset="utf-8" Tegra264 BPMP restricts access to GPCDMA reset control and the reset is expected to be deasserted on boot by BPMP. Hence Make the reset control optional in the driver. Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 4d6fe0efa76e..236a298c26a1 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1382,7 +1382,7 @@ static int tegra_dma_probe(struct platform_device *pd= ev) if (IS_ERR(tdma->base_addr)) return PTR_ERR(tdma->base_addr); =20 - tdma->rst =3D devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); + tdma->rst =3D devm_reset_control_get_optional_exclusive(&pdev->dev, "gpcd= ma"); if (IS_ERR(tdma->rst)) { return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), "Missing controller reset\n"); --=20 2.50.1 From nobody Fri Apr 3 04:39:50 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013008.outbound.protection.outlook.com [40.93.201.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5330036EA9E; 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charset="utf-8" Repurpose tegra_dma_channel_regs struct to define offsets for all the channel registers. Previously, the struct only held the register values for each transfer and was wrapped within tegra_dma_sg_req. Now, let struct tegra_dma_sg_req hold the values directly and use channel_regs for storing the register offsets. Update all register read/write to use channel_regs struct. This is to accommodate the register offset change in Tegra264. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 280 +++++++++++++++++---------------- 1 file changed, 147 insertions(+), 133 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 236a298c26a1..72701b543ceb 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -22,7 +22,6 @@ #include "virt-dma.h" =20 /* CSR register */ -#define TEGRA_GPCDMA_CHAN_CSR 0x00 #define TEGRA_GPCDMA_CSR_ENB BIT(31) #define TEGRA_GPCDMA_CSR_IE_EOC BIT(30) #define TEGRA_GPCDMA_CSR_ONCE BIT(27) @@ -58,7 +57,6 @@ #define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10) =20 /* STATUS register */ -#define TEGRA_GPCDMA_CHAN_STATUS 0x004 #define TEGRA_GPCDMA_STATUS_BUSY BIT(31) #define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30) #define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28) @@ -70,22 +68,13 @@ #define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21) #define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20) =20 -#define TEGRA_GPCDMA_CHAN_CSRE 0x008 #define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31) =20 -/* Source address */ -#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C - -/* Destination address */ -#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010 - /* High address pointer */ -#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014 #define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0) #define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16) =20 /* MC sequence register */ -#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18 #define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31) #define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25) #define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23) @@ -101,7 +90,6 @@ #define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0) =20 /* MMIO sequence register */ -#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c #define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31) #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28) #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \ @@ -120,17 +108,7 @@ #define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16) #define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7) =20 -/* Channel WCOUNT */ -#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20 - -/* Transfer count */ -#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24 - -/* DMA byte count status */ -#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28 - /* Error Status Register */ -#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF #define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \ @@ -143,14 +121,9 @@ #define TEGRA_DMA_MC_SLAVE_ERR 0xB #define TEGRA_DMA_MMIO_SLAVE_ERR 0xA =20 -/* Fixed Pattern */ -#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34 - -#define TEGRA_GPCDMA_CHAN_TZ 0x38 #define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0) #define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1) =20 -#define TEGRA_GPCDMA_CHAN_SPARE 0x3c #define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16) =20 /* @@ -181,19 +154,27 @@ struct tegra_dma_chip_data { unsigned int nr_channels; unsigned int channel_reg_size; unsigned int max_dma_count; + const struct tegra_dma_channel_regs *channel_regs; int (*terminate)(struct tegra_dma_channel *tdc); }; =20 /* DMA channel registers */ struct tegra_dma_channel_regs { u32 csr; - u32 src_ptr; - u32 dst_ptr; - u32 high_addr_ptr; + u32 status; + u32 csre; + u32 src; + u32 dst; + u32 high_addr; u32 mc_seq; u32 mmio_seq; u32 wcount; + u32 wxfer; + u32 wstatus; + u32 err_status; u32 fixed_pattern; + u32 tz; + u32 spare; }; =20 /* @@ -205,7 +186,14 @@ struct tegra_dma_channel_regs { */ struct tegra_dma_sg_req { unsigned int len; - struct tegra_dma_channel_regs ch_regs; + u32 csr; + u32 src; + u32 dst; + u32 high_addr; + u32 mc_seq; + u32 mmio_seq; + u32 wcount; + u32 fixed_pattern; }; =20 /* @@ -228,19 +216,20 @@ struct tegra_dma_desc { * tegra_dma_channel: Channel specific information */ struct tegra_dma_channel { - bool config_init; - char name[30]; - enum dma_transfer_direction sid_dir; - enum dma_status status; - int id; - int irq; - int slave_id; + const struct tegra_dma_channel_regs *regs; struct tegra_dma *tdma; struct virt_dma_chan vc; struct tegra_dma_desc *dma_desc; struct dma_slave_config dma_sconfig; + enum dma_transfer_direction sid_dir; + enum dma_status status; unsigned int stream_id; unsigned long chan_base_offset; + bool config_init; + char name[30]; + int id; + int irq; + int slave_id; }; =20 /* @@ -288,22 +277,25 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma= _channel *tdc) { dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", tdc->id, tdc->name); - dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR) + dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x\n", + tdc_read(tdc, tdc->regs->csr), + tdc_read(tdc, tdc->regs->status), + tdc_read(tdc, tdc->regs->csre) ); - dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS) + dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->high_addr) + ); + dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n", + tdc_read(tdc, tdc->regs->mc_seq), + tdc_read(tdc, tdc->regs->mmio_seq), + tdc_read(tdc, tdc->regs->wcount), + tdc_read(tdc, tdc->regs->wxfer), + tdc_read(tdc, tdc->regs->wstatus) ); dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS)); + tdc_read(tdc, tdc->regs->err_status)); } =20 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc, @@ -377,13 +369,13 @@ static int tegra_dma_pause(struct tegra_dma_channel *= tdc) int ret; u32 val; =20 - val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); + val =3D tdc_read(tdc, tdc->regs->csre); val |=3D TEGRA_GPCDMA_CHAN_CSRE_PAUSE; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + tdc_write(tdc, tdc->regs->csre, val); =20 /* Wait until busy bit is de-asserted */ ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + - tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, + tdc->chan_base_offset + tdc->regs->status, val, !(val & TEGRA_GPCDMA_STATUS_BUSY), TEGRA_GPCDMA_BURST_COMPLETE_TIME, @@ -419,9 +411,9 @@ static void tegra_dma_resume(struct tegra_dma_channel *= tdc) { u32 val; =20 - val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); + val =3D tdc_read(tdc, tdc->regs->csre); val &=3D ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + tdc_write(tdc, tdc->regs->csre, val); =20 tdc->status =3D DMA_IN_PROGRESS; } @@ -456,27 +448,27 @@ static void tegra_dma_disable(struct tegra_dma_channe= l *tdc) { u32 csr, status; =20 - csr =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); + csr =3D tdc_read(tdc, tdc->regs->csr); =20 /* Disable interrupts */ csr &=3D ~TEGRA_GPCDMA_CSR_IE_EOC; =20 /* Disable DMA */ csr &=3D ~TEGRA_GPCDMA_CSR_ENB; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); + tdc_write(tdc, tdc->regs->csr, csr); =20 /* Clear interrupt status if it is there */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) { dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status); + tdc_write(tdc, tdc->regs->status, status); } } =20 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc) { struct tegra_dma_desc *dma_desc =3D tdc->dma_desc; - struct tegra_dma_channel_regs *ch_regs; + struct tegra_dma_sg_req *sg_req; int ret; u32 val; =20 @@ -488,29 +480,29 @@ static void tegra_dma_configure_next_sg(struct tegra_= dma_channel *tdc) =20 /* Configure next transfer immediately after DMA is busy */ ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + - tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, + tdc->chan_base_offset + tdc->regs->status, val, (val & TEGRA_GPCDMA_STATUS_BUSY), 0, TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); if (ret) return; =20 - ch_regs =3D &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; + sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); + tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); =20 /* Start DMA */ - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, - ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); + tdc_write(tdc, tdc->regs->csr, + sg_req->csr | TEGRA_GPCDMA_CSR_ENB); } =20 static void tegra_dma_start(struct tegra_dma_channel *tdc) { struct tegra_dma_desc *dma_desc =3D tdc->dma_desc; - struct tegra_dma_channel_regs *ch_regs; + struct tegra_dma_sg_req *sg_req; struct virt_dma_desc *vdesc; =20 if (!dma_desc) { @@ -526,21 +518,21 @@ static void tegra_dma_start(struct tegra_dma_channel = *tdc) tegra_dma_resume(tdc); } =20 - ch_regs =3D &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; + sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); + tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); + tdc_write(tdc, tdc->regs->csr, 0); + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); + tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern); + tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq); + tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq); + tdc_write(tdc, tdc->regs->csr, sg_req->csr); =20 /* Start DMA */ - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, - ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); + tdc_write(tdc, tdc->regs->csr, + sg_req->csr | TEGRA_GPCDMA_CSR_ENB); } =20 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc) @@ -601,19 +593,19 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_i= d) u32 status; =20 /* Check channel error status register */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS); + status =3D tdc_read(tdc, tdc->regs->err_status); if (status) { tegra_dma_chan_decode_error(tdc, status); tegra_dma_dump_chan_regs(tdc); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF); + tdc_write(tdc, tdc->regs->err_status, 0xFFFFFFFF); } =20 spin_lock(&tdc->vc.lock); - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC)) goto irq_done; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, + tdc_write(tdc, tdc->regs->status, TEGRA_GPCDMA_STATUS_ISE_EOC); =20 if (!dma_desc) @@ -673,10 +665,10 @@ static int tegra_dma_stop_client(struct tegra_dma_cha= nnel *tdc) * to stop DMA engine from starting any more bursts for * the given client and wait for in flight bursts to complete */ - csr =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); + csr =3D tdc_read(tdc, tdc->regs->csr); csr &=3D ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK); csr |=3D TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); + tdc_write(tdc, tdc->regs->csr, csr); =20 /* Wait for in flight data transfer to finish */ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME); @@ -687,7 +679,7 @@ static int tegra_dma_stop_client(struct tegra_dma_chann= el *tdc) =20 ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + tdc->chan_base_offset + - TEGRA_GPCDMA_CHAN_STATUS, + tdc->regs->status, status, !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX | TEGRA_GPCDMA_STATUS_CHANNEL_RX)), @@ -739,14 +731,14 @@ static int tegra_dma_get_residual(struct tegra_dma_ch= annel *tdc) unsigned int bytes_xfer, residual; u32 wcount =3D 0, status; =20 - wcount =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT); + wcount =3D tdc_read(tdc, tdc->regs->wxfer); =20 /* * Set wcount =3D 0 if EOC bit is set. The transfer would have * already completed and the CHAN_XFER_COUNT could have updated * for the next transfer, specifically in case of cyclic transfers. */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) wcount =3D 0; =20 @@ -893,7 +885,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr= _t dest, int value, /* Configure default priority weight for the channel */ csr |=3D FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -916,16 +908,16 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_ad= dr_t dest, int value, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].ch_regs.src_ptr =3D 0; - sg_req[0].ch_regs.dst_ptr =3D dest; - sg_req[0].ch_regs.high_addr_ptr =3D + sg_req[0].src =3D 0; + sg_req[0].dst =3D dest; + sg_req[0].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); - sg_req[0].ch_regs.fixed_pattern =3D value; + sg_req[0].fixed_pattern =3D value; /* Word count reg takes value as (N +1) words */ - sg_req[0].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[0].ch_regs.csr =3D csr; - sg_req[0].ch_regs.mmio_seq =3D 0; - sg_req[0].ch_regs.mc_seq =3D mc_seq; + sg_req[0].wcount =3D ((len - 4) >> 2); + sg_req[0].csr =3D csr; + sg_req[0].mmio_seq =3D 0; + sg_req[0].mc_seq =3D mc_seq; sg_req[0].len =3D len; =20 dma_desc->cyclic =3D false; @@ -961,7 +953,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr= _t dest, /* Configure default priority weight for the channel */ csr |=3D FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) | (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); @@ -985,17 +977,17 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_ad= dr_t dest, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].ch_regs.src_ptr =3D src; - sg_req[0].ch_regs.dst_ptr =3D dest; - sg_req[0].ch_regs.high_addr_ptr =3D + sg_req[0].src =3D src; + sg_req[0].dst =3D dest; + sg_req[0].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32)); - sg_req[0].ch_regs.high_addr_ptr |=3D + sg_req[0].high_addr |=3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); /* Word count reg takes value as (N +1) words */ - sg_req[0].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[0].ch_regs.csr =3D csr; - sg_req[0].ch_regs.mmio_seq =3D 0; - sg_req[0].ch_regs.mc_seq =3D mc_seq; + sg_req[0].wcount =3D ((len - 4) >> 2); + sg_req[0].csr =3D csr; + sg_req[0].mmio_seq =3D 0; + sg_req[0].mc_seq =3D mc_seq; sg_req[0].len =3D len; =20 dma_desc->cyclic =3D false; @@ -1049,7 +1041,7 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct s= catterlist *sgl, if (flags & DMA_PREP_INTERRUPT) csr |=3D TEGRA_GPCDMA_CSR_IE_EOC; =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -1096,14 +1088,14 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, dma_desc->bytes_req +=3D len; =20 if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].ch_regs.src_ptr =3D mem; - sg_req[i].ch_regs.dst_ptr =3D apb_ptr; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D mem; + sg_req[i].dst =3D apb_ptr; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].ch_regs.src_ptr =3D apb_ptr; - sg_req[i].ch_regs.dst_ptr =3D mem; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D apb_ptr; + sg_req[i].dst =3D mem; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } =20 @@ -1111,10 +1103,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. */ - sg_req[i].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[i].ch_regs.csr =3D csr; - sg_req[i].ch_regs.mmio_seq =3D mmio_seq; - sg_req[i].ch_regs.mc_seq =3D mc_seq; + sg_req[i].wcount =3D ((len - 4) >> 2); + sg_req[i].csr =3D csr; + sg_req[i].mmio_seq =3D mmio_seq; + sg_req[i].mc_seq =3D mc_seq; sg_req[i].len =3D len; } =20 @@ -1186,7 +1178,7 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_ad= dr_t buf_addr, size_t buf_l =20 mmio_seq |=3D FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -1218,24 +1210,24 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_= addr_t buf_addr, size_t buf_l for (i =3D 0; i < period_count; i++) { mmio_seq |=3D get_burst_size(tdc, burst_size, slave_bw, len); if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].ch_regs.src_ptr =3D mem; - sg_req[i].ch_regs.dst_ptr =3D apb_ptr; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D mem; + sg_req[i].dst =3D apb_ptr; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].ch_regs.src_ptr =3D apb_ptr; - sg_req[i].ch_regs.dst_ptr =3D mem; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D apb_ptr; + sg_req[i].dst =3D mem; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } /* * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. */ - sg_req[i].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[i].ch_regs.csr =3D csr; - sg_req[i].ch_regs.mmio_seq =3D mmio_seq; - sg_req[i].ch_regs.mc_seq =3D mc_seq; + sg_req[i].wcount =3D ((len - 4) >> 2); + sg_req[i].csr =3D csr; + sg_req[i].mmio_seq =3D mmio_seq; + sg_req[i].mc_seq =3D mc_seq; sg_req[i].len =3D len; =20 mem +=3D len; @@ -1305,11 +1297,30 @@ static struct dma_chan *tegra_dma_of_xlate(struct o= f_phandle_args *dma_spec, return chan; } =20 +static const struct tegra_dma_channel_regs tegra186_reg_offsets =3D { + .csr =3D 0x0, + .status =3D 0x4, + .csre =3D 0x8, + .src =3D 0xc, + .dst =3D 0x10, + .high_addr =3D 0x14, + .mc_seq =3D 0x18, + .mmio_seq =3D 0x1c, + .wcount =3D 0x20, + .wxfer =3D 0x24, + .wstatus =3D 0x28, + .err_status =3D 0x30, + .fixed_pattern =3D 0x34, + .tz =3D 0x38, + .spare =3D 0x40, +}; + static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D false, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_stop_client, }; =20 @@ -1318,6 +1329,7 @@ static const struct tegra_dma_chip_data tegra194_dma_= chip_data =3D { .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_pause, }; =20 @@ -1326,6 +1338,7 @@ static const struct tegra_dma_chip_data tegra234_dma_= chip_data =3D { .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_pause_noerr, }; =20 @@ -1346,7 +1359,7 @@ MODULE_DEVICE_TABLE(of, tegra_dma_of_match); =20 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream= _id) { - unsigned int reg_val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + unsigned int reg_val =3D tdc_read(tdc, tdc->regs->mc_seq); =20 reg_val &=3D ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK); reg_val &=3D ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); @@ -1354,7 +1367,7 @@ static int tegra_dma_program_sid(struct tegra_dma_cha= nnel *tdc, int stream_id) reg_val |=3D FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id); 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charset="utf-8" Tegra264 supports address width of 41 bits and has a separate register to accommodate the high address. Add a device data property to specify the number of address bits supported on a device and use that to program the required registers. Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 129 +++++++++++++++++++++------------ 1 file changed, 82 insertions(+), 47 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 72701b543ceb..ce3b1dd52bb3 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -151,6 +151,7 @@ struct tegra_dma_channel; */ struct tegra_dma_chip_data { bool hw_support_pause; + unsigned int addr_bits; unsigned int nr_channels; unsigned int channel_reg_size; unsigned int max_dma_count; @@ -166,6 +167,8 @@ struct tegra_dma_channel_regs { u32 src; u32 dst; u32 high_addr; + u32 src_high; + u32 dst_high; u32 mc_seq; u32 mmio_seq; u32 wcount; @@ -189,7 +192,8 @@ struct tegra_dma_sg_req { u32 csr; u32 src; u32 dst; - u32 high_addr; + u32 src_high; + u32 dst_high; u32 mc_seq; u32 mmio_seq; u32 wcount; @@ -273,6 +277,41 @@ static inline struct device *tdc2dev(struct tegra_dma_= channel *tdc) return tdc->vc.chan.device->dev; } =20 +static void tegra_dma_program_addr(struct tegra_dma_channel *tdc, + struct tegra_dma_sg_req *sg_req) +{ + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + + if (tdc->tdma->chip_data->addr_bits > 40) { + tdc_write(tdc, tdc->regs->src_high, + sg_req->src_high); + tdc_write(tdc, tdc->regs->dst_high, + sg_req->dst_high); + } else { + tdc_write(tdc, tdc->regs->high_addr, + sg_req->src_high | sg_req->dst_high); + } +} + +static void tegra_dma_configure_addr(struct tegra_dma_channel *tdc, + struct tegra_dma_sg_req *sg_req, + phys_addr_t src, phys_addr_t dst) +{ + sg_req->src =3D lower_32_bits(src); + sg_req->dst =3D lower_32_bits(dst); + + if (tdc->tdma->chip_data->addr_bits > 40) { + sg_req->src_high =3D upper_32_bits(src); + sg_req->dst_high =3D upper_32_bits(dst); + } else { + sg_req->src_high =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, + upper_32_bits(src)); + sg_req->dst_high =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, + upper_32_bits(dst)); + } +} + static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc) { dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", @@ -282,11 +321,22 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma= _channel *tdc) tdc_read(tdc, tdc->regs->status), tdc_read(tdc, tdc->regs->csre) ); - dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", - tdc_read(tdc, tdc->regs->src), - tdc_read(tdc, tdc->regs->dst), - tdc_read(tdc, tdc->regs->high_addr) - ); + + if (tdc->tdma->chip_data->addr_bits > 40) { + dev_dbg(tdc2dev(tdc), "SRC %x SRC HI %x DST %x DST HI %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->src_high), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->dst_high) + ); + } else { + dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->high_addr) + ); + } + dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n", tdc_read(tdc, tdc->regs->mc_seq), tdc_read(tdc, tdc->regs->mmio_seq), @@ -490,9 +540,7 @@ static void tegra_dma_configure_next_sg(struct tegra_dm= a_channel *tdc) sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); - tdc_write(tdc, tdc->regs->src, sg_req->src); - tdc_write(tdc, tdc->regs->dst, sg_req->dst); - tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); + tegra_dma_program_addr(tdc, sg_req); =20 /* Start DMA */ tdc_write(tdc, tdc->regs->csr, @@ -520,11 +568,9 @@ static void tegra_dma_start(struct tegra_dma_channel *= tdc) =20 sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 + tegra_dma_program_addr(tdc, sg_req); tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); tdc_write(tdc, tdc->regs->csr, 0); - tdc_write(tdc, tdc->regs->src, sg_req->src); - tdc_write(tdc, tdc->regs->dst, sg_req->dst); - tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern); tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq); tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq); @@ -829,7 +875,7 @@ static unsigned int get_burst_size(struct tegra_dma_cha= nnel *tdc, =20 static int get_transfer_param(struct tegra_dma_channel *tdc, enum dma_transfer_direction direction, - u32 *apb_addr, + dma_addr_t *apb_addr, u32 *mmio_seq, u32 *csr, unsigned int *burst_size, @@ -908,10 +954,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_add= r_t dest, int value, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].src =3D 0; - sg_req[0].dst =3D dest; - sg_req[0].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); + tegra_dma_configure_addr(tdc, &sg_req[0], 0, dest); sg_req[0].fixed_pattern =3D value; /* Word count reg takes value as (N +1) words */ sg_req[0].wcount =3D ((len - 4) >> 2); @@ -977,12 +1020,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_ad= dr_t dest, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].src =3D src; - sg_req[0].dst =3D dest; - sg_req[0].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32)); - sg_req[0].high_addr |=3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); + tegra_dma_configure_addr(tdc, &sg_req[0], src, dest); /* Word count reg takes value as (N +1) words */ sg_req[0].wcount =3D ((len - 4) >> 2); sg_req[0].csr =3D csr; @@ -1002,7 +1040,8 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct s= catterlist *sgl, struct tegra_dma_channel *tdc =3D to_tegra_dma_chan(dc); unsigned int max_dma_count =3D tdc->tdma->chip_data->max_dma_count; enum dma_slave_buswidth slave_bw =3D DMA_SLAVE_BUSWIDTH_UNDEFINED; - u32 csr, mc_seq, apb_ptr =3D 0, mmio_seq =3D 0; + u32 csr, mc_seq, mmio_seq =3D 0; + dma_addr_t apb_ptr =3D 0; struct tegra_dma_sg_req *sg_req; struct tegra_dma_desc *dma_desc; struct scatterlist *sg; @@ -1087,17 +1126,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, mmio_seq |=3D get_burst_size(tdc, burst_size, slave_bw, len); dma_desc->bytes_req +=3D len; =20 - if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].src =3D mem; - sg_req[i].dst =3D apb_ptr; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); - } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].src =3D apb_ptr; - sg_req[i].dst =3D mem; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); - } + if (direction =3D=3D DMA_MEM_TO_DEV) + tegra_dma_configure_addr(tdc, &sg_req[i], mem, apb_ptr); + else if (direction =3D=3D DMA_DEV_TO_MEM) + tegra_dma_configure_addr(tdc, &sg_req[i], apb_ptr, mem); =20 /* * Word count register takes input in words. Writing a value @@ -1120,7 +1152,8 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_ad= dr_t buf_addr, size_t buf_l unsigned long flags) { enum dma_slave_buswidth slave_bw =3D DMA_SLAVE_BUSWIDTH_UNDEFINED; - u32 csr, mc_seq, apb_ptr =3D 0, mmio_seq =3D 0, burst_size; + u32 csr, mc_seq, mmio_seq =3D 0, burst_size; + dma_addr_t apb_ptr =3D 0; unsigned int max_dma_count, len, period_count, i; struct tegra_dma_channel *tdc =3D to_tegra_dma_chan(dc); struct tegra_dma_desc *dma_desc; @@ -1209,17 +1242,10 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_= addr_t buf_addr, size_t buf_l /* Split transfer equal to period size */ for (i =3D 0; i < period_count; i++) { mmio_seq |=3D get_burst_size(tdc, burst_size, slave_bw, len); - if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].src =3D mem; - sg_req[i].dst =3D apb_ptr; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); - } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].src =3D apb_ptr; - sg_req[i].dst =3D mem; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); - } + if (direction =3D=3D DMA_MEM_TO_DEV) + tegra_dma_configure_addr(tdc, &sg_req[i], mem, apb_ptr); + else if (direction =3D=3D DMA_DEV_TO_MEM) + tegra_dma_configure_addr(tdc, &sg_req[i], apb_ptr, mem); /* * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. @@ -1317,6 +1343,7 @@ static const struct tegra_dma_channel_regs tegra186_r= eg_offsets =3D { =20 static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, + .addr_bits =3D 40, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D false, @@ -1326,6 +1353,7 @@ static const struct tegra_dma_chip_data tegra186_dma_= chip_data =3D { =20 static const struct tegra_dma_chip_data tegra194_dma_chip_data =3D { .nr_channels =3D 32, + .addr_bits =3D 40, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, @@ -1335,6 +1363,7 @@ static const struct tegra_dma_chip_data tegra194_dma_= chip_data =3D { =20 static const struct tegra_dma_chip_data tegra234_dma_chip_data =3D { .nr_channels =3D 32, + .addr_bits =3D 41, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, @@ -1446,6 +1475,12 @@ static int tegra_dma_probe(struct platform_device *p= dev) tdc->stream_id =3D stream_id; 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charset="utf-8" Use iommu-map, when provided, to get the stream ID to be programmed for each channel. Register each channel separately for allowing it to use a separate IOMMU domain for the transfer. Channels will continue to use the same global stream ID if iommu-map property is not present in the device tree. Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 62 +++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 13 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index ce3b1dd52bb3..b8ca269fa3ba 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1403,9 +1404,12 @@ static int tegra_dma_program_sid(struct tegra_dma_ch= annel *tdc, int stream_id) static int tegra_dma_probe(struct platform_device *pdev) { const struct tegra_dma_chip_data *cdata =3D NULL; + struct tegra_dma_channel *tdc; + struct tegra_dma *tdma; + struct dma_chan *chan; + bool use_iommu_map =3D false; unsigned int i; u32 stream_id; - struct tegra_dma *tdma; int ret; =20 cdata =3D of_device_get_match_data(&pdev->dev); @@ -1433,9 +1437,12 @@ static int tegra_dma_probe(struct platform_device *p= dev) =20 tdma->dma_dev.dev =3D &pdev->dev; =20 - if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { - dev_err(&pdev->dev, "Missing iommu stream-id\n"); - return -EINVAL; + use_iommu_map =3D of_property_present(pdev->dev.of_node, "iommu-map"); + if (!use_iommu_map) { + if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { + dev_err(&pdev->dev, "Missing iommu stream-id\n"); + return -EINVAL; + } } =20 ret =3D device_property_read_u32(&pdev->dev, "dma-channel-mask", @@ -1449,7 +1456,7 @@ static int tegra_dma_probe(struct platform_device *pd= ev) =20 INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i =3D 0; i < cdata->nr_channels; i++) { - struct tegra_dma_channel *tdc =3D &tdma->channels[i]; + tdc =3D &tdma->channels[i]; =20 /* Check for channel mask */ if (!(tdma->chan_mask & BIT(i))) @@ -1469,10 +1476,6 @@ static int tegra_dma_probe(struct platform_device *p= dev) =20 vchan_init(&tdc->vc, &tdma->dma_dev); tdc->vc.desc_free =3D tegra_dma_desc_free; - - /* program stream-id for this channel */ - tegra_dma_program_sid(tdc, stream_id); - tdc->stream_id =3D stream_id; } =20 ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bi= ts)); @@ -1517,20 +1520,53 @@ static int tegra_dma_probe(struct platform_device *= pdev) return ret; } =20 + list_for_each_entry(chan, &tdma->dma_dev.channels, device_node) { + struct device *chdev =3D &chan->dev->device; + + tdc =3D to_tegra_dma_chan(chan); + if (use_iommu_map) { + chdev->coherent_dma_mask =3D pdev->dev.coherent_dma_mask; + chdev->dma_mask =3D &chdev->coherent_dma_mask; + chdev->bus =3D pdev->dev.bus; + + ret =3D of_dma_configure_id(chdev, pdev->dev.of_node, + true, &tdc->id); + if (ret) { + dev_err(chdev, "Failed to configure IOMMU for channel %d: %d\n", + tdc->id, ret); + goto err_unregister; + } + + if (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) { + dev_err(chdev, "Failed to get stream ID for channel %d\n", + tdc->id); + goto err_unregister; + } + + chan->dev->chan_dma_dev =3D true; + } + + /* program stream-id for this channel */ + tegra_dma_program_sid(tdc, stream_id); + tdc->stream_id =3D stream_id; + } + ret =3D of_dma_controller_register(pdev->dev.of_node, tegra_dma_of_xlate, tdma); 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charset="utf-8" Update compatible and chip data to support GPCDMA in Tegra264. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index b8ca269fa3ba..11347c9f3215 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1342,6 +1342,25 @@ static const struct tegra_dma_channel_regs tegra186_= reg_offsets =3D { .spare =3D 0x40, }; =20 +static const struct tegra_dma_channel_regs tegra264_reg_offsets =3D { + .csr =3D 0x0, + .status =3D 0x4, + .csre =3D 0x8, + .src =3D 0xc, + .dst =3D 0x10, + .src_high =3D 0x14, + .dst_high =3D 0x18, + .mc_seq =3D 0x1c, + .mmio_seq =3D 0x20, + .wcount =3D 0x24, + .wxfer =3D 0x28, + .wstatus =3D 0x2c, + .err_status =3D 0x34, + .fixed_pattern =3D 0x38, + .tz =3D 0x3c, + .spare =3D 0x44, +}; + static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, .addr_bits =3D 40, @@ -1372,6 +1391,16 @@ static const struct tegra_dma_chip_data tegra234_dma= _chip_data =3D { .terminate =3D tegra_dma_pause_noerr, }; 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charset="utf-8" Add iommu-map and remove iommus in the GPCDMA controller node so that each channel uses separate stream ID and gets its own IOMMU domain for memory. Also enable GPCDMA for Tegra264. Signed-off-by: Akhil R --- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 +++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 33 ++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra264-p3834.dtsi index 7e2c3e66c2ab..c8beb616964a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -16,6 +16,10 @@ serial@c4e0000 { serial@c5a0000 { status =3D "okay"; }; + + dma-controller@8400000 { + status =3D "okay"; + }; }; =20 bus@8100000000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 7644a41d5f72..0317418c95d3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3243,7 +3243,38 @@ gpcdma: dma-controller@8400000 { , ; #dma-cells =3D <1>; - iommus =3D <&smmu1 0x00000800>; + iommu-map =3D + <1 &smmu1 0x801 1>, + <2 &smmu1 0x802 1>, + <3 &smmu1 0x803 1>, + <4 &smmu1 0x804 1>, + <5 &smmu1 0x805 1>, + <6 &smmu1 0x806 1>, + <7 &smmu1 0x807 1>, + <8 &smmu1 0x808 1>, + <9 &smmu1 0x809 1>, + <10 &smmu1 0x80a 1>, + <11 &smmu1 0x80b 1>, + <12 &smmu1 0x80c 1>, + <13 &smmu1 0x80d 1>, + <14 &smmu1 0x80e 1>, + <15 &smmu1 0x80f 1>, + <16 &smmu1 0x810 1>, + <17 &smmu1 0x811 1>, + <18 &smmu1 0x812 1>, + <19 &smmu1 0x813 1>, + <20 &smmu1 0x814 1>, + <21 &smmu1 0x815 1>, + <22 &smmu1 0x816 1>, + <23 &smmu1 0x817 1>, + <24 &smmu1 0x818 1>, + <25 &smmu1 0x819 1>, + <26 &smmu1 0x81a 1>, + <27 &smmu1 0x81b 1>, + <28 &smmu1 0x81c 1>, + <29 &smmu1 0x81d 1>, + <30 &smmu1 0x81e 1>, + <31 &smmu1 0x81f 1>; dma-coherent; dma-channel-mask =3D <0xfffffffe>; status =3D "disabled"; --=20 2.50.1