From nobody Sun Apr 5 13:12:52 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5E5C932548C; Tue, 17 Feb 2026 13:35:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771335343; cv=none; b=G9zlolWc8vazo3BnjPZf/KbGIxoJCXP8fCa8jNqw2YrqBnirdSluIMlF0vj8gvV4V8hZmTp+5yntYLI7QEeoBFGX0pirSURjiPygi6ja57o7oZ6MprABkMQ7S4Lr511gDb+lz01fpXcs5UhsmIjEqg3l1Vtvac/waACvhJkO8Eo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771335343; c=relaxed/simple; bh=y/V3R9g2AsOvXhnFszhbQ+7M//mYi5qmnHVETJIoqso=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aEKuLAVbs5rgGtqP2+3pDyb6ZEuPjWtb3fvlW6jcEhWlbqvswDPuZpbOjcPxMAq41JDVoaRpomey/wbitXgHlIxPteheec4aLTfSzqajX/mFbBv9p66Py3LF0SggqgKyDsXb/UX1SOJEwQ6HYuZIP9ECSP9GlWz0PBsibdLPI9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7658A1655; Tue, 17 Feb 2026 05:35:34 -0800 (PST) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 15EC73F632; Tue, 17 Feb 2026 05:35:38 -0800 (PST) From: Ryan Roberts To: stable@vger.kernel.org Cc: Ryan Roberts , catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jack Aboutboul , Sharath George John , Noah Meyerhans , Jim Perrin , Itaru Kitayama , Eric Chanudet , Mark Rutland , Ard Biesheuvel Subject: [PATCH 6.1 2/3] arm64: mm: Batch dsb and isb when populating pgtables Date: Tue, 17 Feb 2026 13:35:23 +0000 Message-ID: <20260217133527.2881603-3-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260217133527.2881603-1-ryan.roberts@arm.com> References: <20260217133527.2881603-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" [ Upstream commit 1fcb7cea8a5f7747e02230f816c2c80b060d9517 ] After removing uneccessary TLBIs, the next bottleneck when creating the page tables for the linear map is DSB and ISB, which were previously issued per-pte in __set_pte(). Since we are writing multiple ptes in a given pte table, we can elide these barriers and insert them once we have finished writing to the table. Execution time of map_mem(), which creates the kernel linear map page tables, was measured on different machines with different RAM configs: | Apple M2 VM | Ampere Altra| Ampere Altra| Ampere Altra | VM, 16G | VM, 64G | VM, 256G | Metal, 512G Reviewed-by: Ard Biesheuvel Reviewed-by: Mark Rutland Tested-by: Eric Chanudet Tested-by: Itaru Kitayama ---------------|-------------|-------------|-------------|------------- | ms (%) | ms (%) | ms (%) | ms (%) ---------------|-------------|-------------|-------------|------------- before | 78 (0%) | 435 (0%) | 1723 (0%) | 3779 (0%) after | 11 (-86%) | 161 (-63%) | 656 (-62%) | 1654 (-56%) Signed-off-by: Ryan Roberts Tested-by: Itaru Kitayama Tested-by: Eric Chanudet Reviewed-by: Mark Rutland Reviewed-by: Ard Biesheuvel Link: https://lore.kernel.org/r/20240412131908.433043-3-ryan.roberts@arm.com Signed-off-by: Will Deacon [ Ryan: Trivial backport ] Signed-off-by: Ryan Roberts --- arch/arm64/include/asm/pgtable.h | 7 ++++++- arch/arm64/mm/mmu.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index 62326f249aa71..3ea0c9768c4c9 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -261,9 +261,14 @@ static inline pte_t pte_mkdevmap(pte_t pte) return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); } -static inline void set_pte(pte_t *ptep, pte_t pte) +static inline void set_pte_nosync(pte_t *ptep, pte_t pte) { WRITE_ONCE(*ptep, pte); +} + +static inline void set_pte(pte_t *ptep, pte_t pte) +{ + set_pte_nosync(ptep, pte); /* * Only if the new pte is valid and kernel, otherwise TLB maintenance diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index b193ea2c0a629..ca06b5e131e0f 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -175,7 +175,11 @@ static void init_pte(pte_t *ptep, unsigned long addr, = unsigned long end, do { pte_t old_pte =3D READ_ONCE(*ptep); - set_pte(ptep, pfn_pte(__phys_to_pfn(phys), prot)); + /* + * Required barriers to make this visible to the table walker + * are deferred to the end of alloc_init_cont_pte(). + */ + set_pte_nosync(ptep, pfn_pte(__phys_to_pfn(phys), prot)); /* * After the PTE entry has been populated once, we @@ -229,6 +233,11 @@ static void alloc_init_cont_pte(pmd_t *pmdp, unsigned = long addr, phys +=3D next - addr; } while (addr =3D next, addr !=3D end); + /* + * Note: barriers and maintenance necessary to clear the fixmap slot + * ensure that all previous pgtable writes are visible to the table + * walker. + */ pte_clear_fixmap(); } -- 2.43.0