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charset="utf-8" Implement the EPC aux-resource API for DesignWare endpoint controllers with integrated eDMA. Report: - DMA controller MMIO window (PCI_EPC_AUX_DMA_CTRL_MMIO) - interrupt-emulation doorbell register (PCI_EPC_AUX_DOORBELL_MMIO), including its Linux IRQ and the data value to write to trigger the interrupt - per-channel LL descriptor regions (PCI_EPC_AUX_DMA_CHAN_DESC) If the DMA controller MMIO window is already exposed via a platform-owned fixed BAR subregion, also provide the BAR number and offset so EPF drivers can reuse it without reprogramming the BAR. Signed-off-by: Koichiro Den --- Changes since v7: - Use range_end_overflows_t() instead of an open-coded overflow check. - Make it explicit that the write data is 0 for dw-edma. .../pci/controller/dwc/pcie-designware-ep.c | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 7e7844ff0f7e..22b6777d520f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "pcie-designware.h" @@ -808,6 +809,155 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_= no, u8 vfunc_no) return ep->ops->get_features(ep); } =20 +static const struct pci_epc_bar_rsvd_region * +dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep, + enum pci_epc_bar_rsvd_region_type type, + enum pci_barno *bar, + resource_size_t *bar_offset) +{ + const struct pci_epc_features *features; + const struct pci_epc_bar_desc *bar_desc; + const struct pci_epc_bar_rsvd_region *r; + int i, j; + + if (!ep->ops->get_features) + return NULL; + + features =3D ep->ops->get_features(ep); + if (!features) + return NULL; + + for (i =3D BAR_0; i <=3D BAR_5; i++) { + bar_desc =3D &features->bar[i]; + + if (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions) + continue; + + for (j =3D 0; j < bar_desc->nr_rsvd_regions; j++) { + r =3D &bar_desc->rsvd_regions[j]; + + if (r->type !=3D type) + continue; + + if (bar) + *bar =3D i; + if (bar_offset) + *bar_offset =3D r->offset; + return r; + } + } + + return NULL; +} + +static int +dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epc_aux_resource *resources, + int num_resources) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + const struct pci_epc_bar_rsvd_region *rsvd; + struct dw_edma_chip *edma =3D &pci->edma; + enum pci_barno dma_ctrl_bar =3D NO_BAR; + int ll_cnt =3D 0, needed, idx =3D 0; + resource_size_t db_offset =3D edma->db_offset; + resource_size_t dma_ctrl_bar_offset =3D 0; + resource_size_t dma_reg_size; + unsigned int i; + + if (!pci->edma_reg_size) + return 0; + + dma_reg_size =3D pci->edma_reg_size; + + for (i =3D 0; i < edma->ll_wr_cnt; i++) + if (edma->ll_region_wr[i].sz) + ll_cnt++; + + for (i =3D 0; i < edma->ll_rd_cnt; i++) + if (edma->ll_region_rd[i].sz) + ll_cnt++; + + needed =3D 1 + ll_cnt + (db_offset !=3D ~0 ? 1 : 0); + + /* Count query mode */ + if (!resources || !num_resources) + return needed; + + if (num_resources < needed) + return -ENOSPC; + + rsvd =3D dw_pcie_ep_find_bar_rsvd_region(ep, + PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO, + &dma_ctrl_bar, + &dma_ctrl_bar_offset); + if (rsvd && rsvd->size < dma_reg_size) + dma_reg_size =3D rsvd->size; + + /* DMA register block */ + resources[idx++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CTRL_MMIO, + .phys_addr =3D pci->edma_reg_phys, + .size =3D dma_reg_size, + .bar =3D dma_ctrl_bar, + .bar_offset =3D dma_ctrl_bar_offset, + }; + + /* + * For interrupt-emulation doorbells, report a standalone resource + * instead of bundling it into the DMA controller MMIO resource. + */ + if (db_offset !=3D ~0) { + if (range_end_overflows_t(resource_size_t, db_offset, + sizeof(u32), dma_reg_size)) + return -EINVAL; + + resources[idx++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DOORBELL_MMIO, + .phys_addr =3D pci->edma_reg_phys + db_offset, + .size =3D sizeof(u32), + .bar =3D dma_ctrl_bar, + .bar_offset =3D dma_ctrl_bar !=3D NO_BAR ? + dma_ctrl_bar_offset + db_offset : 0, + .u.db_mmio =3D { + .irq =3D edma->db_irq, + .data =3D 0, /* write 0 to assert */ + }, + }; + } + + /* One LL region per write channel */ + for (i =3D 0; i < edma->ll_wr_cnt; i++) { + if (!edma->ll_region_wr[i].sz) + continue; + + resources[idx++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CHAN_DESC, + .phys_addr =3D edma->ll_region_wr[i].paddr, + .size =3D edma->ll_region_wr[i].sz, + .bar =3D NO_BAR, + .bar_offset =3D 0, + }; + } + + /* One LL region per read channel */ + for (i =3D 0; i < edma->ll_rd_cnt; i++) { + if (!edma->ll_region_rd[i].sz) + continue; + + resources[idx++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CHAN_DESC, + .phys_addr =3D edma->ll_region_rd[i].paddr, + .size =3D edma->ll_region_rd[i].sz, + .bar =3D NO_BAR, + .bar_offset =3D 0, + }; + } + + return idx; +} + static const struct pci_epc_ops epc_ops =3D { .write_header =3D dw_pcie_ep_write_header, .set_bar =3D dw_pcie_ep_set_bar, @@ -823,6 +973,7 @@ static const struct pci_epc_ops epc_ops =3D { .start =3D dw_pcie_ep_start, .stop =3D dw_pcie_ep_stop, .get_features =3D dw_pcie_ep_get_features, + .get_aux_resources =3D dw_pcie_ep_get_aux_resources, }; =20 /** --=20 2.51.0