From nobody Fri Apr 3 03:23:40 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DEC12D3750 for ; Tue, 17 Feb 2026 08:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771315292; cv=none; b=DxT9oQJY6GniXEdhL+BGKh+FRN3UZKIuHrTgCAX7jHEsvsIEEWNqnExqpMN3QQlsbM72fOq+xqDhmtUoq2zkZJgY7/Aifu1h4mnxZnTAFwo4dKtysEiEjV4eB5WEzlxgki0OgoNh+0kuySra7gXJtQy5Aeebvj0Z7ma4TVOtLbg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771315292; c=relaxed/simple; bh=l/XFNhsX7ERB7yaujlgzJEC3/+9JE4SydtkgZp8Bemg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NwVK6sVSGqOucD6+cXCr39QFMZrxMYEzFh2BMIfSuWPeuPvnvuGWhXWnABTdhBbmZLE5RySUP+f560nX0FVUqGMh0bxXK5qdP7u44wdG4q29i7nFTPoZcnG3z6qpGRIxxso+tylqRCce1u+2GcciS6zhGQin8r0HaTyn5H+zKmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZU/pKziZ; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZU/pKziZ" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-48371bb515eso44127745e9.1 for ; Tue, 17 Feb 2026 00:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771315290; x=1771920090; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kF6ZhZceexRomvWkubldKlsxvta1sWwN/u0Zy1Qrmak=; b=ZU/pKziZLd2CumEKBPlwgIGSbeZw35K3R3k1vs9uQ+VcfMGslVuPteJhXSopvViZy8 B6WzQO72TAxRhGovpNEaiAjMmHHf41Or7UUxD708DrnsSPtnOCVbWabdPoCPqTrZBZuz 2X9M5+oPaKGq4hwZ3nMjmcrkMBet/L5YZaEajEK1K1PnEm1lM+NJRb2YNtvRdb6jASd5 eba4UYuooAuX7XvSrGUToNt7GHhmVkTsj1AweqYhPTQpMaCQlinLSRC7X59sP9Vk6UMg gDpdOyp3h0hqBK7Wv5BbOS4QUMbPNr1Sw3Fl5aYjUtArazE3B3U067xUQziZ9w0Ch5yN fW+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771315290; x=1771920090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=kF6ZhZceexRomvWkubldKlsxvta1sWwN/u0Zy1Qrmak=; b=t0msdkP2YQGwrMjeyTO3LEHuN+/GYKAnGNjcgKu0jH32NKq4Ulx/piZxPmQ2wFabn+ U6Q0YX3uyKl29AbUolL8gGo7dt3TYb0S/Q3ezDWuJ3FgSi5AnjTTRA02Yx0QoXTfkpZ8 r2LIGIAGHnSvWuSVQxXmTHP+GlHhdAv1lAwMRPsclpjwBQOg39x2/A0YI3a4JSKNijOd 5VqtpubFjDgEWoBpG2YNiwKPCOm/nVwuy3J3LBnlHHzpOGKoOJAf5V2s8gOwNeYnOHXJ w3sffCi4Ib56k6Ovzr4KtGr857zoPsfSq6jWrhXoeA2Ma/blJ9xuiItgg3+dksyorf8K +j2g== X-Forwarded-Encrypted: i=1; AJvYcCVZUKqlAjpBhpuUENtDn75m8r9hLZF9vjJlM2XCY2wTh5R62F6+qsX3E5y1Ux4qZrHVVjsRLSdNZqLZpBY=@vger.kernel.org X-Gm-Message-State: AOJu0YyQeYtWvdWyo39YJBeogtg1WkhW8eihuyZ16kP49dJFOl6rb9HC DhACVBmrLzg4/ekJy+Nx+Gwsqr+MvLqKshn+CyezyHEudhaLB2jPJWMr X-Gm-Gg: AZuq6aIBwExfVa8V+f+XgTZZf4zdvFa13fWT9svRy0ktG6ZGg3LcucKNudC/69cDX3x ank64xf2FKJqL5lFFi82JuIGEt5CdjoWWo49/ZqLiZr3hsSvG/cmxD4ERx72exSCY3E6nE9mWfv jMyi83Rm5c2qn4eL/lxjFV4csNZ8i2uoGaKneTDMGHUk0ZRw69n5WwbwRKbFyiuaXw50mdr2st1 TTuFkCygkk2prZvMO2RC0kmWXxnMzXN4p+3kLydy6sG/keTLiQ9r/oQVIvamey9ZCHwt4E8+97/ R9AAWzubRzrXuhSkrpbt1H+eHPGX6zEFVSpPr0O9BVA0M1XMI3xMXO9nqdgOQGsY7a5T37u36El KMQqgqDsqL+YY9QePfenByXD9cq2QbwKfuu1Y0SNvDOFzuJIwV18riI4lUU7SV6WL4WTULM/2Y4 4Jwrel/loYgz3+gZtPSWF+/pBWqLHqgKnl4PcMPKacnnYcuzhEo2V9q87ElOw= X-Received: by 2002:a05:600c:a08c:b0:477:6374:6347 with SMTP id 5b1f17b1804b1-48373a5bad7mr216247045e9.22.1771315289461; Tue, 17 Feb 2026 00:01:29 -0800 (PST) Received: from ionutnechita-arz2022.localdomain ([2a02:2f07:6006:8800:54ea:a0a1:e16b:9ca4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48371a21cbesm153558775e9.5.2026.02.17.00.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 00:01:29 -0800 (PST) From: "Ionut Nechita (Sunlight Linux)" To: Bjorn Helgaas , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Lukas Wunner , Ionut Nechita , linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ionut Nechita Subject: [RFC PATCH 1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions Date: Tue, 17 Feb 2026 10:00:58 +0200 Message-ID: <20260217080102.206581-4-sunlightlinux@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260217080102.206581-2-sunlightlinux@gmail.com> References: <20260217080102.206581-2-sunlightlinux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ionut Nechita Add register definitions for PCIe Gen 7 128 GT/s link speed: - PCI_EXP_LNKCAP_SLS_128_0GB (encoding 0x7) - PCI_EXP_LNKCAP2_SLS_128_0GB (bit 6 in Supported Link Speeds Vector) - PCI_EXP_LNKCTL2_TLS_128_0GT (Target Link Speed 0x7) - PCIE_SPEED_128_0GT enum value (0x1a) Widen pci_dev.supported_speeds from u8 to u16 to accommodate the expanded Supported Link Speeds Vector which now uses bits 1-7. PCIe Gen 7 doubles the data rate to 128 GT/s using PAM4 signaling with mandatory Flit mode encoding (1:1, no overhead), providing up to 256 GB/s unidirectional (512 GB/s bi-directional) bandwidth on an x16 link. Note: Based on the PCIe 7.0 specification announced by PCI-SIG in 2022, targeted for member release in 2025. No hardware exists yet to validate these definitions. Signed-off-by: Ionut Nechita --- include/linux/pci.h | 3 ++- include/uapi/linux/pci_regs.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/linux/pci.h b/include/linux/pci.h index b5cc0c2b99065..21dd6ea5beb6d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -303,6 +303,7 @@ enum pci_bus_speed { PCIE_SPEED_16_0GT =3D 0x17, PCIE_SPEED_32_0GT =3D 0x18, PCIE_SPEED_64_0GT =3D 0x19, + PCIE_SPEED_128_0GT =3D 0x1a, PCI_SPEED_UNKNOWN =3D 0xff, }; =20 @@ -558,7 +559,7 @@ struct pci_dev { struct pci_tsm *tsm; /* TSM operation state */ #endif u16 acs_cap; /* ACS Capability offset */ - u8 supported_speeds; /* Supported Link Speeds Vector */ + u16 supported_speeds; /* Supported Link Speeds Vector */ phys_addr_t rom; /* Physical address if not from BAR */ size_t romlen; /* Length if not from BAR */ /* diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3add74ae25948..fa00c6ca9f382 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -545,6 +545,7 @@ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 = */ #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 = */ #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 = */ +#define PCI_EXP_LNKCAP_SLS_128_0GB 0x00000007 /* LNKCAP2 SLS Vector bit 6= */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ @@ -693,6 +694,7 @@ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */ +#define PCI_EXP_LNKCAP2_SLS_128_0GB 0x00000080 /* Supported Speed 128GT/s= */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */ #define PCI_EXP_LNKCTL2_TLS 0x000f @@ -702,6 +704,7 @@ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ +#define PCI_EXP_LNKCTL2_TLS_128_0GT 0x0007 /* Supported Speed 128GT/s */ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ --=20 2.53.0 From nobody Fri Apr 3 03:23:40 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45FBC2D7DFE for ; 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Tue, 17 Feb 2026 00:01:37 -0800 (PST) Received: from ionutnechita-arz2022.localdomain ([2a02:2f07:6006:8800:54ea:a0a1:e16b:9ca4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48371a21cbesm153558775e9.5.2026.02.17.00.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 00:01:36 -0800 (PST) From: "Ionut Nechita (Sunlight Linux)" To: Bjorn Helgaas , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Lukas Wunner , Ionut Nechita , linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ionut Nechita Subject: [RFC PATCH 2/3] PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting Date: Tue, 17 Feb 2026 10:01:00 +0200 Message-ID: <20260217080102.206581-6-sunlightlinux@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260217080102.206581-2-sunlightlinux@gmail.com> References: <20260217080102.206581-2-sunlightlinux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ionut Nechita Add kernel infrastructure to detect and report PCIe Gen 7 128 GT/s link speeds: - Extend PCIE_LNKCAP_SLS2SPEED, PCIE_LNKCAP2_SLS2SPEED, and PCIE_LNKCTL2_TLS2SPEED macros with 128 GT/s mapping - Add 128 GT/s to PCIE_SPEED2MBS_ENC bandwidth calculation using 1:1 Flit mode encoding (no overhead), consistent with Gen 6 - Add PCIE_SPEED_128_0GT to pcie_dev_speed_mbps() switch - Map link speed encoding 7 to PCIE_SPEED_128_0GT in pcie_link_speed[] table - Add "128.0 GT/s PCIe" display string - Add pcie_speed_requires_flit() helper for Gen 6+ speed validation with proper range check against PCI_SPEED_UNKNOWN - Widen pcie_get_supported_speeds() return type from u8 to u16 - Add Flit mode diagnostic warning when Gen 6+ speed is active but PCI_EXP_LNKSTA2_FLIT is not set Signed-off-by: Ionut Nechita --- drivers/pci/pci.c | 7 +++++-- drivers/pci/pci.h | 28 ++++++++++++++++++++++------ drivers/pci/probe.c | 3 ++- 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31f..8091f7bf30e6f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5912,10 +5912,10 @@ EXPORT_SYMBOL(pcie_bandwidth_available); * * Return: Supported Link Speeds Vector (+ reserved 0 at LSB). */ -u8 pcie_get_supported_speeds(struct pci_dev *dev) +u16 pcie_get_supported_speeds(struct pci_dev *dev) { u32 lnkcap2, lnkcap; - u8 speeds; + u16 speeds; =20 /* * Speeds retain the reserved 0 at LSB before PCIe Supported Link @@ -6020,6 +6020,9 @@ void __pcie_print_link_status(struct pci_dev *dev, bo= ol verbose) =20 if (dev->bus && dev->bus->flit_mode) flit_mode =3D ", in Flit mode"; + else if (dev->bus && pcie_speed_requires_flit(dev->bus->cur_bus_speed)) + pci_warn(dev, "Flit mode not active at %s, expected for Gen 6+\n", + pci_speed_string(dev->bus->cur_bus_speed)); =20 if (bw_avail >=3D bw_cap && verbose) pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)%s\n", diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 60542b05de0c6..4dd23f0d5de9f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -487,7 +487,8 @@ void pci_bus_put(struct pci_bus *bus); ({ \ u32 lnkcap_sls =3D (lnkcap) & PCI_EXP_LNKCAP_SLS; \ \ - (lnkcap_sls =3D=3D PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ + (lnkcap_sls =3D=3D PCI_EXP_LNKCAP_SLS_128_0GB ? PCIE_SPEED_128_0GT : \ + lnkcap_sls =3D=3D PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ lnkcap_sls =3D=3D PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ lnkcap_sls =3D=3D PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ lnkcap_sls =3D=3D PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ @@ -498,7 +499,8 @@ void pci_bus_put(struct pci_bus *bus); =20 /* PCIe link information from Link Capabilities 2 */ #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ - ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ + ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_128_0GB ? PCIE_SPEED_128_0GT : \ + (lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ @@ -510,7 +512,8 @@ void pci_bus_put(struct pci_bus *bus); ({ \ u16 lnkctl2_tls =3D (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ \ - (lnkctl2_tls =3D=3D PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ + (lnkctl2_tls =3D=3D PCI_EXP_LNKCTL2_TLS_128_0GT ? PCIE_SPEED_128_0GT : \ + lnkctl2_tls =3D=3D PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ lnkctl2_tls =3D=3D PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ lnkctl2_tls =3D=3D PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ lnkctl2_tls =3D=3D PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ @@ -519,9 +522,14 @@ void pci_bus_put(struct pci_bus *bus); PCI_SPEED_UNKNOWN); \ }) =20 -/* PCIe speed to Mb/s reduced by encoding overhead */ +/* PCIe speed to Mb/s reduced by encoding overhead: + * Gen 1-2 (2.5, 5 GT/s): 8b/10b encoding + * Gen 3-5 (8, 16, 32 GT/s): 128b/130b encoding + * Gen 6+ (64, 128 GT/s): Flit mode, 1:1 (no encoding overhead) + */ #define PCIE_SPEED2MBS_ENC(speed) \ - ((speed) =3D=3D PCIE_SPEED_64_0GT ? 64000*1/1 : \ + ((speed) =3D=3D PCIE_SPEED_128_0GT ? 128000*1/1 : \ + (speed) =3D=3D PCIE_SPEED_64_0GT ? 64000*1/1 : \ (speed) =3D=3D PCIE_SPEED_32_0GT ? 32000*128/130 : \ (speed) =3D=3D PCIE_SPEED_16_0GT ? 16000*128/130 : \ (speed) =3D=3D PCIE_SPEED_8_0GT ? 8000*128/130 : \ @@ -544,6 +552,8 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_spee= d speed) return 32000; case PCIE_SPEED_64_0GT: return 64000; + case PCIE_SPEED_128_0GT: + return 128000; default: break; } @@ -551,7 +561,13 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_spe= ed speed) return -EINVAL; } =20 -u8 pcie_get_supported_speeds(struct pci_dev *dev); +/* PCIe Gen 6+ (>=3D 64 GT/s) requires Flit mode with 1:1 encoding */ +static inline bool pcie_speed_requires_flit(enum pci_bus_speed speed) +{ + return speed >=3D PCIE_SPEED_64_0GT && speed <=3D PCIE_SPEED_128_0GT; +} + +u16 pcie_get_supported_speeds(struct pci_dev *dev); const char *pci_speed_string(enum pci_bus_speed speed); void __pcie_print_link_status(struct pci_dev *dev, bool verbose); void pcie_report_downtraining(struct pci_dev *dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 9d4eeda5ea946..031c3ec8615d2 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -774,7 +774,7 @@ const unsigned char pcie_link_speed[] =3D { PCIE_SPEED_16_0GT, /* 4 */ PCIE_SPEED_32_0GT, /* 5 */ PCIE_SPEED_64_0GT, /* 6 */ - PCI_SPEED_UNKNOWN, /* 7 */ + PCIE_SPEED_128_0GT, /* 7 */ PCI_SPEED_UNKNOWN, /* 8 */ PCI_SPEED_UNKNOWN, /* 9 */ PCI_SPEED_UNKNOWN, /* A */ @@ -816,6 +816,7 @@ const char *pci_speed_string(enum pci_bus_speed speed) "16.0 GT/s PCIe", /* 0x17 */ "32.0 GT/s PCIe", /* 0x18 */ "64.0 GT/s PCIe", /* 0x19 */ + "128.0 GT/s PCIe", /* 0x1a */ }; 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Tue, 17 Feb 2026 00:01:51 -0800 (PST) From: "Ionut Nechita (Sunlight Linux)" To: Bjorn Helgaas , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Lukas Wunner , Ionut Nechita , linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ionut Nechita Subject: [RFC PATCH 3/3] PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s) Date: Tue, 17 Feb 2026 10:01:02 +0200 Message-ID: <20260217080102.206581-8-sunlightlinux@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260217080102.206581-2-sunlightlinux@gmail.com> References: <20260217080102.206581-2-sunlightlinux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Ionut Nechita Update PCIe subsystem components to support 128 GT/s link speed: - bwctrl: Extend pcie_valid_speed() range to PCIE_SPEED_128_0GT, add PCIE_SPEED_128_0GT to speed conversion table, widen supported_speeds variables from u8 to u16 - portdrv: Switch hweight8() to hweight16() for supported_speeds to match the widened type - pcie_cooling: Add static_assert for PCIE_SPEED_128_0GT enum contiguity check Signed-off-by: Ionut Nechita --- drivers/pci/pcie/bwctrl.c | 7 ++++--- drivers/pci/pcie/portdrv.c | 2 +- drivers/thermal/pcie_cooling.c | 1 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c index 36f939f23d34e..b9125b40cb860 100644 --- a/drivers/pci/pcie/bwctrl.c +++ b/drivers/pci/pcie/bwctrl.c @@ -50,7 +50,7 @@ static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem); =20 static bool pcie_valid_speed(enum pci_bus_speed speed) { - return (speed >=3D PCIE_SPEED_2_5GT) && (speed <=3D PCIE_SPEED_64_0GT); + return (speed >=3D PCIE_SPEED_2_5GT) && (speed <=3D PCIE_SPEED_128_0GT); } =20 static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed) @@ -62,6 +62,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed) [PCIE_SPEED_16_0GT] =3D PCI_EXP_LNKCTL2_TLS_16_0GT, [PCIE_SPEED_32_0GT] =3D PCI_EXP_LNKCTL2_TLS_32_0GT, [PCIE_SPEED_64_0GT] =3D PCI_EXP_LNKCTL2_TLS_64_0GT, + [PCIE_SPEED_128_0GT] =3D PCI_EXP_LNKCTL2_TLS_128_0GT, }; =20 if (WARN_ON_ONCE(!pcie_valid_speed(speed))) @@ -70,7 +71,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed) return speed_conv[speed]; } =20 -static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds) +static inline u16 pcie_supported_speeds2target_speed(u16 supported_speeds) { return __fls(supported_speeds); } @@ -88,7 +89,7 @@ static inline u16 pcie_supported_speeds2target_speed(u8 s= upported_speeds) static u16 pcie_bwctrl_select_speed(struct pci_dev *port, enum pci_bus_spe= ed speed_req) { struct pci_bus *bus =3D port->subordinate; - u8 desired_speeds, supported_speeds; + u16 desired_speeds, supported_speeds; struct pci_dev *dev; =20 desired_speeds =3D GENMASK(pci_bus_speed2lnkctl2(speed_req), diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 38a41ccf79b9a..5ee8795107f26 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -274,7 +274,7 @@ static int get_port_device_capability(struct pci_dev *d= ev) =20 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap); if (linkcap & PCI_EXP_LNKCAP_LBNC && - hweight8(dev->supported_speeds) > 1) + hweight16(dev->supported_speeds) > 1) services |=3D PCIE_PORT_SERVICE_BWCTRL; } =20 diff --git a/drivers/thermal/pcie_cooling.c b/drivers/thermal/pcie_cooling.c index a876d64f15827..9a2e39398674b 100644 --- a/drivers/thermal/pcie_cooling.c +++ b/drivers/thermal/pcie_cooling.c @@ -75,6 +75,7 @@ static_assert(PCIE_SPEED_5_0GT + 1 =3D=3D PCIE_SPEED_8_0G= T); static_assert(PCIE_SPEED_8_0GT + 1 =3D=3D PCIE_SPEED_16_0GT); static_assert(PCIE_SPEED_16_0GT + 1 =3D=3D PCIE_SPEED_32_0GT); static_assert(PCIE_SPEED_32_0GT + 1 =3D=3D PCIE_SPEED_64_0GT); +static_assert(PCIE_SPEED_64_0GT + 1 =3D=3D PCIE_SPEED_128_0GT); =20 MODULE_AUTHOR("Ilpo J=C3=A4rvinen "); MODULE_DESCRIPTION("PCIe cooling driver"); --=20 2.53.0