From nobody Fri Apr 3 04:52:43 2026 Received: from out-187.mta1.migadu.com (out-187.mta1.migadu.com [95.215.58.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D759F145348 for ; Tue, 17 Feb 2026 07:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771311746; cv=none; b=e6E1bEuG/XoEo9zRvPRayDmM64IDVmJo8eBDv+7fafCqcvkPO9Jum8GTDN6Dn3PyrMq6MqdthxEWxkNgHFY//t6gLUUABh09C2rOWE2xtPcaPf+1JfWUxLElbx+81oDKMhjw3gNjFUkyOZgS/QvlamQ7Dxx2gMxE72tuWeouE4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771311746; c=relaxed/simple; bh=dYwkhdkE1W6S4zelRNE7KHUipC43PLafhWLvqAczjuo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MFS8gSfKAIApOn8sCZeWOXFw/UE+/fW02H3mTnrkh5ovnQTzjBkl9mBGDLYMiYpNLE4enIMRTQb1ALy03IXK3PrjYXAzokEw6VOMzjMCFInGLDokoANJI3XYroAm5MdAK/kDjU9/s6CIKRM1KrUfDYo/ida+4CUWz+Ma0sgcDmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=UF2/6JUt; arc=none smtp.client-ip=95.215.58.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="UF2/6JUt" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1771311742; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QrJL52H3P+sZw3D88DjO+0Dvn3Xt8fjuAIAZXJfqjlQ=; b=UF2/6JUtQCxjTjQrY0QVkbwMgVrmbiwJNhqfvZqyK+Uj92p+neG1hqb8EK+U7CGhqRlSL5 sSbt+Jf3m7VVk8Ih6ElF8d9bnz8Gasrf46lCsizmipOXJhl7H/3zaXPZvUC5ibEl5mIA3G zZAUWrjDaNJ3fyWEfAI336Jkhkqk2CHB+snVaa7edhu++/QLfO1oCHhNV/2VC+VKb9d1KY BvPBxcnz0/HQ+OyaVCs2rCz3hQzKzQ0o2Qz61ECd8H+ZroAH9PVu7Bzk+DlmWY4YD6Sa4t QIRfSiBCuVxXAVQiAjqjwe2cgRzJEIUuKgaxDhGmUByENs1Jm26foCBWeQf3iQ== From: Val Packett To: Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-kernel@vger.kernel.org, Val Packett Subject: [PATCH 3/4] drm/panel: himax-hx83102: Add support for Holitech HTF065H045 Date: Tue, 17 Feb 2026 04:00:11 -0300 Message-ID: <20260217070121.190108-4-val@packett.cool> In-Reply-To: <20260217070121.190108-1-val@packett.cool> References: <20260217070121.190108-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" This 720x1600 panel is found in several Motorola/Lenovo smartphones like the Moto G9 Play (guamp). The initialization sequence is based on the datasheet. Add it to the existing HX83102 panel driver. Signed-off-by: Val Packett Reviewed-by: Neil Armstrong --- drivers/gpu/drm/panel/panel-himax-hx83102.c | 86 +++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/= panel/panel-himax-hx83102.c index 1d3bb5dca559..34e0e956db48 100644 --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c @@ -701,6 +701,67 @@ static int starry_2082109qfh040022_50e_init(struct hx8= 3102 *ctx) return dsi_ctx.accum_err; } =20 +static int holitech_htf065h045_init(struct hx83102 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + msleep(50); + + hx83102_enable_extended_cmds(&dsi_ctx, true); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x22, 0x44, 0x27= , 0x27, 0x32, + 0x52, 0x57, 0x39, 0x08, 0x08, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x00, 0x06,= 0x40, 0x00, + 0x0e, 0xae, 0x38, 0x00, 0x00, 0x00, 0x00, 0xf4, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x01, 0x58, 0x01, = 0x58, 0x01, + 0x58, 0x03, 0x58, 0x03, 0xff, 0x01, 0x20, 0x00, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00,= 0x00, 0x00, + 0x10, 0x00, 0x17, 0x00, 0x63, 0x37, 0x0e, 0x0e, 0x00, 0x00, + 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x16, 0x4e, 0x06, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x04, 0x0c, 0xb2, = 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x24, 0x25, 0x18,= 0x18, 0x19, + 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x06, 0x07, 0x04, 0x05, 0x18, 0x18, 0x18, + 0x18, 0x02, 0x03, 0x00, 0x01, 0x20, 0x21, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x00, 0x09, 0x16,= 0x1f, 0x28, + 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 0x91, 0xa0, 0x9e, + 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 0x7f, 0x00, 0x09, + 0x16, 0x1f, 0x28, 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, + 0x91, 0xa0, 0x9e, 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, + 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xff, 0x14, 0x00, = 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff,= 0xff, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa,= 0xaa, 0xaa, + 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x70, 0x23, 0xa8,= 0x93, 0xb2, + 0xc0, 0xc0, 0x01, 0x10, 0x00, 0x00, 0x00, 0x0d, 0x3d, 0x82, + 0x77, 0x04, 0x01, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x00, 0x53, 0x00= , 0x02, 0x59); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x00, 0x04,= 0x9e, 0xf6, + 0x00, 0x5d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x42, 0x00, 0x33, = 0x00, 0x33, + 0x88, 0xb3, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x20, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x7f, 0x03, 0xf5= ); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + + return dsi_ctx.accum_err; +} + static const struct drm_display_mode starry_mode =3D { .clock =3D 162680, .hdisplay =3D 1200, @@ -833,6 +894,28 @@ static const struct hx83102_panel_desc starry_2082109q= fh040022_50e_desc =3D { .init =3D starry_2082109qfh040022_50e_init, }; =20 +static const struct drm_display_mode holitech_htf065h045_default_mode =3D { + .clock =3D 90720, + .hdisplay =3D 720, + .hsync_start =3D 720 + 40, + .hsync_end =3D 720 + 40 + 40, + .htotal =3D 720 + 40 + 40 + 40, + .vdisplay =3D 1600, + .vsync_start =3D 1600 + 186, + .vsync_end =3D 1600 + 186 + 2, + .vtotal =3D 1600 + 186 + 2 + 12, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc holitech_htf065h045_desc =3D { + .modes =3D &holitech_htf065h045_default_mode, + .size =3D { + .width_mm =3D 68, + .height_mm =3D 151, + }, + .init =3D holitech_htf065h045_init, +}; + static int hx83102_enable(struct drm_panel *panel) { msleep(130); @@ -1069,6 +1152,9 @@ static const struct of_device_id hx83102_of_match[] = =3D { { .compatible =3D "starry,himax83102-j02", .data =3D &starry_desc }, + { .compatible =3D "holitech,htf065h045", + .data =3D &holitech_htf065h045_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, hx83102_of_match); --=20 2.52.0