From nobody Fri Apr 3 03:15:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F20422D9496 for ; Tue, 17 Feb 2026 07:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314761; cv=none; b=ZlOUIZUjsbMez/14L6a+iMjT9ev4Wf311WLEgy7B5wwzmBFsiqCaF3zQXL+rSOnm8g2BXe62PNcYVs9/HvK7tbJumkp6iusEz5M1cjfy1bwZzNyziSYE+ri3T3VnSRWxpTiusOpHH/fiocPtngEWj459twcHShxRrZKAP3RbWzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314761; c=relaxed/simple; bh=QVTybmkdt7ET3baJ/2CwGUw6pY0Jc7HwG1B/0cUaPQ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X/ABw1dfrtAmDD22jnP/c5ZeLMXyWobjXXEmXutLQtAX44Hnz3nNmsUZ1eNE/qTxUb2YfRg7wYbzkq32CdQLjFfQsml06ZklXNSmjIMfisxXTPasR1TB3y6qURPjl94550/w475HS3kuvdfC7vtoFl7jef1UdDPuXaeRQZNNTJg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mFfxX7aj; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=AjzOvw4T; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mFfxX7aj"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="AjzOvw4T" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61GL7nsu850080 for ; Tue, 17 Feb 2026 07:52:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= v2Wg2VwBlodi0lED0h/KpQ0d9RtRO+Iy3lC8si0JyDc=; b=mFfxX7ajYL7sq/Uv HNIzADUV5wK11ET5MQhLYMkEJGvNxhXo8xbKisYoOQXRQferoEkfucvIHzGn+j47 s8opl6/lXURIuxFXZJpolXLV9tsG5Ijrc9A4IwaY3Npl31eHWEvL138Xr27L7XzQ JuEB5zkhMg7ToQJse0FvOUAsIRjtwQefDiYa7s9oDdtrMJsKqkLQnYj2mr4ktL/v mN/tfSoqnDThZlqeJ+Of/EEGsqYHWjmfJbZ9F2cRV7upD7VGsrx66V2SDYePgz8F rRZgejw+cXV9o4J+D9ntdGYf7ANP5lP/MtBemEaj6gjod+UUtIQCtJE7sT6Z1P8m 5CFW6A== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc6nrsgu2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 07:52:38 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-8cb403842b6so2669351485a.1 for ; Mon, 16 Feb 2026 23:52:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771314758; x=1771919558; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v2Wg2VwBlodi0lED0h/KpQ0d9RtRO+Iy3lC8si0JyDc=; b=AjzOvw4T1Lqr6PQ0I98xsVUEhqHod5TPSGwHIgySw+yZSEIDCINM5mXtRMqJUmER7R h/HZvqRNV3/HKu3eX5KSNf4VPgNTjCSkOqLli4OY8zLFW5RhvARlCgbHVAuerPpGzvyi YIb9fF+KSNuJ4fe9r8SVhD4BIpyeUNLZRjo+Tshul9XxAjg+FJsJL/EE62AYXz9fEIxh VwOnRhmpGKhxvItUOG7+h+ljtvUA1DV91xT4AqumVaSJe47d790nHxSmb7sFy+hjBeSI mmCaHc/qtyt+8j/i+euEnqJQaExAQsuiL6rb3wUbwHXIpszPaHLHIlecQiRBFFmKZaoe eYag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771314758; x=1771919558; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=v2Wg2VwBlodi0lED0h/KpQ0d9RtRO+Iy3lC8si0JyDc=; b=iFE6GeJ1ZL+AFpyod7Ycakqi+lnFmiRwyDhp0CqFnySOOhy6WbiZGFcpPYy0fdTDWN V+6WSIMzlsUTrmfYadmru3PlkyjYvHqr5s3TEOnRfgXUvXl9RmvbkxYxEKniFDqkibaQ euURSR55EoKCUXX+y2MD2YB4X3t60gDIS9nxjIr9haRYo95ZtDcKqNZn7AuS8jO9D+kD IxagWc1J300N9j89yxVufpzaRvUu9EUFHCp+tWQliPO3zgL9U8332SmFwl1RxR/wsg/9 Ozifz5paRVIKrTmsH9UaGaAgMnlzvX79bZczmKMSsjHwAfUP7doRE1+Yg28XDYFadcQl Iylg== X-Forwarded-Encrypted: i=1; AJvYcCX23VhJGLGjPPz6CVSOThAp8qUUzA4Wg0W3YVnsowXYMOgAELOOs30rvPoPOLO3YwAbvOxN+HseyV7LtVk=@vger.kernel.org X-Gm-Message-State: AOJu0YymEHtEoAY6xKybysL85QeQn53LFLQMvoq4fvn1PRHXCeRjWZwm bfOhDvMCz8mS9iWIZFjx46Vb7C47CPxI1O8VWp7SjMlM1owwVSedFve/1V9O9ldjosP4pZe/73U 9yugtHU7L8z3pwBYB1beFyGXqFxe53V+P0SsDJ23/tJF5ww5+8Nm1IWVUpm6g2mYZlmo= X-Gm-Gg: AZuq6aIwzyzVsO9cbOgr7DeDstidwCbdDmR3wIcFD8AJv0d2ZfN+sJ+VlU57oNEwyxK cJmRS1bXJ0xiXDeVcR6pksh/V7I59GgC/sVL8savotvYwBBG/qH71LDRdqokILQQqAoQvYwNYNt 6dxwN2A1y21Ri4O1Csoq06BNw6rJLP6sJF0txYIrTqDj5vzcJ9WIwm5foI8vYLG8BK1odNLLe4I qCK0Nyk5yiaNSqZQoItWztwFygud3O2BgJuH6ETjRMNQ4QLt0nb2cvDXv89enwdgi98e5pJZvQr SwSN3wUWDV6zDFo4jILwbOAufUQMyeSkhwz1Fu6j5i/tfl/ZpcCFLVqTs1FVzkA9Xdl5sVAiOQg Tq3qS+mgGuTEUWt8dq4EC0LomRnxR3g== X-Received: by 2002:a05:620a:3187:b0:8c7:995:b961 with SMTP id af79cd13be357-8cb4243d406mr1427105685a.58.1771314758090; Mon, 16 Feb 2026 23:52:38 -0800 (PST) X-Received: by 2002:a05:620a:3187:b0:8c7:995:b961 with SMTP id af79cd13be357-8cb4243d406mr1427103585a.58.1771314757574; Mon, 16 Feb 2026 23:52:37 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ac9d77sm29860229f8f.33.2026.02.16.23.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 23:52:36 -0800 (PST) From: Abel Vesa Date: Tue, 17 Feb 2026 09:52:21 +0200 Subject: [PATCH v4 1/6] dt-bindings: clock: qcom: document the Eliza Global Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-eliza-clocks-v4-1-5d09f28d4251@oss.qualcomm.com> References: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> In-Reply-To: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=10237; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=vxOdVgdl1Oawmc9RM/XHsJZ9J2wuLHt6IlyUoblJpYQ=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBplB46wKagruv56/F+eVwd2xlkKFHujTmwEi7Ey pVZ3b18MVCJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZQeOgAKCRAbX0TJAJUV VvScEACC8jnNnyU3E+A1piWuKBF8ERFYcLm+yXPpYC1NEFGHXjgz4cxBvc6indDnIe3ZE+z3EDp i+ZanWO9EGe6bN8vJSmqT2CAGFHw2llEaaHqxEbY4upryT2f6bQRk1LBGTNU9AFW0T1A6Y9YVaM YKfhB936fjyFYk3DeQJiJ1/4tyLVkLwPu7JDa8Nb/BJL6YSdXkhDGjFFJy7cTdpDkeuy1I/Bwot cdTZlxpRS3BiCuvAsLYCyoiByTgi25FOGgTFRoIMq74vgoMlHg0ZGPIpkiXvx2NAZ6DZ6cYLY6p yAr4FjCgf1txcvolM/eVueZMTFjGKl+1TS8Tgwg3lDuK0QUXPIySviGbxD1D9PA+A9irIkOVMGq yswabamLJdQOIxjS8isr2TnDnQiEQqMC74aErvKL+V9GgrX1c1n0se/DlxIbeeBXCdZ1bq3KZAM lKHAPoGrws1Eb3Ml6JnjSbGty/UhjfnPWJk107/qevYnkXkrwCGFuQoTsGtrDQ5NdPk8hWNU174 kTTMokHeupalerOgUQxwDABkcHDaLMsFnNSfUw4ATl8uRuyj5Exeeg02eBbv55F2Nni4Mu/In7B QWg9XlQIoPzlY31c/KNuXWKzLZIhBNaPAuFnhsIxmgzFqEDYang8jSCtVE27i0rMKgIkmlS2AXE 5yHB2lRTczpJq2Q== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Authority-Analysis: v=2.4 cv=XKo9iAhE c=1 sm=1 tr=0 ts=69941e46 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=6H0WHjuAAAAA:8 a=QqclT2NS3jCD4ft7SfEA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA2NCBTYWx0ZWRfX5IsxlUQHvItE STwbJvakUkanyrOPaet/6GExvfcKY9UGyEmx15Tod4yxiu13M9NZiN8SanmwZwt5MJrfhx8snHy Yxq70Q2iNXeMY3Gn5kP7j6++C1qXbRNkalo4oEvgMCeTJdn8Ty0fShPIna//33DhPJ0+rkB72/J l+TqvCciyyDlvlYLV34GJuxIK6714mr5gJBGM9tDKFppEHQqKd74o64UH3Mk8wAFfEbVL7arnS2 e2wSwnIJaXiBBYJdUgWTN9z+kyzmNXdoOudSjVqZtHArnBdPL3MSnMTqQbCZJOdk6p978/O+rBk 7FvU+wjmRME94t8JB+0tR1UdjiNPUKKddNevyxM7IHI1FKICc+iexMWVbcvMmr6aGaag1AAZ/Vh uOvTk6Z+Au6NwulitO0XZWlw5nNYB9bzbTZyIorkPoLrxuDVDMZphl5kQwc9XWvd7AvbQHGydC/ d19uI/Dj4UAq/vrllCg== X-Proofpoint-ORIG-GUID: suJGS-XdIDDTvJEdc3_ERAMfZMGt-SzM X-Proofpoint-GUID: suJGS-XdIDDTvJEdc3_ERAMfZMGt-SzM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170064 From: Taniya Das Add bindings documentation for the Global Clock Controller on Qualcomm Eliza SoC. Reuse the Milos bindings schema since the controller resources are exactly the same, even though the controllers are incompatible between them. Signed-off-by: Taniya Das Signed-off-by: Abel Vesa --- .../devicetree/bindings/clock/qcom,milos-gcc.yaml | 9 +- include/dt-bindings/clock/qcom,eliza-gcc.h | 218 +++++++++++++++++= ++++ 2 files changed, 225 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml b/= Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml index cf244c155f9a..60f1c8ca2c13 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml @@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Milos =20 maintainers: - Luca Weiss + - Taniya Das =20 description: | Qualcomm global clock control module provides the clocks, resets and pow= er domains on Milos. =20 - See also: include/dt-bindings/clock/qcom,milos-gcc.h + See also: + - include/dt-bindings/clock/qcom,eliza-gcc.h + - include/dt-bindings/clock/qcom,milos-gcc.h =20 properties: compatible: - const: qcom,milos-gcc + enum: + - qcom,eliza-gcc + - qcom,milos-gcc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,eliza-gcc.h b/include/dt-bindin= gs/clock/qcom,eliza-gcc.h new file mode 100644 index 000000000000..3e0ff3fb69f6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-gcc.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2 +#define GCC_BOOT_ROM_AHB_CLK 3 +#define GCC_CAM_BIST_MCLK_AHB_CLK 4 +#define GCC_CAMERA_AHB_CLK 5 +#define GCC_CAMERA_HF_AXI_CLK 6 +#define GCC_CAMERA_SF_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 +#define GCC_CNOC_PCIE_SF_AXI_CLK 11 +#define GCC_DDRSS_GPU_AXI_CLK 12 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 13 +#define GCC_DISP_AHB_CLK 14 +#define GCC_DISP_HF_AXI_CLK 15 +#define GCC_GP1_CLK 16 +#define GCC_GP1_CLK_SRC 17 +#define GCC_GP2_CLK 18 +#define GCC_GP2_CLK_SRC 19 +#define GCC_GP3_CLK 20 +#define GCC_GP3_CLK_SRC 21 +#define GCC_GPLL0 22 +#define GCC_GPLL0_OUT_EVEN 23 +#define GCC_GPLL4 24 +#define GCC_GPLL7 25 +#define GCC_GPLL8 26 +#define GCC_GPLL9 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GEMNOC_GFX_CLK 29 +#define GCC_GPU_GPLL0_CPH_CLK_SRC 30 +#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 31 +#define GCC_GPU_SMMU_VOTE_CLK 32 +#define GCC_MMU_TCU_VOTE_CLK 33 +#define GCC_PCIE_0_AUX_CLK 34 +#define GCC_PCIE_0_AUX_CLK_SRC 35 +#define GCC_PCIE_0_CFG_AHB_CLK 36 +#define GCC_PCIE_0_MSTR_AXI_CLK 37 +#define GCC_PCIE_0_PHY_RCHNG_CLK 38 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 39 +#define GCC_PCIE_0_PIPE_CLK 40 +#define GCC_PCIE_0_PIPE_CLK_SRC 41 +#define GCC_PCIE_0_PIPE_DIV2_CLK 42 +#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 43 +#define GCC_PCIE_0_SLV_AXI_CLK 44 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 +#define GCC_PCIE_1_AUX_CLK 46 +#define GCC_PCIE_1_AUX_CLK_SRC 47 +#define GCC_PCIE_1_CFG_AHB_CLK 48 +#define GCC_PCIE_1_MSTR_AXI_CLK 49 +#define GCC_PCIE_1_PHY_RCHNG_CLK 50 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51 +#define GCC_PCIE_1_PIPE_CLK 52 +#define GCC_PCIE_1_PIPE_CLK_SRC 53 +#define GCC_PCIE_1_PIPE_DIV2_CLK 54 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 55 +#define GCC_PCIE_1_SLV_AXI_CLK 56 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 58 +#define GCC_PCIE_RSCC_XO_CLK 59 +#define GCC_PDM2_CLK 60 +#define GCC_PDM2_CLK_SRC 61 +#define GCC_PDM_AHB_CLK 62 +#define GCC_PDM_XO4_CLK 63 +#define GCC_QMIP_CAMERA_CMD_AHB_CLK 64 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 65 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 66 +#define GCC_QMIP_GPU_AHB_CLK 67 +#define GCC_QMIP_PCIE_AHB_CLK 68 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 71 +#define GCC_QUPV3_WRAP1_CORE_CLK 72 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 73 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S0_CLK 75 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S1_CLK 77 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S2_CLK 79 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 80 +#define GCC_QUPV3_WRAP1_S3_CLK 81 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 82 +#define GCC_QUPV3_WRAP1_S4_CLK 83 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 84 +#define GCC_QUPV3_WRAP1_S5_CLK 85 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 86 +#define GCC_QUPV3_WRAP1_S6_CLK 87 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 88 +#define GCC_QUPV3_WRAP1_S7_CLK 89 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 90 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 91 +#define GCC_QUPV3_WRAP2_CORE_CLK 92 +#define GCC_QUPV3_WRAP2_S0_CLK 93 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 94 +#define GCC_QUPV3_WRAP2_S1_CLK 95 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 96 +#define GCC_QUPV3_WRAP2_S2_CLK 97 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 98 +#define GCC_QUPV3_WRAP2_S3_CLK 99 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 100 +#define GCC_QUPV3_WRAP2_S4_CLK 101 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 102 +#define GCC_QUPV3_WRAP2_S5_CLK 103 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 104 +#define GCC_QUPV3_WRAP2_S6_CLK 105 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 106 +#define GCC_QUPV3_WRAP2_S7_CLK 107 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 108 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 109 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 110 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 111 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 112 +#define GCC_SDCC1_AHB_CLK 113 +#define GCC_SDCC1_APPS_CLK 114 +#define GCC_SDCC1_APPS_CLK_SRC 115 +#define GCC_SDCC1_ICE_CORE_CLK 116 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 117 +#define GCC_SDCC2_AHB_CLK 118 +#define GCC_SDCC2_APPS_CLK 119 +#define GCC_SDCC2_APPS_CLK_SRC 120 +#define GCC_UFS_PHY_AHB_CLK 121 +#define GCC_UFS_PHY_AXI_CLK 122 +#define GCC_UFS_PHY_AXI_CLK_SRC 123 +#define GCC_UFS_PHY_ICE_CORE_CLK 124 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 125 +#define GCC_UFS_PHY_PHY_AUX_CLK 126 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 127 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 128 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 129 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 130 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 131 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 132 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 133 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135 +#define GCC_USB30_PRIM_ATB_CLK 136 +#define GCC_USB30_PRIM_MASTER_CLK 137 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 138 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 139 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 140 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 141 +#define GCC_USB30_PRIM_SLEEP_CLK 142 +#define GCC_USB3_PRIM_PHY_AUX_CLK 143 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 146 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147 +#define GCC_VIDEO_AHB_CLK 148 +#define GCC_VIDEO_AXI0_CLK 149 +#define GCC_VIDEO_AXI1_CLK 150 +#define GCC_VIDEO_XO_CLK 151 + +/* GCC power domains */ +#define GCC_PCIE_0_GDSC 0 +#define GCC_PCIE_0_PHY_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_UFS_MEM_PHY_GDSC 4 +#define GCC_UFS_PHY_GDSC 5 +#define GCC_USB30_PRIM_GDSC 6 +#define GCC_USB3_PHY_GDSC 7 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PCIE_RSCC_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUPV3_WRAPPER_2_BCR 19 +#define GCC_QUSB2PHY_PRIM_BCR 20 +#define GCC_QUSB2PHY_SEC_BCR 21 +#define GCC_SDCC1_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_UFS_PHY_BCR 24 +#define GCC_USB30_PRIM_BCR 25 +#define GCC_USB3_DP_PHY_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_SEC_BCR 27 +#define GCC_USB3_PHY_PRIM_BCR 28 +#define GCC_USB3_PHY_SEC_BCR 29 +#define GCC_USB3PHY_PHY_PRIM_BCR 30 +#define GCC_USB3PHY_PHY_SEC_BCR 31 +#define GCC_VIDEO_AXI0_CLK_ARES 32 +#define GCC_VIDEO_AXI1_CLK_ARES 33 +#define GCC_VIDEO_BCR 34 +#define GCC_CAMERA_HF_AXI_SLP_STG_ARES 37 +#define GCC_CAMERA_SF_AXI_SLP_STG_ARES 38 +#define GCC_CAMERA_HF_AXI_SEL_SLP_STG_ARES 39 +#define GCC_CAMERA_SF_AXI_SEL_SLP_STG_ARES 40 +#define GCC_CAMERA_HF_CLK_EN_SLP_STG 41 +#define GCC_CAMERA_SF_CLK_EN_SLP_STG 42 +#define GCC_CAMERA_HF_CLK_EN_SEL_SLP_STG 43 +#define GCC_CAMERA_SF_CLK_EN_SEL_SLP_STG 44 + +#endif --=20 2.48.1 From nobody Fri Apr 3 03:15:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A899E2DA776 for ; Tue, 17 Feb 2026 07:52:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314762; cv=none; b=pSZUDZQ/xSfLJ/gVBmy21uhoA8GgUjvpD6/2LffUDKYFxBbKYMjn56qj2f4u2iaAJbFuZ2BgIsGAOVOlJVR18oDe6qpBDMD33+RXeAd+RtxH8azEidF8KOjdu45DQJ/a6OJ1lRRwXXBkztHogGP1nbiBYHFeu0oY/xWfFn0v6Vo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314762; c=relaxed/simple; bh=+X74KMWb2lVjQ9fnowKj6jei9ytZdwOYWqFCEBJ/bZs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k9CRDbr1xVFsjQB9ugqG1bK7C3LPwvohK3CbbT0suxsvKap72ZDqusXbA+Q3qVAuns6t2ukOqJpHDMcj5yDxNhW7BzfSXqLO8QFawb0u8YR2RuzEdVg2fkTW+Rb9gjPDuR58vMiH0Z28mELrrrplEU7+4vN62UgYD67C4bcwIPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=kNJc8VVR; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jr+F1Bed; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="kNJc8VVR"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jr+F1Bed" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61GFtRG9297136 for ; Tue, 17 Feb 2026 07:52:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= fB98BuCBiJhrIm8NgYodeQbl3q2SBFUZLmymOwOVjDs=; b=kNJc8VVRHNJkBpNx 3GvJo5HUQnF7+5yIygZs88CjO0yep1DnWnZvAn7G6fvHfQyi8GELXDGAb1wpOej5 dYMs9kk3uRsZ7+93Uixk8r3TRjmYbbWx7UjlMznxVoQR0AU8q46HhKmCuOCaugun p+GZShFEHyAKHGGLCIb57V8nufWYlOg6XQrEj4W7nEw1olzViaJJQRAhwIu2fA0V h6eYlId/B7mEtDofZa8qpzKq6UBNmB8kxFuZMHJd1RSuiVtZEyQs0loZh6PLG7eL m6rHTJb/kTkQO7GI5JuoqzobiV1QtlOkw1fekrAEAxeu4oe5Ku4gkRt7l4gXAwjd oilXLw== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc6a9sjju-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 07:52:40 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8c70b6a5821so2199354085a.0 for ; Mon, 16 Feb 2026 23:52:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771314760; x=1771919560; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fB98BuCBiJhrIm8NgYodeQbl3q2SBFUZLmymOwOVjDs=; b=jr+F1Bed29IJngrvjHzRrx7dTX9a6s7Q/8ODc5mTjNUbE0x+v9yKBAtLpLYeKXhbXC se+vw1De5cFdqQ+XYWQJJsQdxIU2UDYW1sTHwmcXaAY0luhuM34VBG0nWf9LdpCe3gz+ 7zZpNXBQ3A6fLwfJXmLnnxzO6LgL6+i3DvgBVlNjfWC/UjylVjyi0Tby/EXe214tLmiF BeuucFQEAW72F2ZP2aG7ZFZtJB1Qdq8WzAiFDentySEfzyTTrnBhg4W1n2AiPNGu7eDj /yZMztzeuNTuHSJQ6sBmxLknR44hfcZtf3SKKAJ38LOFM2Gvj5lNxVVVMvBi6/s9sU2D po+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771314760; x=1771919560; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=fB98BuCBiJhrIm8NgYodeQbl3q2SBFUZLmymOwOVjDs=; b=c7rPlO9v5xWX1FjB+v6uO9TRSf5tl2SrJNUkK0ImdU0KHrHPZiYMh8ZF84edLnpIEj trz4C/oKZbKe2orjqWQIiMXr5iLZlknXE0ILbEX0KuuCe+U+HWRyCMiDz88d2hvkkP1w KjjNMKcfm4yelqNEJxUhQIGyOyMhwgHp2HkM5nCXaa2JG4VEKxGEiwfRsWpEHzTaQ7A8 zm9jq1BQb620MSYyVmAeXgUKPc7HeYc1LklNfiyZ2hFdYH24jYav38P1m3Mh2wxvy3Oj DtLdK/m+ZSSAdKpj9rHH1lBUj81g+os9Ny4TgHKdp7UmgGswUbQQvBRJvUbbsmi4g6ET Z2CA== X-Forwarded-Encrypted: i=1; AJvYcCVbKSyU/9fT9RbNvLczB/XljBIn0fdsrNaBn6a0EGUo+gCaVOAsZ/+W9bYNzNVXd5DC2g9D5JoJeWNhvo4=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9vQjheAyK42AscU604KGvlrPkH+yWveEXe/A9HEZLTrchnu0Z tHoHDopyOxoqMCsrEcEOBJUkFgrJgGFCGCvbFkWb3vRt6IzSFSJLPBfUVHiXbwYFUeeRE/FHx2+ NLNdUriRe9t6eq6cgflReKjKrS8m0uKavfFhaLuWmbEX9OTE79dFyiqDtJtyApjfTJiU= X-Gm-Gg: AZuq6aLIz7l37V2O9BMWelaMrDXzVfQfpbf44L0WZBun+rgCtz1IEwnzPHMA4oeVEBe 2te1rQy+meKvt/S94GyULhbN7iquvBIHJdbPmFxkVlUGpTAiEz5SUCZ0OUVFDM7KPgEd98uzQ0+ cLPREwgk3+iKpN4d0Fog7Yn7u02wCL8XrkISDhY9MhiGCLyKz5P51dv9sD/ujITQmQA//fSoNMl SzQIw0lJlovdozpXXjLrnP+7nQj6owbFRkD71/hoxawq8QSEZkgHid1cCWXk7VM8yydwj8nrZF/ qJfF6ZlkN3vSDY7zLmZqc19rR3az8QYrV31AJ9+SYix1IHZ4xfPaZynSVlN60yazdqEzNRp393B dpSgmT6H+PnaZL011COZdkvVlvRrnBQ== X-Received: by 2002:a05:620a:319f:b0:8cb:104b:bf4 with SMTP id af79cd13be357-8cb424e0b11mr1585372885a.90.1771314759942; Mon, 16 Feb 2026 23:52:39 -0800 (PST) X-Received: by 2002:a05:620a:319f:b0:8cb:104b:bf4 with SMTP id af79cd13be357-8cb424e0b11mr1585371085a.90.1771314759333; Mon, 16 Feb 2026 23:52:39 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ac9d77sm29860229f8f.33.2026.02.16.23.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 23:52:38 -0800 (PST) From: Abel Vesa Date: Tue, 17 Feb 2026 09:52:22 +0200 Subject: [PATCH v4 2/6] dt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-eliza-clocks-v4-2-5d09f28d4251@oss.qualcomm.com> References: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> In-Reply-To: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=2001; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=AauMYzLc6gTEXz/GOQcSBdK6m37250bGHySZPyTqHNw=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBplB47RwyeJ2mJ5FUwuIfaBvT9Lauhk8AoJjZwz XgQGsqjH8qJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZQeOwAKCRAbX0TJAJUV VkXdEACtgvqViLh0Z2wfrK+aZugUoSHnNX0WW9aQWspU4828K1Bi7ZuOBSo4oTbr33r/3vsAE2x yIWB7gCOtCC268fyrXVwfGp9W9Ahl/XiYX5qqff24+r0tK4lo7Dh1hK1lMAMgAEts2H7mmhclc2 tkmlIlBZlg8TVZ3eIJ2R0+fOOyUbYO7XUBae8fk4QYKJZlD68x4DTBzQ/O+iZxA68dirTz/unsF GRIT9USjuckHKN7VU3gHhOtsSBp99+HXJ4G+IbazkGX1Yccuweudj7rYArBoD7e4dhSm+XWgQpp KLHOnj3LmEulmw/2ryUlzuhQvgccK5TO3DjYLX2fEJTvVMDc1EZ0kce5TPgM8bi4CmXK8Vmocva 1lvhtOx1CgvGdJUylmmfPX45NOmnKO7DFp+qi6Eorwrts4x7OpghOBMqbzgVYPYQniyg9TTuD28 w3hRLumurEaoKO43CFnUhcA2livWHx673DmhqejFdLXv+joJsJGY3fRd0XIzXKmgcKOZ5KplWdr xyH9cP2FZzaT/WNWBEtEtzqugA9gjfBwWju5H/O80bxlvoqhBEWbruVaOldvPPhXpRqhu49XOfK elCCncyireDFSBXO4FcoTaop7ljwQmDIUIORLoUUrnzc5VAvhrM8c5NehxqqI8UI6k47fAEjkr2 Y6qQPQYrlJ2lE/A== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA2NCBTYWx0ZWRfX3auxniX5RO1V hv+zbiJw2tZtUCbRyNPwvSjtU25Kg13l8yf8UAXauJIgNKYcWskejtQ6KdNYul9UxkTKt2+lq+g 009LwJRqQONkaeRCw8kNzK2ljVn0zsUCfUDjUKncsCqTQirWk52s7JeWElPOaWBwOo4ZQXej6g9 N9mHP+TIThs4IUJknAi5LaO9zIA5JjiaBxYzqZvXE1NgnOotSOfqgGWL93G76KWLXdBwc5Of9Ft 9IDIkxcyM/cveUCKw4Q27a7fXIojy1QwQ+4y3HG6oixwD2wFgvkpj/F8X6sSyZOJjsCZ1nppgvQ ovBpzxHXiC9ovJCQOHpsBVoJnM5sRoKlQwo9Hy/qof2V6CF8Y+cvUKJkESdJwZCZtk/KkxrRkY/ ukwj9jBEQ347M7kasx7/8eQlRBTCLayl5WVCpaNYUhI6cv6ProDWXgZwcsBU3jg66FrXsWqv4VT MjmQXRBHUpWwiOS6lug== X-Proofpoint-GUID: aCO01poyInYK4MDVzPNXnaL0lq__BkAl X-Proofpoint-ORIG-GUID: aCO01poyInYK4MDVzPNXnaL0lq__BkAl X-Authority-Analysis: v=2.4 cv=TPNIilla c=1 sm=1 tr=0 ts=69941e48 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=UWqaS1yFD4rTGqj9qVkA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170064 From: Taniya Das Add bindings documentation for TCSR Clock Controller for Eliza SoC. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- .../devicetree/bindings/clock/qcom,sm8550-tcsr.yaml | 2 ++ include/dt-bindings/clock/qcom,eliza-tcsr.h | 17 +++++++++++++= ++++ 2 files changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 784fef830681..ae9aef0e54e8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -15,6 +15,7 @@ description: | power domains on SM8550 =20 See also: + - include/dt-bindings/clock/qcom,eliza-tcsr.h - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h @@ -24,6 +25,7 @@ properties: compatible: items: - enum: + - qcom,eliza-tcsr - qcom,glymur-tcsr - qcom,kaanapali-tcsr - qcom,milos-tcsr diff --git a/include/dt-bindings/clock/qcom,eliza-tcsr.h b/include/dt-bindi= ngs/clock/qcom,eliza-tcsr.h new file mode 100644 index 000000000000..aeb5e2b1a47b --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-tcsr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H + +/* TCSR_CC clocks */ +#define TCSR_HDMI_CLKREF_EN 0 +#define TCSR_PCIE_0_CLKREF_EN 1 +#define TCSR_PCIE_1_CLKREF_EN 2 +#define TCSR_UFS_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif --=20 2.48.1 From nobody Fri Apr 3 03:15:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 324482DBF5E for ; Tue, 17 Feb 2026 07:52:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314765; cv=none; b=X8MXt3xsbTplcy+ZjxW3VZTbKHhJ4K9+0EP+PL5QcHL9jPj/p0JwGo3iJ/T7V10NZD4o6dSrCVF4R43H/TAwYw8uC36l4vOJSsVlwV0UpGpfP7Act3AQnLD8szvkarDHMRJbu7arRJljW37/3VjQojmy765D7WRT/FVdWr2hZgo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314765; c=relaxed/simple; bh=ljNAanNsQX3haUgfK2VNArM8xCcxc69jvU1l9y/w+to=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MwfNRr7ad50KoR7IejHx4fsSjw1BxuaOd90V+3JNdLlbL/ZukyfdVPaQndwNjh3d9IkahmeHHxIYDCLvnIC26jWDeuKvbATWtZKKjs3NmYr4yraGr2HskC+G+ZFJlRz8CnBAboExTApECWiyY7dfmQAG6I+jygJVkhv6DxUeu14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=g93e3sep; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bdZt3y0s; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="g93e3sep"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bdZt3y0s" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61H1lhBE1441859 for ; Tue, 17 Feb 2026 07:52:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 44Jhd6TeZL4PPKiVLdK78+OKBcNZjGbvEfGHis15NrM=; b=g93e3sepjWrNTdhq /KVLdzNZiaWehs0tpxuGBjv5+0uS3LkXr1LZbeqzjGBIE914a6JkIXDqv5maLfvX 66WHMwfS004FDtnb6riOiKvwYRLzD0vhZuf9Fd2T981Rl9m0GtyPLQDQYH5prz5h Pm7liXqMBHG77A1dxf7wdISX8NaC6MvCVjEuPnrgtKDB2LVU2IzokOQhC5QsG6+N lhCc892In4brusw8D9lRv1ZjodQgQpGj79mNw1Ym/vqEP3iWm3YQXEuvTlRN8EP3 8zhu4bZlJhYIwgxo7HhIot6hHlnmMl9MqFAH4TQM01PPO+kgJYbK7KLOTyi2VJza qPBeFg== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc6a9sjjw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 07:52:42 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-8c71655aa11so3268093985a.3 for ; Mon, 16 Feb 2026 23:52:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771314762; x=1771919562; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=44Jhd6TeZL4PPKiVLdK78+OKBcNZjGbvEfGHis15NrM=; b=bdZt3y0sl6tFonuaXSmZoh1fPT5+nd7KYUhDCqaJPxyBzDlJ75Q4Q4iyhilaUU/nPn 8DTWF2DUL/B/0S3gZ4H2MHIFm4xxG14AkMoghNGVA9ioPqIpwtpRH9+gXKPuVw4+HZ5k NScA8u5rxX7DIAvVnHcw3VE2wKmDllLI6rO2B+lCv2iSpQOC0cJXy2wD9ox7a3guEw6H 5u3bQUGLvpro/fUarL6oplwCvBmcSEOOLI1laq6vuBtKWn6z2fQxlmKrjxEc0isHaWUo J8EcAemw1DyeVQgD4ShPYCoF9HpSF+a+vh0RnFeiDaquRzYVFDveeSYsE+CGV62lG1+q 7u8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771314762; x=1771919562; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=44Jhd6TeZL4PPKiVLdK78+OKBcNZjGbvEfGHis15NrM=; b=P2ZGzJMbyxxctN3ruUyXqSwInpWrxmtJc0e+bSabVkkwKFH1lxXfsF/YEpfKbNdxjm t07CqCWBb+3yzclbqp1DxgjZFUg3prSmCZjNZBhcGRXUXx6bJ4N49wOJs9K9i6g1MQGb FfEti17xpV+CCmRAyFal3CGVOkulXYZ1tIqGdquKHo0srA4hINV8QlU33Nt1Dm7JoCIH NOOgNKjsNCURZWGmkqXaqbRiA37Vf1p0l1gI3jO9nBz6NC6hD6e2KdeNnwl37FKJldNi X+IXAHQdh03fOV8PblvfGR4BybSclAnxNQmXLyToEFHBd/fMwZ53ahIQtfbHqOqIylG8 tBCA== X-Forwarded-Encrypted: i=1; AJvYcCVfBeu0YT69qzHuVdzzwmGDd46EXZaI3yKV9+duiSYJ2fxPkt5yCnUqfkjztz9L2XimeQLKSTw63aLCjK0=@vger.kernel.org X-Gm-Message-State: AOJu0YzptDq4HjVppwOpm1+0CaZwboB61exjKINJftHs3r+oJJ9yTEZ2 WYPLy0TtEdf77mkN+VftOXzyK/XOvP4L9eOeEMEzPAEz/LztiT1Qg6+K4MZQq1Tpam25aY8s5KC UFg0jfifVwkHk5EVY3SkAPIsAZmuaJfg2R8qN4OmAvfVSOpDGUzyrNgPwiepSJxYTf2A= X-Gm-Gg: AZuq6aISg8jpyR78QXckhLLa/wvJ0MKfKWks+CR6NMOhg/BEeCgj0Tl9LV/cB5k0qO6 7jE1adgb2EkpIRbx2EzzvFaMcap7U5CW0o+NHTvyrYcKxTRT3+9x8kNqE3fXddFwnG/w9hhLzUF GgA9Ay+UWfrJIWNHU8N6fE6PlUUi09RhfBrP2Gb+0PMT9Bb6d3LwiT4u45smANwBtueKb1/do+h nMrmsLni4AwZOM/Z5Hxu1WXHWl87Bh0v1bTf/y2/v5TZ60QilhlnLKXeDfH+C9NSH3r7kip4fLk jTr05mVdarmAgTkXcoBUskFf99Q5vD9Pcoh4YsFHyzEIR4wuSHFkbs1vIxZtbYaNmizaLuYrZRN bbt6rAncZ4BtorOvGCDVidhIedQvlBw== X-Received: by 2002:a05:620a:171e:b0:8c7:13b8:8b55 with SMTP id af79cd13be357-8cb42412460mr1479045185a.46.1771314761549; Mon, 16 Feb 2026 23:52:41 -0800 (PST) X-Received: by 2002:a05:620a:171e:b0:8c7:13b8:8b55 with SMTP id af79cd13be357-8cb42412460mr1479043085a.46.1771314761032; Mon, 16 Feb 2026 23:52:41 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ac9d77sm29860229f8f.33.2026.02.16.23.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 23:52:40 -0800 (PST) From: Abel Vesa Date: Tue, 17 Feb 2026 09:52:23 +0200 Subject: [PATCH v4 3/6] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Eliza Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-eliza-clocks-v4-3-5d09f28d4251@oss.qualcomm.com> References: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> In-Reply-To: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=871; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=RKCYGsJFqEQSzos+9ejqQfu8ULxnCzq56BctAEfqjW4=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBplB49QQnlb0qw1wGUJvCx0m/XPk5jwp8b9dPRN 8/upQ3/mIOJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZQePQAKCRAbX0TJAJUV Vi42D/9C82yRRnYnVLZBdbzrEdqD6mkCuKAyOuynWjTTRKAVEyAoivog70Ffk1L488gt4nP9E4z PEXTRo9F4J3Prcit0au2KkXuUpjG0xzWf5fcIA+vlxngQ0kGsDiLFuZWNfocO9s7yX5ahGiPjxV m7dIyeX7BgcMeEIPm2v+CVlWs3/yfM6bURBRUarD4P/6+Y1r8jtzakMKQazN4H1FJAT9bUx0M6/ 57jDkOvL7uNq1gO5xKMLoHzlKO/byly6DNWokzm6klWqK6UTysZoty0md5RiIbhEW5eO++NaBnw dtrdgIWtojglW/z9w6QeCo7q2ZeXZlszgE9t8JC3DNvGioJZM0gokKyjjocnpSkGu68izmbjkYC FSESYFblO6VrfTJCI0kA+AQHKrS4XD+YkGH30UT5FiDwNak2EXNzgBRzNx5mrf6paLV0tgfPfve QxOasgs9oswe4A3u/DKRhOn34xrJTaf4RR7TfSIbFrxALCPsAiTVNx2zQnhLneZu/iF30s6S7I5 ZBuFqJpCde/QKB/F0vkJ1d1wmMdYZiEgnke1uRT0ufd3mwhArelx8IhiE8bzbsqbLTMlPaq8p8D oXfEUp3151rak6cVNTZtVaFr1MtlhSUbSBMdBKYZ4SaBUu75Czl1vJf3o0bqARSO900Eh7QUUO3 rj1pM1HemvJPc1g== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA2NCBTYWx0ZWRfX3by3b7BqPORD pZvYSCwJ5FbKfcRjT/Bfw7PmvJt64i5aF0aoQZwDnEE6qAj3zyhVnMN9NdAVt3jPrPvEQqtacGF HSObot7ml9VLmbNBQuauinyml3SZtNSeUKV/IXRYlz8cqALp1e1H2sQz2sslQ5k1BAjy/8zUeWX 0AzfSl0rAVnxb3rCsN7HwyrGg/cceguRm8o0k2ufdTA3qUBL2ZkBgU1Gya3zbcCMQewFlPqQzhO WHRAU9VBMFrlWHAazA+nXMT482t2IIcwRn09KWPG/7XfS2hGwpyNjp9BrNFcFNNQVe1RVFF56sG 8JI6YybZgadMj/a7BTBDdzg3MzSZuOxGPpb4V4ZCjeYIfKH9v15n8RZ/uzS1iOwAlhAX7wxljiL jbi1Nkh941SN9LBAcXkpFWFCTzJw+VQjjzmPVF2fMIUyVT/30xh4NsVzGfTsqdjH/DLgZFZUZKB 44OoeAsIO1aAYVsN6gQ== X-Proofpoint-GUID: SL8XfV4Wgi8hJGG7QI3xeecOHacERMDq X-Proofpoint-ORIG-GUID: SL8XfV4Wgi8hJGG7QI3xeecOHacERMDq X-Authority-Analysis: v=2.4 cv=TPNIilla c=1 sm=1 tr=0 ts=69941e4a cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=PJhJesWDv2iQC9CHGcgA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170064 From: Taniya Das Update the documentation for RPMH clock controller for Eliza SoC. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 3f5f1336262e..9690169baa46 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - qcom,eliza-rpmh-clk - qcom,glymur-rpmh-clk - qcom,kaanapali-rpmh-clk - qcom,milos-rpmh-clk --=20 2.48.1 From nobody Fri Apr 3 03:15:15 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A122D8DD0 for ; Tue, 17 Feb 2026 07:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314767; cv=none; b=IoPENiy7sCHMH7+WnFTSVCWI3qkNuM4FChW+2oPacgO/24owSlHQ2sVKvcS/y8Rh2kWksqcwjG3DW2n7C6Qfc2EhsFkKgFeukbwv3uMjjBDmAmT2jAZD2+eAnmABGk+wFQS2XsxDvUXubEGGasxMk2xPHPv6DfPXRXXvGgh8ZM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314767; c=relaxed/simple; bh=/SzSv8UMfhi5znodHP6PjQYlZg18R+0NDZwkrVHeQ14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dT2v9PkHbuUbnWZGJBQZ7bn4rOcaZlT3KIRkbpGMtStfmMmoRbD/twpk2N3nl/Ly6lPkruwzZo4YEgEudBTsky0in7nsjR5HD4uTrP49Th8z9BIs20TCCPrmEm10xB287hyq0A0CpN0VGC7nYHxFVuDkewk0APidql8tI6vZE4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cWPCk6om; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dirBSn5o; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cWPCk6om"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dirBSn5o" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61H6NaKi3392807 for ; Tue, 17 Feb 2026 07:52:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Tz0PzecnV0gOV0OjTmSAMQlZ89zqvIEzR4OqGyCHFRk=; b=cWPCk6omPAXMyqsW 7i2/IHomSnOMBW2oFFqKFQ3wD/BCrZPp5GjmmZ4lCLhiYu0WEqGf1h4vBRhSXP5G 9SLSKYy4IrBGyVNwZwVtWwsk3j7Z2GbG0924KYsQzHjVAvkKUDCeibZXDJ8ns47Z 2ok7cTXgGT2Rsqi5cFv5zcn0nzkwyjGzLvODSb5YRz06zoLFe0oK4JzW2Wo+4iHl LVPGOCGQAkVx1D/auaToWLC7j8Gmjeaq9uUchSIC/nWXUChtZPfbRSEKnT+bsKp1 RrbAtsCZOUr/CZKugz0tns/EnW+jPgna6HpBr5cJeaO+nUHujKsjoH7CJricC+1J jlXy7g== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc5kh9r6k-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 07:52:44 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8cb3a129cd2so2836879585a.0 for ; Mon, 16 Feb 2026 23:52:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771314763; x=1771919563; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tz0PzecnV0gOV0OjTmSAMQlZ89zqvIEzR4OqGyCHFRk=; b=dirBSn5o1UJYQ7gBqev+qvBmh9EMqrOfeAephEW8+TGPKGvjcWgQ6FJlm+uIFPLekc yporEu+Q2RLy1WY9AaF4GxzyhiIw1v7nL3DtLMYD6jQHczXXe4b8rzPgtNh57vA46YDU Ez+194hfbA2ChoHAZa0Ip1vY4SIAuxDrjz0pITv97fdqPYr/6nEjSFPndzexKWH+r4Kf glZ1olN0nT2BdMAdABiEDEEC7L00JDq52UmC0wi3kembrwjJryUSTkhpA6OMCofvrc6f b/EcthT+QqxRbu73Kz07rcql5CMMy11SgVZ+rbucx+fS4dsQju45C9qHIvj7Sr+i9lzs WCdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771314763; x=1771919563; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Tz0PzecnV0gOV0OjTmSAMQlZ89zqvIEzR4OqGyCHFRk=; b=XmuqDdX3ylDYFUw7Kdjl521Nr82/io8Wr5SdumDBGQxqX0C1515jzzERyfkxvSb6Ol hy3tOEvv9iBY/aD7eKaiyJNCMyCSw7KJ49VZOCE+qs0PNeM4pAQdAyjp9dWWtsEgIzYQ h+D6brPFPfIJXe8qGpp8CuaJi6WsK0FafTj94HZMi25oHHqX/jC3gofhULNBu7qMhuhe 6tjaCjbK3kA1eLFrjoALYVYu0oVqeon2JCWN7k+Jq+vvUIP0Z1F52oQqqrDgHw4Tht+r 0+rDOR5P9gxEEYuzCtq8BliWNOJ83zxPJKNxppFfUi1ZBVyoAnNIsTy2RLmUwP3bkaqT Uslg== X-Forwarded-Encrypted: i=1; AJvYcCVTr8onUpW8NqKidjTa9/rV+j8hRIpzjA86hhPRwIpkJzPDRx9TWBUrEwrEuaL3j6TSt9jIbtA5MUv4S9k=@vger.kernel.org X-Gm-Message-State: AOJu0YyU4AyQIlC6ptZAcwYkAHYLzkXsCWLTy57QeGi70FvMI7RMD9yQ BrQ99/L6Wy/PieHHdTQR+qvJaQN7rmSGos0elZ1xDVddOJkB1sW/dbk38W/G3h69M/8mSpXdLAD yTuGqdHfcqBdyelwtYQgT76wLwCmsjaUWXfRqvxUA8qlGIDPhuvcZA3TgRY75H4gmOVA= X-Gm-Gg: AZuq6aIrNkcl2uY90wDCENh17Gy8niyiivUCV895adVXe8cEZHIXuIASn1OkorGw8hC TCFEIddla4uA+g46a0PTrQ+YAhl8TFUaKfDxZL6dszbSCDTw61wF54XV+FRYE/kYZp9maT7T2wi d/tQJZkQBrnfYOc2po53rB3cPu3kmG6KmBkQ9r/BDAAAZPBc6O/fH7Jt5YPAWf6d0TmsNuiPcFa 6A/t6UhMozB9aTbquogqlPTen5iwRuK/ocQNePn3gby2+zBR9g9kLndCvbfbnxt6uC+9GNPUTXc HMnpDPd08uZNyw8axkcQYex7l+37DLBGa8JJAbq7MtxiVv96ATwvj4cQuOfBtIj95ttnPEhvSg1 zqYPEdFEwvUstowYhRmi2JD6OuBsmNw== X-Received: by 2002:a05:620a:40ca:b0:8c7:110e:9cd5 with SMTP id af79cd13be357-8cb4acd53c8mr1153725385a.45.1771314763367; Mon, 16 Feb 2026 23:52:43 -0800 (PST) X-Received: by 2002:a05:620a:40ca:b0:8c7:110e:9cd5 with SMTP id af79cd13be357-8cb4acd53c8mr1153723285a.45.1771314762783; Mon, 16 Feb 2026 23:52:42 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ac9d77sm29860229f8f.33.2026.02.16.23.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 23:52:42 -0800 (PST) From: Abel Vesa Date: Tue, 17 Feb 2026 09:52:24 +0200 Subject: [PATCH v4 4/6] clk: qcom: rpmh: Add support for Eliza rpmh clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-eliza-clocks-v4-4-5d09f28d4251@oss.qualcomm.com> References: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> In-Reply-To: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Dmitry Baryshkov X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=2482; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=pIwMv3xwfCvbmXtdNXhaPOf3iqbou1znO8168is1YGY=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBplB4+uYRxQhZASOvz/ykwpEifRNoxEwpHfPAeK g2VCxOJf3uJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZQePgAKCRAbX0TJAJUV VuFVEADIRvKK4Kz4raB1hNHwsOo5jk23imbh3oSbyhYamXIJSPUlH8LPAr1+VD1aIo96jpvz5G7 UIzAR2dW9TccUaNFCopPTAudIMi6kmffxa/acTthLwvGxNic6+Zii7rN0o32s3ZwW08kxpcG6PQ efZ9M38/WceM3nuW/o1+9uTtdVHvL4nk6XzVjdv2Ni7qZu/fD19k5ZeIOqPms+4VAvJkyw/2dQM ap8z4PfOqr2u2MCnjskYLYjpv9hlvhVDb/ZQTN3w44p6iv5H2ZmrElGn5V1nbHD12tn1hVDRnw4 yImLrp7GyqBcXajbtNcx2BFfD2lLjHFYpZEzgi5G4/2pAkPSUVYgxetoSM5XOGKlj25HCB2y8yi Kb5nWaMuiPnl4uPhihSf0WCGAjqyfQ7Tf0bnW0FJVTtuDlPxVVITRTBuD7v5LV+xz8eBpOBr0Rt fBKePBNDr8/9yw3pg/kdv7byQNXkAY1TFKkvbCeC4bKeBu0J4nEI3/aVVCMObFXiB6XnqAE+BL/ uHrQOTXue0yHgzmXOgGEpiWsuWLfRAnJX1Mk3FUpssiFzafgWDlBZbsq05LmqHZOsQO/hqHzlQr CxZBzFCdkmEdTftDzpF9D3Z9i5yrSH4tPr6O8FW1D5NcyvtviEsXkiP1gTWKQRmZSAcg+2MzZXx BkerIDf02c134fg== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Authority-Analysis: v=2.4 cv=Coyys34D c=1 sm=1 tr=0 ts=69941e4c cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=WYKAqXAjdBNwTyPbr-UA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: V28PR5-REu0xZH4GcyryS5qjuT-sT74w X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA2NCBTYWx0ZWRfXwb3bCxntKhrw DGPNSX1WaIfOkTD4NnrRxrAJUIMtFmtcJjGYF3j/I+6oqWWHXRnsWwS9EkWI3F4fnhsDuoC86dJ pUdEL+nz1+d7nhIQBCDTeUD8RVnFY72PhjMFHM0Dj4Fv5Y9akN3NEYaDZdlwZR16iQX0+p3Bkdr uzOKfcqAx6I7QpKErTOqoe+5i7Q+MFtGNAIV4q9GEvvBfprOUfcDjTj/gipGNt1Z4+2Q4+sxztC MwKNcRJDe3yYXecwLW26Vc7CyaR9LDzH753ew5OGSMzoI0KWYTe/mVVK7d/utlmkpp/7IgOsJHD O2AEE1JZfzjyh6PNkImvFne9Fc21QQqxNxY5Kc4QC1g/EbwkEKu/0RytB1PQzbJJUGEnaJNtIVx 7UiUsjdWhi8vV//AxjSeut9OW4GRVUomRlAHrci3oASkz6bW19IsrYv5P/ttVFAsvrk1zGw0iXp MxYRS9HlFUsIMSx3iNw== X-Proofpoint-ORIG-GUID: V28PR5-REu0xZH4GcyryS5qjuT-sT74w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170064 From: Taniya Das Add the RPMH clocks present in Eliza SoC. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-rpmh.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 547729b1a8ee..6a54481cc6ae 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -372,6 +372,8 @@ DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); =20 DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2); +DEFINE_CLK_RPMH_VRM(rf_clk4, _a2, "rfclka4", 2); +DEFINE_CLK_RPMH_VRM(rf_clk5, _a2, "rfclka5", 2); =20 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); @@ -940,6 +942,29 @@ static const struct clk_rpmh_desc clk_rpmh_kaanapali = =3D { .num_clks =3D ARRAY_SIZE(kaanapali_rpmh_clocks), }; =20 +static struct clk_hw *eliza_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] =3D &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] =3D &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK3] =3D &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] =3D &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] =3D &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] =3D &clk_rpmh_rf_clk2_a_ao.hw, + [RPMH_RF_CLK4] =3D &clk_rpmh_rf_clk4_a2.hw, + [RPMH_RF_CLK4_A] =3D &clk_rpmh_rf_clk4_a2_ao.hw, + [RPMH_RF_CLK5] =3D &clk_rpmh_rf_clk5_a2.hw, + [RPMH_RF_CLK5_A] =3D &clk_rpmh_rf_clk5_a2_ao.hw, + [RPMH_IPA_CLK] =3D &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_eliza =3D { + .clks =3D eliza_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(eliza_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -1029,6 +1054,7 @@ static int clk_rpmh_probe(struct platform_device *pde= v) } =20 static const struct of_device_id clk_rpmh_match_table[] =3D { + { .compatible =3D "qcom,eliza-rpmh-clk", .data =3D &clk_rpmh_eliza}, { .compatible =3D "qcom,glymur-rpmh-clk", .data =3D &clk_rpmh_glymur}, { .compatible =3D "qcom,kaanapali-rpmh-clk", .data =3D &clk_rpmh_kaanapal= i}, { .compatible =3D "qcom,milos-rpmh-clk", .data =3D &clk_rpmh_milos}, --=20 2.48.1 From nobody Fri Apr 3 03:15:15 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 259D62E229F for ; Tue, 17 Feb 2026 07:52:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314774; cv=none; b=SdZzF5gUDlemk/29kcrr0tEKHeC/S+ABoadtjIhV3zTjCjU0gRLLAAcJzbxohItSpBKr1RdMLdc7r0q3sfLrI1pYfTpLQxVyx0Ug5VmrEI3lcNvJu3d6A+YhdbsmRLSfxSKej3SSJaT6aw1ShtG1yI5QknfdlfbuTOrSmDXC3BY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314774; c=relaxed/simple; bh=zwMCcPAuCXai999/wI98Q7dCCUM0EYh9melzSQ3993M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZCBZCVHJOLCLq8FIcXDcxBxYagX5y08sPgMR100bsWfBrmFrkIjJ5u06kadLmaIvFYxTWmdhR7CnA20hC5xGqz0M2PsqgYtzQ/j/aNhlsZycMJbejNsAYe6FkYgdZ2wnziFgPIk7+xPVFiKg+mc0AvFdw3w27/SG5Zog68v7Xh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mE5b9JZK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=doGngOEK; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mE5b9JZK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="doGngOEK" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61GL7eIv1613296 for ; Tue, 17 Feb 2026 07:52:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= u1vuheQQZwC5yO5E/I67rb6CP8LDvvO1aimLGi515dk=; b=mE5b9JZKi5N8+873 oy71L6OtQeC6mPwtUuMBJMYA8/V54stvYDBUBuBbYasPHkVMn4OE5vA8N9lZKntK eXMhymJyFV3ICSCJq9Z9QnFbhz16kIeA9HCF+nfh/kyM8gQNDMySV5fKup5ic3DD ee+7sp3mkFpEbbgb4PX4oYULA+Wuw3A0/KcW7gro698o8U2Q/f6BpWGw+iLDYO2+ Qf9AlKNbaAmIZI4qvAfk4TX85UKw6xz2CetFue1n9mPHkpEpiNzl1tANTnpfC9Zx GqBj9NjBqaYlBlk4HIdXODqcG+iFK52HiZQ8fPqGNgmexiCMIgCIaNcUTMpnwLxh yftDDw== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc662sk57-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 07:52:46 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8cb3a129cd2so2836905185a.0 for ; Mon, 16 Feb 2026 23:52:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771314766; x=1771919566; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=u1vuheQQZwC5yO5E/I67rb6CP8LDvvO1aimLGi515dk=; b=doGngOEKOHTMJML9e7XCAuw1EJ664M01vUAAX9HgxNuxoi5k7mRaBwn6F2gsL4xG+C V5g8JfKbQL35txfdvqhv9N0VVK7rWoIDYQp1BrgUx9r6CxpGVADrvIf6JddZRpbX+P7j zPEgZfd7m4jmyETRbzbA1RiD/aFwlRcMNVsTVvrxTKejCwpSr5VA/QIECM63J+LxAhA2 9itM5ChNn6hKkCd55eB7A6VCt9etAEHaDPEOjT1kZXXnQhV7OZ/HW8nvY3SZ8SG5PHKU ME20QDxVTm0M3Rd4PgZequurUXkgC7kGyovJVRN3cDXs2Z56Gk6J2I+5GKxkt3Tvg3iC 25Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771314766; x=1771919566; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=u1vuheQQZwC5yO5E/I67rb6CP8LDvvO1aimLGi515dk=; b=OpgFtmgISFLAxh+DHBvqwZ+EYhLJcSoHgnDNaZhq6PuJ7jxeePQJfhHJ8M4A5N19lw 7fd0s0Di5dP/9QZM36HEWNkD2dGeXClh//KxOAv1OsnTmapD7+VFrtGZNokcOCDe3hdR 8vsWXuHMWuty6USaBKEtPWUNNbJHT7hb5SnloqOZJAuAMF0ll8EQ94xj2y3e1oQ9pGlr /20NRU6gxkIzCyaHETbEy3l+iQ7CxLpOwhsAf7PRk2S4CaRnELVZ/aOQ23Jh0SfIh77X ZmMtdGW1/zG4JArrEtVZLd2qNYCGkAQuVwvFT6BpvavmXQcQaYdExZIVinNR2Qw1hiYY WbGA== X-Forwarded-Encrypted: i=1; AJvYcCV5SU/9EN+/IXYoo3aWIkxCqNi8ACoqYQphhiAoLeaW3at1z02X92vqI9rBYxGVxj2f1ufUNZeYpOuTrAI=@vger.kernel.org X-Gm-Message-State: AOJu0Ywwii80Uf/xYUIdd3A9SA8MZ/0wrabzJgo7v/KZHVHY7e0QTTUp /6ta18pn31SC4C9HOn3vO8CpFfJvbUtGEGX88Hq8LhPMnaM37t/BbJpOfl/vZNmk1+H1S/N9Wo4 FJwnX0CB25cBHG652i22/0JYxVUsovujXEAYb3RwAgj4KbIsq6EjWT9gq+9+Y7bZNzlw= X-Gm-Gg: AZuq6aIiZJVqf6p04fYwCkjJretw/+lsK927StPDF5bPp5+0L5kzzf9Wm/qcRSQLMhP ZDiXlzweWRWTqHDVCTQdZvhjklguGCYBlYkmso6acL4J0xh8gYaMmDsBShDGMTWJcbbkn8iq6FM pY4ugQqMtJKSuzEGTi/JxabdcUocHvthnJ3DG1h5j2e9sJWUSspOQcUPTWzAuEeSbbO/yiM9Wn2 BFkkp95Ky5FVZnXIHVh8ErmU6blh1z3+75yYeOs0OS5rKqvMKBoge9ysM9fpFb1Az2d3Fi9ZYiZ 4sPqyOFMsPqj/okFpxOu7QWni5Mkr88iQNxkJbA+iqIJusiLk8f58fzYWcXe08crvDMIfIRYZZT g8G362Kj5y3+uSYLqhiCe7INXzlp9IA== X-Received: by 2002:a05:620a:4724:b0:8ca:370a:3ac4 with SMTP id af79cd13be357-8cb4abedea6mr1304944185a.12.1771314765472; Mon, 16 Feb 2026 23:52:45 -0800 (PST) X-Received: by 2002:a05:620a:4724:b0:8ca:370a:3ac4 with SMTP id af79cd13be357-8cb4abedea6mr1304942785a.12.1771314764636; Mon, 16 Feb 2026 23:52:44 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ac9d77sm29860229f8f.33.2026.02.16.23.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 23:52:43 -0800 (PST) From: Abel Vesa Date: Tue, 17 Feb 2026 09:52:25 +0200 Subject: [PATCH v4 5/6] clk: qcom: Add support for Global clock controller on Eliza Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-eliza-clocks-v4-5-5d09f28d4251@oss.qualcomm.com> References: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> In-Reply-To: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Dmitry Baryshkov X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=94808; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=5yfKPWLLmRSQpPNSCdv4ageh07BjqeQsonWGk6NlejI=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBplB4/qcxUmFGHg00dSfYOvfwO9zqF417OMsK92 5sMhbSgtuWJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZQePwAKCRAbX0TJAJUV VofMEACqkZA6pjtNaksvrO0mWSoMBF5BoVgYOhR9+AxXEe9MY93+tsNnvIGfj5mFPJwMjoe0J3i iEkUaxkxb9fKHbs7GHXX65QqV2ZgTdc0xC23KxgxDUdWfBhzTO+wZ5w0lYypg48j2oXesN7XPOS wOT9506n1mIw4tmONUzJWDBzPHhyAUK9Md+ZanSyJhnnckOFopiRg9zCzAdzo7uTYu7QSItourY wjgK61NW9OxWJLjB9uojwWg7LztUnNWD9xnMygZArcg+1Fu7thQqQ+XQc6yhFp/o0o9B6TOLZo8 CQtcKsR2ZG6iCCW5F/YEk2rDgpx77sukL6jKgvW7f6NYPQNhQRdKTZpOkf7nDHnb53Vtg7RW6Bi /5q5GicYBXjzXRW+L05yHLSP8p1x4UKO4JHnFLxCyN6UFww3sTUOHjfDr2kuw9+i7cbCZRVxq/w 6FtAMdlRVJ+9A57kJ1tdzEPXlAFBZTeUmLugZuSp7ruHHlWppgt5W1VFYQQYMqMq8Y57ID1PqS7 poJV1o65Q5NNCdCf+vrqzVpQD3jPngCZG1JJp8M0DdMWqEoXpK65Z1vhsAVlciv8pDqZmw52XPG KkW9TPH+8jD/fb+g/xy2ewx3qBMC4CqLZup0n+jCZE3iWFXUMRrpvzVAjamnWkDzJzCvvCa9WkM LY2fvZcTGKa/Prg== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA2NCBTYWx0ZWRfX4mrQrQMBnQWV uUvOt8DUMk9EZJJsSY6F3+/U5UVZ8mLkmykn4303cA+uVwUootK1akcO5hh6C8GnfCxCLDdTKm7 11CBxFUsCFi7H6SLJGHXSgVycqmzcblilVj/Iwf4bh/mna9FIgHFLz7OMOi8Fl2T9fHcCJn8kQJ Hi+7Uadsj7mPQRpnIrALNfYNx2VLMkp0yXssMT3DIWdM108/J327Fe9zS7kw2GD2fN058Kei07f jhw7dFT8U9arNG/ydg8CdoUkT2fnVjcn0FJbdY3kch68O78yUHhNf3Q+lqQ/gwtmjebVR2zU6KG JYWrc1sfhOD10/sykNZegiuYhD7pUYXFa5cqzG5aPQDNf8Ew0vC73c5YSRONFSbagTQxFK49uGs VI61RZOysocZLBmTG8HpRJX2O1AEuU9no9/sIZKQEjEx4/AWpDDwabgPd4Vs1EqWEdVdHqSJ/xK 1qlgMIFMjmDsJcwzaxA== X-Authority-Analysis: v=2.4 cv=Y6b1cxeN c=1 sm=1 tr=0 ts=69941e4f cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=vEk81DoPt5Q0sh-jQiIA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: RnNklNmsxW3wedgRyTWdQyCzQvnbwYJ_ X-Proofpoint-ORIG-GUID: RnNklNmsxW3wedgRyTWdQyCzQvnbwYJ_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170064 From: Taniya Das Add support for Global clock controller for Eliza Qualcomm SoC. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-eliza.c | 3160 ++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 3170 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb74..edac919d3aa2 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -19,6 +19,15 @@ menuconfig COMMON_CLK_QCOM =20 if COMMON_CLK_QCOM =20 +config CLK_ELIZA_GCC + tristate "Eliza Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on Eliza devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, UFS, SDCC, etc. + config CLK_GLYMUR_DISPCC tristate "GLYMUR Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55..6ec63a5d4363 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -21,6 +21,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) +=3D gdsc.o obj-$(CONFIG_APQ_GCC_8084) +=3D gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) +=3D mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o +obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c new file mode 100644 index 000000000000..239d9b61ae6b --- /dev/null +++ b/drivers/clk/qcom/gcc-eliza.c @@ -0,0 +1,3160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_PCIE_0_PIPE_CLK, + DT_PCIE_1_PIPE_CLK, + DT_UFS_PHY_RX_SYMBOL_0_CLK, + DT_UFS_PHY_RX_SYMBOL_1_CLK, + DT_UFS_PHY_TX_SYMBOL_0_CLK, + DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPLL0_OUT_EVEN, + P_GCC_GPLL0_OUT_MAIN, + P_GCC_GPLL4_OUT_MAIN, + P_GCC_GPLL7_OUT_MAIN, + P_GCC_GPLL8_OUT_MAIN, + P_GCC_GPLL9_OUT_MAIN, + P_PCIE_0_PIPE_CLK, + P_PCIE_1_PIPE_CLK, + P_SLEEP_CLK, + P_UFS_PHY_RX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_1_CLK, + P_UFS_PHY_TX_SYMBOL_0_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +static struct clk_alpha_pll gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll7 =3D { + .offset =3D 0x7000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll7", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll8 =3D { + .offset =3D 0x8000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll8", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll9 =3D { + .offset =3D 0x9000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll9", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL8_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll8.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_PCIE_0_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_PCIE_0_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_PCIE_1_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_PCIE_1_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL9_OUT_MAIN, 2 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll9.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_UFS_PHY_RX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_UFS_PHY_RX_SYMBOL_1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_UFS_PHY_TX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_13[] =3D { + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, + { P_GCC_GPLL0_OUT_EVEN, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src =3D { + .reg =3D 0x6b080, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_7, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src =3D { + .reg =3D 0xac07c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_8, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src =3D { + .reg =3D 0x77068, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_10, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_0_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src =3D { + .reg =3D 0x770ec, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_11, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_1_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src =3D { + .reg =3D 0x77058, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_12, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_tx_symbol_0_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src =3D { + .reg =3D 0x39070, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_13, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_13, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_13), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x64004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x65004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x66004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_aux_clk_src =3D { + .cmd_rcgr =3D 0x6b084, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x6b068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_aux_clk_src =3D { + .cmd_rcgr =3D 0xac080, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0xac064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x33010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), + F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_qspi_ref_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src =3D { + .cmd_rcgr =3D 0x188c0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_qspi_ref_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x18014, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x18150, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x182a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x183dc, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s5_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x18518, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s5_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { + .cmd_rcgr =3D 0x18654, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { + .cmd_rcgr =3D 0x18790, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src =3D { + .cmd_rcgr =3D 0x1e014, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src =3D { + .cmd_rcgr =3D 0x1e150, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s2_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s2_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src =3D { + .cmd_rcgr =3D 0x1e28c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src =3D { + .cmd_rcgr =3D 0x1e3c8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src =3D { + .cmd_rcgr =3D 0x1e504, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src =3D { + .cmd_rcgr =3D 0x1e640, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s5_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s6_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src =3D { + .cmd_rcgr =3D 0x1e77c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src =3D { + .cmd_rcgr =3D 0x1e8b8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap1_s3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s7_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), + F(384000000, P_GCC_GPLL8_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0xa9018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0xa9040, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x1401c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_apps_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), + F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x77034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_axi_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), + F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x7708c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_ice_core_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x770c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x770a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_ice_core_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { + F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0x39030, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x39048, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x39074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src =3D { + .reg =3D 0x6b0a4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_div2_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src =3D { + .reg =3D 0xac0a0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_div2_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src =3D { + .reg =3D 0x1828c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x39060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_aggre_noc_pcie_axi_clk =3D { + .halt_reg =3D 0x10068, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x10068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_pcie_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x770f4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770f4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x39094, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x39094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x38004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0x26014, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x26014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0x26024, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x26024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk =3D { + .halt_reg =3D 0x10050, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x10050, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_pcie_anoc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x39090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x39090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie_sf_axi_clk =3D { + .halt_reg =3D 0x10058, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x10058, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { + .halt_reg =3D 0x71158, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x71158, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71158, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ddrss_gpu_axi_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk =3D { + .halt_reg =3D 0x1007c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1007c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ddrss_pcie_sf_qtb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk =3D { + .halt_reg =3D 0x27008, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x27008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_disp_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x64000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x64000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x65000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x65000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x66000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x66000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gemnoc_gfx_clk =3D { + .halt_reg =3D 0x71010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_gemnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_cph_clk_src =3D { + .halt_reg =3D 0x71150, + .halt_check =3D BRANCH_HALT_ENABLE_VOTED, + .clkr =3D { + .enable_reg =3D 0x71150, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_gpll0_cph_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src =3D { + .halt_reg =3D 0x71154, + .halt_check =3D BRANCH_HALT_ENABLE_VOTED, + .clkr =3D { + .enable_reg =3D 0x71154, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_gpll0_div_cph_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x7d000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmu_tcu_vote_clk =3D { + .halt_reg =3D 0x7d02c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mmu_tcu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_aux_clk =3D { + .halt_reg =3D 0x6b044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_cfg_ahb_clk =3D { + .halt_reg =3D 0x6b040, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x6b040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk =3D { + .halt_reg =3D 0x6b030, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x6b030, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_phy_rchng_clk =3D { + .halt_reg =3D 0x6b064, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipe_clk =3D { + .halt_reg =3D 0x6b054, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipe_div2_clk =3D { + .halt_reg =3D 0x6b0a8, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_div2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_pipe_div2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_axi_clk =3D { + .halt_reg =3D 0x6b020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x6b020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x6b01c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_aux_clk =3D { + .halt_reg =3D 0xac040, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_cfg_ahb_clk =3D { + .halt_reg =3D 0xac03c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xac03c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk =3D { + .halt_reg =3D 0xac02c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0xac02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_phy_rchng_clk =3D { + .halt_reg =3D 0xac060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_clk =3D { + .halt_reg =3D 0xac050, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_div2_clk =3D { + .halt_reg =3D 0xac0a4, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_div2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_axi_clk =3D { + .halt_reg =3D 0xac01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xac01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk =3D { + .halt_reg =3D 0xac018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x33004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x33004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x33008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_cmd_ahb_clk =3D { + .halt_reg =3D 0x26010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x26010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_camera_cmd_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk =3D { + .halt_reg =3D 0x26008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x26008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_camera_nrt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk =3D { + .halt_reg =3D 0x2600c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2600c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2600c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_camera_rt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_gpu_ahb_clk =3D { + .halt_reg =3D 0x71008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_gpu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_pcie_ahb_clk =3D { + .halt_reg =3D 0x6b018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x6b018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_pcie_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x32010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_video_v_cpu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3200c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_video_vcodec_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x2301c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk =3D { + .halt_reg =3D 0x188bc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_qspi_ref_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x18004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x18140, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x1827c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x18290, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x183cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x18508, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s6_clk =3D { + .halt_reg =3D 0x18644, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s7_clk =3D { + .halt_reg =3D 0x18780, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_2x_clk =3D { + .halt_reg =3D 0x23174, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_clk =3D { + .halt_reg =3D 0x23160, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s0_clk =3D { + .halt_reg =3D 0x1e004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s1_clk =3D { + .halt_reg =3D 0x1e140, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s2_clk =3D { + .halt_reg =3D 0x1e27c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s3_clk =3D { + .halt_reg =3D 0x1e3b8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s4_clk =3D { + .halt_reg =3D 0x1e4f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s5_clk =3D { + .halt_reg =3D 0x1e630, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s6_clk =3D { + .halt_reg =3D 0x1e76c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s7_clk =3D { + .halt_reg =3D 0x1e8a8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x23000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x23004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk =3D { + .halt_reg =3D 0x23158, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23158, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_2_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk =3D { + .halt_reg =3D 0x2315c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2315c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_2_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0xa9004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa9004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0xa9008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa9008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0xa9030, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa9030, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa9030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x14014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x14004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x77028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x77018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x7707c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7707c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7707c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x770bc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770bc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x77030, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x77030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x770d8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x770d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x7702c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x7706c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7706c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7706c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_atb_clk =3D { + .halt_reg =3D 0x3908c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x3908c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0x39018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0x3902c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3902c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0x39028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0x39064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0x39068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0x3906c, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x3906c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3906c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk =3D { + .halt_reg =3D 0x32018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x32018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_video_axi0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi1_clk =3D { + .halt_reg =3D 0x32028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x32028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_video_axi1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gcc_pcie_0_gdsc =3D { + .gdscr =3D 0x6b004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x5214c, + .collapse_mask =3D BIT(0), + .pd =3D { + .name =3D "gcc_pcie_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_0_phy_gdsc =3D { + .gdscr =3D 0x6c000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .collapse_ctrl =3D 0x5214c, + .collapse_mask =3D BIT(2), + .pd =3D { + .name =3D "gcc_pcie_0_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_1_gdsc =3D { + .gdscr =3D 0xac004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x5214c, + .collapse_mask =3D BIT(3), + .pd =3D { + .name =3D "gcc_pcie_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_1_phy_gdsc =3D { + .gdscr =3D 0xad000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .collapse_ctrl =3D 0x5214c, + .collapse_mask =3D BIT(4), + .pd =3D { + .name =3D "gcc_pcie_1_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_ufs_mem_phy_gdsc =3D { + .gdscr =3D 0x9e000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_ufs_mem_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_ufs_phy_gdsc =3D { + .gdscr =3D 0x77004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_prim_gdsc =3D { + .gdscr =3D 0x39004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb3_phy_gdsc =3D { + .gdscr =3D 0x50018, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb3_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_eliza_clocks[] =3D { + [GCC_AGGRE_NOC_PCIE_AXI_CLK] =3D &gcc_aggre_noc_pcie_axi_clk.clkr, + [GCC_AGGRE_UFS_PHY_AXI_CLK] =3D &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] =3D &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] =3D &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] =3D &gcc_camera_sf_axi_clk.clkr, + [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] =3D &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CNOC_PCIE_SF_AXI_CLK] =3D &gcc_cnoc_pcie_sf_axi_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] =3D &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DDRSS_PCIE_SF_QTB_CLK] =3D &gcc_ddrss_pcie_sf_qtb_clk.clkr, + [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GPLL0] =3D &gcc_gpll0.clkr, + [GCC_GPLL0_OUT_EVEN] =3D &gcc_gpll0_out_even.clkr, + [GCC_GPLL4] =3D &gcc_gpll4.clkr, + [GCC_GPLL7] =3D &gcc_gpll7.clkr, + [GCC_GPLL8] =3D &gcc_gpll8.clkr, + [GCC_GPLL9] =3D &gcc_gpll9.clkr, + [GCC_GPU_GEMNOC_GFX_CLK] =3D &gcc_gpu_gemnoc_gfx_clk.clkr, + [GCC_GPU_GPLL0_CPH_CLK_SRC] =3D &gcc_gpu_gpll0_cph_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] =3D &gcc_gpu_gpll0_div_cph_clk_src.clkr, + [GCC_GPU_SMMU_VOTE_CLK] =3D &gcc_gpu_smmu_vote_clk.clkr, + [GCC_MMU_TCU_VOTE_CLK] =3D &gcc_mmu_tcu_vote_clk.clkr, + [GCC_PCIE_0_AUX_CLK] =3D &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_AUX_CLK_SRC] =3D &gcc_pcie_0_aux_clk_src.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] =3D &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] =3D &gcc_pcie_0_mstr_axi_clk.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK] =3D &gcc_pcie_0_phy_rchng_clk.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_0_phy_rchng_clk_src.clkr, + [GCC_PCIE_0_PIPE_CLK] =3D &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_PIPE_CLK_SRC] =3D &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_PCIE_0_PIPE_DIV2_CLK] =3D &gcc_pcie_0_pipe_div2_clk.clkr, + [GCC_PCIE_0_PIPE_DIV2_CLK_SRC] =3D &gcc_pcie_0_pipe_div2_clk_src.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] =3D &gcc_pcie_0_slv_axi_clk.clkr, + [GCC_PCIE_0_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_0_slv_q2a_axi_clk.clkr, + [GCC_PCIE_1_AUX_CLK] =3D &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_AUX_CLK_SRC] =3D &gcc_pcie_1_aux_clk_src.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] =3D &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] =3D &gcc_pcie_1_mstr_axi_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK] =3D &gcc_pcie_1_phy_rchng_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_1_phy_rchng_clk_src.clkr, + [GCC_PCIE_1_PIPE_CLK] =3D &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_PIPE_CLK_SRC] =3D &gcc_pcie_1_pipe_clk_src.clkr, + [GCC_PCIE_1_PIPE_DIV2_CLK] =3D &gcc_pcie_1_pipe_div2_clk.clkr, + [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] =3D &gcc_pcie_1_pipe_div2_clk_src.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] =3D &gcc_pcie_1_slv_axi_clk.clkr, + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_1_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QMIP_CAMERA_CMD_AHB_CLK] =3D &gcc_qmip_camera_cmd_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] =3D &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] =3D &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_GPU_AHB_CLK] =3D &gcc_qmip_gpu_ahb_clk.clkr, + [GCC_QMIP_PCIE_AHB_CLK] =3D &gcc_qmip_pcie_ahb_clk.clkr, + [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] =3D &gcc_qmip_video_v_cpu_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] =3D &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_QSPI_REF_CLK] =3D &gcc_qupv3_wrap1_qspi_ref_clk.clkr, + [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] =3D &gcc_qupv3_wrap1_qspi_ref_clk_src.= clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_S6_CLK] =3D &gcc_qupv3_wrap1_s6_clk.clkr, + [GCC_QUPV3_WRAP1_S6_CLK_SRC] =3D &gcc_qupv3_wrap1_s6_clk_src.clkr, + [GCC_QUPV3_WRAP1_S7_CLK] =3D &gcc_qupv3_wrap1_s7_clk.clkr, + [GCC_QUPV3_WRAP1_S7_CLK_SRC] =3D &gcc_qupv3_wrap1_s7_clk_src.clkr, + [GCC_QUPV3_WRAP2_CORE_2X_CLK] =3D &gcc_qupv3_wrap2_core_2x_clk.clkr, + [GCC_QUPV3_WRAP2_CORE_CLK] =3D &gcc_qupv3_wrap2_core_clk.clkr, + [GCC_QUPV3_WRAP2_S0_CLK] =3D &gcc_qupv3_wrap2_s0_clk.clkr, + [GCC_QUPV3_WRAP2_S0_CLK_SRC] =3D &gcc_qupv3_wrap2_s0_clk_src.clkr, + [GCC_QUPV3_WRAP2_S1_CLK] =3D &gcc_qupv3_wrap2_s1_clk.clkr, + [GCC_QUPV3_WRAP2_S1_CLK_SRC] =3D &gcc_qupv3_wrap2_s1_clk_src.clkr, + [GCC_QUPV3_WRAP2_S2_CLK] =3D &gcc_qupv3_wrap2_s2_clk.clkr, + [GCC_QUPV3_WRAP2_S2_CLK_SRC] =3D &gcc_qupv3_wrap2_s2_clk_src.clkr, + [GCC_QUPV3_WRAP2_S3_CLK] =3D &gcc_qupv3_wrap2_s3_clk.clkr, + [GCC_QUPV3_WRAP2_S3_CLK_SRC] =3D &gcc_qupv3_wrap2_s3_clk_src.clkr, + [GCC_QUPV3_WRAP2_S4_CLK] =3D &gcc_qupv3_wrap2_s4_clk.clkr, + [GCC_QUPV3_WRAP2_S4_CLK_SRC] =3D &gcc_qupv3_wrap2_s4_clk_src.clkr, + [GCC_QUPV3_WRAP2_S5_CLK] =3D &gcc_qupv3_wrap2_s5_clk.clkr, + [GCC_QUPV3_WRAP2_S5_CLK_SRC] =3D &gcc_qupv3_wrap2_s5_clk_src.clkr, + [GCC_QUPV3_WRAP2_S6_CLK] =3D &gcc_qupv3_wrap2_s6_clk.clkr, + [GCC_QUPV3_WRAP2_S6_CLK_SRC] =3D &gcc_qupv3_wrap2_s6_clk_src.clkr, + [GCC_QUPV3_WRAP2_S7_CLK] =3D &gcc_qupv3_wrap2_s7_clk.clkr, + [GCC_QUPV3_WRAP2_S7_CLK_SRC] =3D &gcc_qupv3_wrap2_s7_clk_src.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_2_M_AHB_CLK] =3D &gcc_qupv3_wrap_2_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_2_S_AHB_CLK] =3D &gcc_qupv3_wrap_2_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, + [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] =3D &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] =3D &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_0_clk_src.cl= kr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_1_clk_src.cl= kr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_tx_symbol_0_clk_src.cl= kr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D &gcc_ufs_phy_unipro_core_clk_src.cl= kr, + [GCC_USB30_PRIM_ATB_CLK] =3D &gcc_usb30_prim_atb_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_clk_src.= clkr, + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_= postdiv_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_prim_phy_pipe_clk_src.clkr, + [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_AXI1_CLK] =3D &gcc_video_axi1_clk.clkr, +}; + +static struct gdsc *gcc_eliza_gdscs[] =3D { + [GCC_PCIE_0_GDSC] =3D &gcc_pcie_0_gdsc, + [GCC_PCIE_0_PHY_GDSC] =3D &gcc_pcie_0_phy_gdsc, + [GCC_PCIE_1_GDSC] =3D &gcc_pcie_1_gdsc, + [GCC_PCIE_1_PHY_GDSC] =3D &gcc_pcie_1_phy_gdsc, + [GCC_UFS_MEM_PHY_GDSC] =3D &gcc_ufs_mem_phy_gdsc, + [GCC_UFS_PHY_GDSC] =3D &gcc_ufs_phy_gdsc, + [GCC_USB30_PRIM_GDSC] =3D &gcc_usb30_prim_gdsc, + [GCC_USB3_PHY_GDSC] =3D &gcc_usb3_phy_gdsc, +}; + +static const struct qcom_reset_map gcc_eliza_resets[] =3D { + [GCC_CAMERA_BCR] =3D { 0x26000 }, + [GCC_DISPLAY_BCR] =3D { 0x27000 }, + [GCC_GPU_BCR] =3D { 0x71000 }, + [GCC_PCIE_0_BCR] =3D { 0x6b000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] =3D { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] =3D { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] =3D { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] =3D { 0x6c028 }, + [GCC_PCIE_1_BCR] =3D { 0xac000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] =3D { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] =3D { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] =3D { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] =3D { 0x8e024 }, + [GCC_PCIE_PHY_BCR] =3D { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] =3D { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] =3D { 0x6f010 }, + [GCC_PCIE_RSCC_BCR] =3D { 0x11000 }, + [GCC_PDM_BCR] =3D { 0x33000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] =3D { 0x1e000 }, + [GCC_QUSB2PHY_PRIM_BCR] =3D { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] =3D { 0x12004 }, + [GCC_SDCC1_BCR] =3D { 0xa9000 }, + [GCC_SDCC2_BCR] =3D { 0x14000 }, + [GCC_UFS_PHY_BCR] =3D { 0x77000 }, + [GCC_USB30_PRIM_BCR] =3D { 0x39000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x50008 }, + [GCC_USB3_DP_PHY_SEC_BCR] =3D { 0x50014 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] =3D { 0x5000c }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] =3D { 0x50010 }, + [GCC_VIDEO_AXI0_CLK_ARES] =3D { 0x32018, 2 }, + [GCC_VIDEO_AXI1_CLK_ARES] =3D { 0x32028, 2 }, + [GCC_VIDEO_BCR] =3D { 0x32000 }, + [GCC_CAMERA_HF_AXI_SLP_STG_ARES] =3D { 0x26018, 4 }, + [GCC_CAMERA_SF_AXI_SLP_STG_ARES] =3D { 0x26028, 4 }, + [GCC_CAMERA_HF_AXI_SEL_SLP_STG_ARES] =3D { 0x26018, 5 }, + [GCC_CAMERA_SF_AXI_SEL_SLP_STG_ARES] =3D { 0x26028, 5 }, + [GCC_CAMERA_HF_CLK_EN_SLP_STG] =3D { 0x26018, 1 }, + [GCC_CAMERA_SF_CLK_EN_SLP_STG] =3D { 0x26028, 1 }, + [GCC_CAMERA_HF_CLK_EN_SEL_SLP_STG] =3D { 0x26018, 2 }, + [GCC_CAMERA_SF_CLK_EN_SEL_SLP_STG] =3D { 0x26028, 2 }, +}; + +static u32 gcc_eliza_critical_cbcrs[] =3D { + 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ + 0x26004, /* GCC_CAMERA_AHB_CLK */ + 0x26034, /* GCC_CAMERA_XO_CLK */ + 0x27004, /* GCC_DISP_AHB_CLK */ + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ + 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ + 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ + 0x32004, /* GCC_VIDEO_AHB_CLK */ + 0x32038, /* GCC_VIDEO_XO_CLK */ +}; + +static const struct clk_rcg_dfs_data gcc_eliza_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), +}; + +static const struct regmap_config gcc_eliza_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data gcc_eliza_driver_data =3D { + .clk_cbcrs =3D gcc_eliza_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_eliza_critical_cbcrs), + .dfs_rcgs =3D gcc_eliza_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_eliza_dfs_clocks), +}; + +static const struct qcom_cc_desc gcc_eliza_desc =3D { + .config =3D &gcc_eliza_regmap_config, + .clks =3D gcc_eliza_clocks, + .num_clks =3D ARRAY_SIZE(gcc_eliza_clocks), + .resets =3D gcc_eliza_resets, + .num_resets =3D ARRAY_SIZE(gcc_eliza_resets), + .gdscs =3D gcc_eliza_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_eliza_gdscs), + .driver_data =3D &gcc_eliza_driver_data, +}; + +static const struct of_device_id gcc_eliza_match_table[] =3D { + { .compatible =3D "qcom,eliza-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_eliza_match_table); + +static int gcc_eliza_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_eliza_desc); +} + +static struct platform_driver gcc_eliza_driver =3D { + .probe =3D gcc_eliza_probe, + .driver =3D { + .name =3D "gcc-eliza", + .of_match_table =3D gcc_eliza_match_table, + }, +}; + +static int __init gcc_eliza_init(void) +{ + return platform_driver_register(&gcc_eliza_driver); +} +subsys_initcall(gcc_eliza_init); + +static void __exit gcc_eliza_exit(void) +{ + platform_driver_unregister(&gcc_eliza_driver); +} +module_exit(gcc_eliza_exit); + +MODULE_DESCRIPTION("QTI GCC Eliza Driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1 From nobody Fri Apr 3 03:15:15 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C192F2E4247 for ; Tue, 17 Feb 2026 07:52:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314771; cv=none; b=TDoGbd+vd5991wYcyNN62llz0qJo7BLZltuXK98PCWbT6SADf96xgfSlg3DD3uOV4FSVxQCuOg0ypDzwgjho8XYVdtgnps20fjFhjihRk0ZDzY92WFI0CoUvSvR2kLOwbcFdOcanudSqreYJ4OjaugwbOPbzLqAAXexnVXdRr9Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771314771; c=relaxed/simple; bh=kSfceoKoPkCgd7aDR+qYIcA97c3pxNAG8T/RrOOziqk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OTCK9I2D38tXMqJI6AGf5g+KmgSRniG+lMIo66lpa4K5Q42Qgr51Pr2vaVSy7iODcKrN+hghHL4NsRh6GtcQ8wmVtpLxXqRrabbVPk3PhPsvaKCWFXCAcTrqgMna/7DvXvRyZ5vuPBLZR6TWNUNritJKkWOPYUZ6kAuCD8DeBwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=XHdm6Cn0; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Si5e6Xix; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="XHdm6Cn0"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Si5e6Xix" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61GNGrNi945797 for ; Tue, 17 Feb 2026 07:52:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 8qJJfStkAEr01lyx9zngav29xGmsak5mO1cGnXwyAnc=; b=XHdm6Cn0pG3vQmDe lduOib83RYdJw/jF09itorJprMjibvWWqjnxjEsU18RVGUaxzvWOwhPRASvdVn1H Y0fIrskZ6uguGy99F1cqsaIFFbyLfsjdVoEPKCU/rowjBQPgvziF6Nu4pJDQGcK0 LqZQyMiegqzvYNWn9GU9Z0cNnc3em/9If8RFh8LzCOr4HnG/nS/Fba31x1yrMU+l Roeaz3gLBAAGRDgmSz1UIK0As/m95t5ZUsEzk1DPB/RdIKmtvPNgIFReKOeiuUgX QBEakZCHNNO3OtdoM3Pm47bUupgtdluwz/1iTDMmRtKF0EMSPR+xCIhf2PawxKIZ QFekkA== Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cca3611us-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 07:52:48 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-8cb4d191ef1so333011485a.0 for ; Mon, 16 Feb 2026 23:52:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771314767; x=1771919567; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8qJJfStkAEr01lyx9zngav29xGmsak5mO1cGnXwyAnc=; b=Si5e6XixNo1EJUWvZJYIF//cb5nS4gzhQe6oMB7+U5qYJOZPhEKZVzdzYkJNrABJwh GK30t5xFpt91POE6pk9+6VASFcZ6E5rWjewDGOYvtimImqnCFkvaiDW6Q7w1/LP4MhZ5 4Zqc9z2L5YMun9q7ryUutkeRB/bfqknFHvWT+puDcp+BzG9rN362oSTj7e5ZzejRo/Qf ocqB6YUkiUISPzpSl4vk5AipHzOKCvI603Tnj9Er9ng7X7j/fK1MizBo+91z1zh0XwKz +eOZ3v11o2t0UhtbNBonGX7a1HfrLe8oEJvahT4AkzJamesshDY9OQW9H8rRbt/wSnuZ qdsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771314767; x=1771919567; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8qJJfStkAEr01lyx9zngav29xGmsak5mO1cGnXwyAnc=; b=F6VKLOlUEkSkzdlDnQeorz/V79gwlqw/n6735CuZTI//lvbgC2qwt+fOEigM8fAcwf 8nnIoDRUo+3AB/ZlpcQuJ6mS5nMluavs4BPbRMF2vNmbuyhHyJA28RAiTM12a0bUDheV AF9yk5tmnx1uN0kT1/qkzmoSdyPUKDLIbT82zq70IOCXMWOPHM1QUZ1/UO3MzITp4w4B eeUjhxuc07IJvaCLwLftP3KWN1dj3owf1GLJjRDJc4EjhnJ9Hh4hUoOKTIof1rYdcoHA PbEgaXBdGi8Y+e4RFZC7qkIWO1BQvK/TDVHSZb4aThHGhDx2n8Yvcob4T0UDEm84QZ4G C/Ag== X-Forwarded-Encrypted: i=1; AJvYcCUfqvAJlb5dSwmY+DGMJjGWvMTWJeM+rQvVhcyy/DTRiJ9dq6RJEbNj/MIyZ07LOYIyBa986CicSBKNilc=@vger.kernel.org X-Gm-Message-State: AOJu0YxfpxSenLIp7BV/s/xTAH9qVWnBG37UynIbydyOQra5dl/8ZHgE nkl+eGHXqKCe41EbnGsVRkwHHXe/fC8y4DZLV/XRsBpDGdEid4ZoCwmiDFIepf3RUB6q1K2rsVv BzQ2M+Yhl7eYzSlXNVmvpYHw6m+6Z2m3Ujgp5wHPjdtyQnvD3kfKkWOkO2HSt+3sJMrE= X-Gm-Gg: AZuq6aL3tqkrDN40asR3IlzAFjnm+dTDV4hqF7LHv9ZazXWzQKb77XVHtbSsXP31Dn0 w4FQkc1chdrk/CP5/0x6ujMfijZTKc1+n+fAQ4h8vVzffc2T8DNohVnBAJIfAVk789alF33qYTC jJd+RxGIGW2R2FLtvknk8Tx2ig5meS+bNoMNM2w7VSxc62C+QjEa6KyPuqubRMplSVw1BjgOLr8 ITMWF0v8wDsx6OGZjmgQav1Ss/+3kz8xzN0XrPm8KoWaYyO0s4Xyd/R10B+XBqMfwMT8du47/u+ 8M7aPhuXyAUKFwtIh171DS9nQlRVBBNpfZTbe3C/T7/wK+KkOePmDOLLApZKhnpKLB6M16jEfvn yvMt9uWtXEkCT5tTC+lh9aYEsUTFi8g== X-Received: by 2002:a05:620a:44cf:b0:8ca:3d7c:e765 with SMTP id af79cd13be357-8cb424604b1mr1389479485a.50.1771314766957; Mon, 16 Feb 2026 23:52:46 -0800 (PST) X-Received: by 2002:a05:620a:44cf:b0:8ca:3d7c:e765 with SMTP id af79cd13be357-8cb424604b1mr1389477785a.50.1771314766327; Mon, 16 Feb 2026 23:52:46 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ac9d77sm29860229f8f.33.2026.02.16.23.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 23:52:45 -0800 (PST) From: Abel Vesa Date: Tue, 17 Feb 2026 09:52:26 +0200 Subject: [PATCH v4 6/6] clk: qcom: Add TCSR clock driver for Eliza Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-eliza-clocks-v4-6-5d09f28d4251@oss.qualcomm.com> References: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> In-Reply-To: <20260217-eliza-clocks-v4-0-5d09f28d4251@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=6777; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=kSfceoKoPkCgd7aDR+qYIcA97c3pxNAG8T/RrOOziqk=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBplB5AQoZm+JkV4dOCIsIyI+j7F7Go56+dlOmFX +Q9hUgLTleJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZQeQAAKCRAbX0TJAJUV Vh/7D/0clbUjuOxScSqTi1SBKFZdN0WJoGEqf80RJcwF6uQC9M6c2LCW0GtD1AG1rCGBIRd7Ef4 AHd3uxrdrELebfCyYZUGXMf6CPz69K/9EN6DJNzoYcS6NIQ13oNmQGn/Mk97Y3uj6XgLPii+pGm z0hbi5H8u9SZiZPrKhF/NF2MyjxV84EqwNDorBmL/NcdMBH4XmY/SyBo+6YVvAzh0hy5Ngap1qU 0uvwNG5JAhKNUfYk01Wa6whjRBJ4plWPTBU/OArHUvBiZgKcFBzjf4xlf8T0lJOZZYi8vctO6VB bsL6rcRCt2IN7yqnY71aD/99K4lwF2tik1aWW/6+MkhAHQeNyB1h947nUCilqFy9d8uXYa418tG ilLYKhXQdZroY+2QT+aT7O5DaKZXFXHoiboC6ZIqsvQY1QWvnPX5WGOsgwT8BMqvpclAaxFzqpm wDZUSbmJ9Idt8l2W+L+a48dYMIi8B+RIxlOnWolnCZHAmDaVLFor9lWxXHU02UXSCE696/O9oJ4 0Xvmuua9vTFbJub025UsZo3N48A1Drft3ZpiNyXlOs330PWeA3D2yEVQfOiqDvWtaK+LqVvY3KU dThPI7Gbx+6+cWXBcUVo3CE5GSyYntCzvKQfFIQViCFddhZSdTHOpJD8jHuZ0jKOFMBRjGy8cOx rZXtpqT9abYRDpA== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA2NCBTYWx0ZWRfX66LyNSu/84F2 Qq1FVy6vk6Nhk0VB0TioKgvtL3XW/y2/0HFO14xqGjkL5refuuwcab9m+/TNbbi5wSstWtMMyz1 mRM4RwuifOZY0BW4+PMEdPi4CKy3srDV3zEL1lbKfcrc0iJym2u3uEyltF1N4aZngelmVjo6PJD 03ZS7ZeRCtaSP/2Si6WEP5UxP/8K2INZkmEhx66gbt02xZYx/VQPMbNA5npLIJr6KLcQgkKdyvv v/CLecTpZoLPn0O5upYb/UAIvisoKRMHGNy3FLZimfdB1zmqj052gUcgpmqVTDw4/oDC+k9zy5q B94BJ7aaOPb8PpfexU9OFeR6g/SmLbHJNqC3hjoc+uu64/3YU2oTZArG7xMOmtBMaE7+7M0T0DB hcTqxnIkKJPvF/0iOIClnXb1lWXTanfIs3HhhOR8BBnr6yXrfSTwClBHSAoaigXv5ju4iPfqPBd B2UmtYux9Rv4bX47+Xw== X-Authority-Analysis: v=2.4 cv=b+G/I9Gx c=1 sm=1 tr=0 ts=69941e50 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=xMpycIIAKlYumkEOWPcA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: MX6HY_gbWock_LQdUtGQbpLDkr_EghoG X-Proofpoint-ORIG-GUID: MX6HY_gbWock_LQdUtGQbpLDkr_EghoG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170064 Add the TCSR clock controller that provides the refclks on Eliza platform for PCIe, USB and UFS subsystems. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa --- drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-eliza.c | 180 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 189 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index edac919d3aa2..dce21e33e366 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -28,6 +28,14 @@ config CLK_ELIZA_GCC Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. =20 +config CLK_ELIZA_TCSRCC + tristate "Eliza TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the TCSR clock controller on Eliza devices. + Say Y if you want to use peripheral devices such as USB/PCIe/UFS. + config CLK_GLYMUR_DISPCC tristate "GLYMUR Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6ec63a5d4363..d2bbaaada826 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_GCC_8084) +=3D gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) +=3D mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o +obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o diff --git a/drivers/clk/qcom/tcsrcc-eliza.c b/drivers/clk/qcom/tcsrcc-eliz= a.c new file mode 100644 index 000000000000..ef9b6393f57e --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-eliza.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-branch.h" +#include "clk-regmap.h" +#include "common.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_hdmi_clkref_en =3D { + .halt_reg =3D 0x14, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x14, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_hdmi_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en =3D { + .halt_reg =3D 0x0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_1_clkref_en =3D { + .halt_reg =3D 0x1c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en =3D { + .halt_reg =3D 0x8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_ufs_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en =3D { + .halt_reg =3D 0x4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en =3D { + .halt_reg =3D 0x10, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb3_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_eliza_clocks[] =3D { + [TCSR_HDMI_CLKREF_EN] =3D &tcsr_hdmi_clkref_en.clkr, + [TCSR_PCIE_0_CLKREF_EN] =3D &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] =3D &tcsr_ufs_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] =3D &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] =3D &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_eliza_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc tcsr_cc_eliza_desc =3D { + .config =3D &tcsr_cc_eliza_regmap_config, + .clks =3D tcsr_cc_eliza_clocks, + .num_clks =3D ARRAY_SIZE(tcsr_cc_eliza_clocks), +}; + +static const struct of_device_id tcsr_cc_eliza_match_table[] =3D { + { .compatible =3D "qcom,eliza-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_eliza_match_table); + +static int tcsr_cc_eliza_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &tcsr_cc_eliza_desc); +} + +static struct platform_driver tcsr_cc_eliza_driver =3D { + .probe =3D tcsr_cc_eliza_probe, + .driver =3D { + .name =3D "tcsr_cc-eliza", + .of_match_table =3D tcsr_cc_eliza_match_table, + }, +}; + +static int __init tcsr_cc_eliza_init(void) +{ + return platform_driver_register(&tcsr_cc_eliza_driver); +} +subsys_initcall(tcsr_cc_eliza_init); + +static void __exit tcsr_cc_eliza_exit(void) +{ + platform_driver_unregister(&tcsr_cc_eliza_driver); +} +module_exit(tcsr_cc_eliza_exit); + +MODULE_DESCRIPTION("QTI TCSR_CC Eliza Driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1