From nobody Sun Apr 19 09:28:07 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0274B32C33A for ; Tue, 17 Feb 2026 11:19:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327161; cv=none; b=T8wtdRPfzLY1jgVnBkqg6PZ7vv9KY6Uo0zLDutUEGK/ug1d8MNx8PV/VApxBFXm18km43k3mxqe1P6huYPqt8ioG/m9aU1QRsI9BP89PtUds5sZVo+HUhjOyZRGuykykWDIsil/BLO7KnU8WNNp9j+GlICpky6IYuc9c8IzQLco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327161; c=relaxed/simple; bh=5VNrPa5yioPWFjGZOM4dXOcXPUPcjXAmODnXjn9DUOc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bQhM6Sqax/A9kQ1eOcv2ErP7Cri8ub1TQkbvMcOZoNvvcluV1aLETIrl4XNisz1iXeD0IKbKMe7GwEbgiWQru3dreDi1/mgD1XDh8/58RdRwhAKwk4qK53JffUygkQJ1dOQhNBnwQam7viArI2XiXzHOesFsTc/9HrxLL2U4Lyw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=k3PSiT1O; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JBSYRqzZ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="k3PSiT1O"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JBSYRqzZ" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61HB3X061942820 for ; Tue, 17 Feb 2026 11:19:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9eiqgaf+oSJpBj2Bn5wVQjCwa9YYEJiu3YTycJF0zus=; b=k3PSiT1OjH4lMZsK +eJStrLWQNnGTjQxrrzum5yleG6R/pbRQOk3HKjaeliZR8CeCGIHWhqw2z3k3bYQ USF5E9nG8AWGv8jlmj93O8aRkJRjeLizSyozjlleznp2+O9b3yv1saqmxrQMg2FC N/qkrJsVwYHeYpmma7tFZyYhMV+K+BsOaegRViSUHbouzg+5vtx7oRV6drSfvvkm zdEoZKS+YE3zzc/oHOlWZsbx3cqOBTzHNeTWRzf3YJj6/gedtas/TksQzm51ougC 4Fi91+ydf5BraeTdIcZiprOoH/Tta2VJogy3Fg1u07M5CiAqeBA8LKju4wysg1uA ACfM7A== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ccq4g01f5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 11:19:18 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-8243a081fd2so1879708b3a.1 for ; Tue, 17 Feb 2026 03:19:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771327158; x=1771931958; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9eiqgaf+oSJpBj2Bn5wVQjCwa9YYEJiu3YTycJF0zus=; b=JBSYRqzZtutqS6Tynp7c1jNmO9DlvFE8zkXTo+oUAsK3SprfFWH9T1qjcUjNKUQEjC 6lbPwhLr6FlnzmFxJCvtY5KEUz4VNtajVsIzlo/fiybBX6rjRy28X/6BnOQV7o9vivsU 66OWxe/BVRVD8C8l1Ddy5qngGxH4yAg/GQUQ0PU6jhKqu9GuDA1hQAt/zhFR6psAtOqd uMR5OeI9iptNZUxQs65Qa9Sm2Bvg9Mqf03g8U7r/iq4caXturqKr+/3/tw64u7tL4zvY qaaS0zsgd/qk4+t1lGlR8Q/da4fKeUEjSGUbIn+EX0skMgpCwN7w+KJhva6/mCwMsgIQ iY8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771327158; x=1771931958; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=9eiqgaf+oSJpBj2Bn5wVQjCwa9YYEJiu3YTycJF0zus=; b=an1uYY3GHKRvmFpzLKO+5kgHCDInK+9gueSzONiMHbidWXm9MDOh2kpjeIFZyPhR+R MeZtnZULGnr4vE36G7Bsw/t8GOnyoJh0zrzqPu0FcfE0VMTeSznfemWN7nnImkT1hfXp iFN/nyHBvV3Sd/dBOBFPy9y1e0Ya4tTYwcDkWP7CuWwa2aVZWIqWOtIeu5syReDDI0UL uBBePqdCxRe291sIJdGxrTTNdYUl3F5EGLoKpuyX6ZX8aDjgSVxU3KdOY7/MP6/nHgd5 MMVZliK4XeFkjH0ROeN7a8kpBfEFke7HcXWRNXfMiZksaQUcH1NGo+gKoWdrki15KS6h mctw== X-Forwarded-Encrypted: i=1; AJvYcCXx9vtkz4geo3nzFMQX2IkM+TabUQSOEaOyODDcZvq5W+optnLFUKzpvVb01k/sRfUrXkHOmM2lZ5s+BHo=@vger.kernel.org X-Gm-Message-State: AOJu0YwLZtiwwLwT+bx7s+MGugfFh+GdFSk+/UDQofzUcu0nJxAlDVqR K01qrX/0svW3XHDVDYTtAr2WUWnfCMfmRT6yjI7dodwuKtjHSycw2ts09U0FGcxxjrPLKcuW7F4 tYPkyp39rCDhQy+16NvT9EH5cq9mlUEpcfwu5f4ty9GbcvgzhTPGnmctQo8Kp1nA4oO4= X-Gm-Gg: AZuq6aLgHYEBjEDFhI+R4jgVK2n2BvM4bRn2wwnjEucnCJG/+yTHb0tJ/HTFj9Rwnh1 w0paRdG1EDPUuqlCO14C2ogP11+nOqQ/+6vh1M777rSG4jdAp+Zu2xpLCwSAYD88IrwDA8H9rKa vJskOJswyjxEh/+12TjDExNz0yZD4OyifuSQnk+caDODbrhqcZH/VijvoB3lYRhl52706nZClzi zcxKhhVu+uqy0AU5J6p+kMokNQOMx9ktU2cURR2xY415GRlMxDXuHwkMz4f51+DSjRnvNVCkhaN t4YOB3WXRj5QalvzLtShNxs4Q8Jt5VE787zHe3bMureTDeplEWibEmCey6dpYcGZkuQ9R96QirY 7wuekZe9luP7U8uMVXug0cYf51DCHu9Nw8ivj7xHez3ZZqqK8MFdDykBg X-Received: by 2002:a05:6a00:12d7:b0:81f:5ec1:8bcd with SMTP id d2e1a72fcca58-824c949ad7dmr11646616b3a.20.1771327158023; Tue, 17 Feb 2026 03:19:18 -0800 (PST) X-Received: by 2002:a05:6a00:12d7:b0:81f:5ec1:8bcd with SMTP id d2e1a72fcca58-824c949ad7dmr11646592b3a.20.1771327157470; Tue, 17 Feb 2026 03:19:17 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-824c6b9a661sm13181914b3a.50.2026.02.17.03.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 03:19:17 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 17 Feb 2026 16:49:06 +0530 Subject: [PATCH v2 1/5] PCI: host-common: Add helper to determine host bridge D3cold eligibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-d3cold-v2-1-89b322864043@oss.qualcomm.com> References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> In-Reply-To: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771327148; l=3861; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=5VNrPa5yioPWFjGZOM4dXOcXPUPcjXAmODnXjn9DUOc=; b=eGsMoCR3RnwpV+cX/R2irzRnKPCBzeZrOnIZldX5d22y4OrPn6w5R6++P63dUeOwPgvwRrmBv y0NjhBhmG0cBIsIOV98eCu70NW/22EPqp6zbz0CTKFQknsolsw+70aE X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX+d3RQleiPbKx 8Ftf6Vbl36+QdJiK7dXdEaZjdMoYZ7Cnc1UwjGd70sy9XR9MTTLHqPvweffFI8+XQ1usIGefSdv Ywi71vJx3xbW7hwcCYn+3yjzDmK0g6VmjnBRmIh9V2zIu5fZBVbpilRBs2dQ57PlVws8VgFGQTg Y9WA/PXnKAi+i8xdm2FX80+53LlffoCB3F9xj7CfZQAsQCBwFKvW3woUt34sbJ5wv1c276YMBmB 5pQrUqAJViSp9SedymdGDtKTaJ6RqzEB+uNJ3KJRVsjfpYEfYzDA6q1KVo/3mcq5Z4deyqWGuwP uCzvtZA0zm++6qBHRBkS/G0gHnafrUNLqR6y+10yhOTZ8y/Ez9Fuf78g3sjfE+fO6OOxqUP5nxc cEeTacbv0Y0PyzfNfaVx86jZ8k6QRYO5NRXLzJb1ddMMFVoGFbU2iTS9/sbedClnZNyMfE4Doie XQGI3G9GHH2xgB10oww== X-Proofpoint-ORIG-GUID: _XWvu0DmUA84O-AtvVGDgLfSSxwQdSDe X-Proofpoint-GUID: _XWvu0DmUA84O-AtvVGDgLfSSxwQdSDe X-Authority-Analysis: v=2.4 cv=YdiwJgRf c=1 sm=1 tr=0 ts=69944eb7 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=R0UKu0mhgHHlQpweOhEA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094 Add a common helper, pci_host_common_can_enter_d3cold(), to determine whether a PCI host bridge can safely transition to D3cold. This helper is intended to be used by PCI host controller drivers to decide whether they may safely put the host bridge into D3cold based on the power state and wakeup capabilities of downstream endpoints. The helper walks all devices on the bridge's primary bus and only allows the host bridge to enter D3cold if all PCIe endpoints are already in PCI_D3hot. This ensures that we do not power off the host bridge while any active endpoint still requires the link to remain powered. For devices that may wake the system, the helper additionally requires that the device supports PME wake from D3cold (via WAKE#). Devices that do not have wakeup enabled are not restricted by this check and do not block the host bridge from entering D3cold. Devices without a bound driver and with PCI not enabled via sysfs are treated as inactive and therefore do not prevent the host bridge from entering D3cold. This allows controllers to power down more aggressively when there are no actively managed endpoints. Signed-off-by: Krishna Chaitanya Chundru Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/pci/controller/pci-host-common.c | 45 ++++++++++++++++++++++++++++= ++++ drivers/pci/controller/pci-host-common.h | 2 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/control= ler/pci-host-common.c index d6258c1cffe5ec480fd2a7e50b3af39ef6ac4c8c..b0a4a3c995e80e0245657f0273a= 349334071013c 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -106,5 +106,50 @@ void pci_host_common_remove(struct platform_device *pd= ev) } EXPORT_SYMBOL_GPL(pci_host_common_remove); =20 +static int pci_host_common_check_d3cold(struct pci_dev *pdev, void *userda= ta) +{ + bool *d3cold_allow =3D userdata; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return 0; + + if (!pdev->dev.driver && !pci_is_enabled(pdev)) + return 0; + + if (pdev->current_state !=3D PCI_D3hot) + goto exit; + + if (device_may_wakeup(&pdev->dev) && !pci_pme_capable(pdev, PCI_D3cold)) + goto exit; + + return 0; +exit: + *d3cold_allow =3D false; + return -EBUSY; +} + +/** + * pci_host_common_can_enter_d3cold - Determine whether a host bridge may = enter D3cold + * @bridge: PCI host bridge to check + * + * Walk downstream PCIe endpoint devices and determine whether the host br= idge + * is permitted to transition to D3cold. + * + * The host bridge may enter D3cold only if all active PCIe endpoints are = in + * %PCI_D3hot and any wakeup-enabled endpoint is capable of generating PME= from + * D3cold. Inactive endpoints are ignored. + * + * Return: %true if the host bridge may enter D3cold, otherwise %false. + */ +bool pci_host_common_can_enter_d3cold(struct pci_host_bridge *bridge) +{ + bool d3cold_allow =3D true; + + pci_walk_bus(bridge->bus, pci_host_common_check_d3cold, &d3cold_allow); + + return d3cold_allow; +} +EXPORT_SYMBOL_GPL(pci_host_common_can_enter_d3cold); + MODULE_DESCRIPTION("Common library for PCI host controller drivers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/control= ler/pci-host-common.h index b5075d4bd7eb31fbf1dc946ef1a6afd5afb5b3c6..18a731bca058828340bca84776d= 0e91da1edbbf7 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -20,4 +20,6 @@ void pci_host_common_remove(struct platform_device *pdev); =20 struct pci_config_window *pci_host_common_ecam_create(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); + +bool pci_host_common_can_enter_d3cold(struct pci_host_bridge *bridge); #endif --=20 2.34.1 From nobody Sun Apr 19 09:28:07 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7967B33031C for ; Tue, 17 Feb 2026 11:19:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327165; cv=none; b=JXMBZwKDKGMjc+ywIO5bMYduz/hImQtgVix0A5kKOsBnJYlZB3c+KED9A8Pg0QrdhVvo713Ys4PvNkX+BIV3IK7zAHXThH2xBYjGkceOlFxn4dNOGSFkIqB5xLAaIsIt2YHtAUpb5p1LmlfBW5szdwJkkp7jUWGkU5etEss1WpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327165; c=relaxed/simple; bh=TtbJw2QxkiBmLJKp1okcAfp6LW1NcrShntWzlulImc8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BCMyHk4TXRcygna8+ZiaJtVcYCMVJ0W/hrSrTpXwwiHoDFkwiLyPi1zbmNNxMmCRz3fleXPzLy1X4Rd94Om0py2qPNQRd5TuY53Op8oaLY6XQ9JZvwllzdrCnZGdvJnH/HZQoulk4+zdZO7v8u3cPI8vJJoI9klbx/DtaeUkKhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=OYHGcIeH; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ZmtPOfH0; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="OYHGcIeH"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ZmtPOfH0" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61H1lhbR1441859 for ; Tue, 17 Feb 2026 11:19:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= immdT9IL2DaXPDLwrAcUsFxixoY+wZMF3PrZeo1ewh8=; b=OYHGcIeHtSftBEjf JAIxbkCxa2n0CVYJXJgTn7akXtjzV4q+UW0WJxImaqudghK8tDhl3NVscWsw28ul 9V4zi0MCRnvmi5oBje9o5eTTIR/UP7e/8cVHYUMj71WPZzE/R9Rr0/9ny2aNDqoj R4UfvrVt3a4z7NUknitxrCDn64ab6HOdOY5RLPlfZHga2BW+vxZv0TGtiJLJL58E T4E75T+y7BUYxAsz/E5gqgxx+VBiqMMyM4UnoeYAlU+weKugg19LlFY0sx5gZbc3 +9M9VIAstoxCZuhKHDOJodR31csLsAvqn/JhweNlvJdd7AlhS2TmYBy0rQSVyFYJ yKn4rg== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc6a9t3hv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 11:19:23 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-8245982e538so1856687b3a.0 for ; Tue, 17 Feb 2026 03:19:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771327162; x=1771931962; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=immdT9IL2DaXPDLwrAcUsFxixoY+wZMF3PrZeo1ewh8=; b=ZmtPOfH0u91n8YGLxpjIYSB7QeWwLMa6+azdjWNOs7KkmDV3y0ETAGkx6LrLfEKNGv Vdq/6pMYlzydGiVDW70GYtJBqi8mWy0KAQoxoPhVwdvxwatpw1BC8PG1Yg9T36bHp4Zf eFIV0wT9KIgZRhOkY/RAwbsXiuZQ954I4vQZTKrWOjk7wbZndBkzRS2QgTIg20hDE2NC xqrAGhdt8DJwNoDdjl2xTzmF+SGyfKRlIj2PLsRwQUKF5sJDBvc189ddGS8ceqvwiRqI yNSUV7R6IIRiPVYcqtYAlBJ9D/TrJVzznv/fRN5p2Xo4hOkLRoyd459HMTLIMCWQVQzN rEUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771327162; x=1771931962; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=immdT9IL2DaXPDLwrAcUsFxixoY+wZMF3PrZeo1ewh8=; b=WTjT5n4svUEfnMcEw5qodICD1mqKOoylClNN8uDLOOo55mgVQ/8ut5gSsFfLEIXLux ewCgEHvGID6wcWwkE1yxe9gym0mEugFXXRmdeY8DmZS8bdfggtCo+QMFCgmg4EKcIBzU V6RilvgCSe9Uo/CPGUTP41+sbmCd1X6ld4AwM92NN1l9RUiclG7uboSIty77NpWax6lB AuEhJnpf83fB0NoLZCEttSIl7357RyLKyTq6BZzIkr2E0jz+qa7DVwTDKcCPQirwyfYR oSsaLuchYIj0T/GoNOjmPFFXGa2/xWLQY/CNyfH07hSLP1FxCgCjGdoaMN2Ww9hwQTyk bwrg== X-Forwarded-Encrypted: i=1; AJvYcCU2QATyRddsmfbjrTWWG2zVO0bThllMKcfPV9B6mFMu0f9UJqfqPjsuE72ieul73xqQ8/evS5ko6yS/t0c=@vger.kernel.org X-Gm-Message-State: AOJu0YxbFjJlOC2HHOZ7TXvSEhOhs0Eu8AYHpBH82hRvO1D97NM7tJ/d dHLM1tRGnM8RRXdWGr73myHmqowDIkPhag8NFFMMIzvSY6YpTnlsrUzWcZux6WMhbHMqXmtZ880 LBbpfrqAKY5UxaUlN2XdvJS1GQL91gApLrDw5BQMxrOnb761HYa9ODrMnm/5QrmnzTzQ= X-Gm-Gg: AZuq6aLpeEMymKXVAav3jpg2hrT0Emnh1Yoo0hxd3UhYYX/73spm9unHGS3ys0lVLzw 2qloBySaBnVt9wGEf4qSw9rtUwh+IWyb4ckNeGvMr1wr5F1dIw5F516V3neCghGolSekYBG869M PFsiAj74Ak/DaJiP5a316oDg65ItGuIvzJxdbJ6RiOUCWvUduQi22VduHgqRyFfNTTMQkJc6A06 DkrONiTreXOdWpxfRQ0gq3TzFImcp+KVUkmVDgfrStwtOegV6N6dJeA5DjHmerKkNgKyJs7NIkS HsI1nNJktfAvScq/lNaP7PfYENfif9/8gEHKqemW9xZRugz4HQWJSDy8Qcam9SLuR0LUYXqCaeW 24VEJePc578hRuBa2hnqll16FLfLup0c5ofjYd/wBEr9NocgQcJoQ4L/r X-Received: by 2002:a05:6a00:2444:b0:823:ec5:430c with SMTP id d2e1a72fcca58-824d5eb79a4mr9451783b3a.29.1771327162389; Tue, 17 Feb 2026 03:19:22 -0800 (PST) X-Received: by 2002:a05:6a00:2444:b0:823:ec5:430c with SMTP id d2e1a72fcca58-824d5eb79a4mr9451756b3a.29.1771327161858; Tue, 17 Feb 2026 03:19:21 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-824c6b9a661sm13181914b3a.50.2026.02.17.03.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 03:19:21 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 17 Feb 2026 16:49:07 +0530 Subject: [PATCH v2 2/5] PCI: dwc: Use common D3cold eligibility helper in suspend path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-d3cold-v2-2-89b322864043@oss.qualcomm.com> References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> In-Reply-To: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771327148; l=2041; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=TtbJw2QxkiBmLJKp1okcAfp6LW1NcrShntWzlulImc8=; b=YWmGKKIDBl3wYoKkpN/uTl2ahJVwSeE+5nhAt6wtBrGX2sN86iG3g8H4fNwHYNFYCQvszbMOM qBFuDArb0YoDjIliFHrt0hfLTqnbaWrwXLZ4WkXsz6TBpW+1rxpcmoZ X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX7zGOyRRGqXeW BWyqfHee8M57KMKV8A8cLHoi1LdzSV275jeiUQqBkkRmMESKuI55kknN+YqyVkL4TjKx4GejYpF W2aOqUccQzeFr7eDiHGmLyRhQy8fsgkLgwPTBR9CY+aIi6URbVE8ZdIy8Qby9FPo1MKy0B7f9ai PtM7sTjcNZuQaPCh1qO1K5g3B3/4Gd8rz/51Qpwcqz/yZVLveSMEY8kw8EOtWjaUBKV7V6sF8Sd 01dgAz/Ee+BPtJt4zQQz9gSI72n+y2y/kUY8ZuFBf/MQYKL4/EenjFDD/usezrJ8iqfFA6w4RP9 LKBZuYkLuukWtBdcBu8cKHhmDqxS3rOEa5DyVUiHSJNso4An+ew2lrR75tFQCfhT6b9+f/dSFRZ 9r/nQ3/GN+RXFI9sODUd95asfTzT+kAkuQsKMeycg8G1gVUk7Ofa0krewo3dtPJyhKNPAdy7zkq nK1NdnCsQ035TwqB6zw== X-Proofpoint-GUID: gie7H9_2ZER-aTXLREMAZxvvLpzR9omX X-Proofpoint-ORIG-GUID: gie7H9_2ZER-aTXLREMAZxvvLpzR9omX X-Authority-Analysis: v=2.4 cv=TPNIilla c=1 sm=1 tr=0 ts=69944ebb cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=ir7Wv4stjHWE4dv3774A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094 Previously, the driver skipped putting the link into L2/device state in D3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect low resume latency and may not tolerate deeper power states. However, such devices typically remain in D0 and are already covered by the new helper's requirement that all endpoints be in D3hot before the host bridge may enter D3cold. So, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with the shared pci_host_common_can_enter_d3cold() helper to decide whether the DesignWare host bridge can safely transition to D3cold. Signed-off-by: Krishna Chaitanya Chundru Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 6ae6189e9b8a9021c99ece17504834650debd86b..713aa64553bfc988717cab29369= 35bb43aabd72c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -16,9 +16,11 @@ #include #include #include +#include #include #include =20 +#include "../pci-host-common.h" #include "../../pci.h" #include "pcie-designware.h" =20 @@ -1218,18 +1220,13 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) =20 int dw_pcie_suspend_noirq(struct dw_pcie *pci) { - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int ret =3D 0; u32 val; =20 if (!dw_pcie_link_up(pci)) goto stop_link; =20 - /* - * If L1SS is supported, then do not put the link into L2 as some - * devices such as NVMe expect low resume latency. - */ - if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM= _L1) + if (!pci_host_common_can_enter_d3cold(pci->pp.bridge)) return 0; =20 if (pci->pp.ops->pme_turn_off) { --=20 2.34.1 From nobody Sun Apr 19 09:28:07 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF9A4330641 for ; Tue, 17 Feb 2026 11:19:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327169; cv=none; b=asBjOX4CdlAQSScdWXkXTJhf8fK98vf6Egrd+Ug1lmhL9TTXzCCrgQZ2ggI3J/sTX5z0lg6TzEOLq7n1hjJuvqSy1/O4JsdcuroJB+EMkTelZ14cj7SML5RhHHjN21mGzObCvcQr4LfExR2LCBUJlOfyBchM14Hslmv/0e4d+Xo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327169; c=relaxed/simple; bh=ZcPk/Vi6V1NIpnr+WX6LGNudzcSd+NdHRwSIluMD/yo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TXAJKex9aG/xTaHPphseK6gc5OHsUjTxafxm9rR90kYUxz/up8FOwLlG4rIIwGjS2eJjMHDf59/ohorqv6QB9u5IsE/6U/LbiLrTCEfH6E6fmYpVVRGuuGnmAwGfVmEFXsEL79VWkZj/99VxE+0ARpbc/jrcSrRi94bol0tuOeg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=WDnVMHKn; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=BpaX50s3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="WDnVMHKn"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="BpaX50s3" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61HAgBuP2803104 for ; Tue, 17 Feb 2026 11:19:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2UqZI7iscHApYsWoxbSsIfOsBYwdXDoKOyc0XcojPzw=; b=WDnVMHKntMf7wzZf UJmFZWlfxOYLtbv4YWo82GzWA4NCgzanGcG2qFwa0HbXJjJaS51lkTfLard1TyNB urMSPCD0yIvFwxvT5j/qDX+vbeBG+xXdGSFsb2U7n3G42uqPWhBO+FVb4CG/D4ii dJP/+CpkgPwLgC3QQ/174RtPO7EvdEauzKirHDx+W6kWxKxQSW1Mv/Hpa0c0JPEA F6NIgEmAzimJJETKH1iZhhD2ik9O3l2VbvjaEfdugAc6oDWGkdPAcuo9IbtmKHMI iXyf5ixXPu5ajFX7oMKqpORlwBC2PFJVJQ+suIC1lBbD5wqvT8PO9ASZwTyWNpUh zfc29Q== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cbyxuk62b-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 11:19:27 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-824b5637daaso2062508b3a.3 for ; Tue, 17 Feb 2026 03:19:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771327167; x=1771931967; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2UqZI7iscHApYsWoxbSsIfOsBYwdXDoKOyc0XcojPzw=; b=BpaX50s3Zme9ORAJO0/48XzTSMUSZC0flSzq9kLV+KKzvYey0+aLLG1m8nZcMlW/xr LIArFfhbCMb/6eJoIxF6pitpqeCFAgS5NPLkA7WsToRrpBddM4jBrKkvQI+eQnsePiAw Tt4agj9seLQTNvbS9MRt0SP84CFiSleqM0DYHaNHCqXnEmw69GB4wUoMBh/DXXuiAdUG REu69sOGROXmJnxn5Q0JPzCpn+Wiew8iwuM8ICdW5bDMgttu2kL9q9ZXO8CsbNTt+m73 zhSSXMCzwR4GgBxAdOv4rZiZ+NwzZZrhvT0AoJWaqE9WPnvjcYNdOIeVAyFQMDcyG0Ys JgHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771327167; x=1771931967; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2UqZI7iscHApYsWoxbSsIfOsBYwdXDoKOyc0XcojPzw=; b=st7L7WxD6N0qUAAg74Kon2ne1dyLJyt99KPPSNVdnE65UmiVThTagRYLEpgpLFOJiF irhY+xCcw5QWGGCyJYTZQx2bKy3jGAoDB4r2cF1oqMN+lnb3LFb38mXSYZzRkYnCyUBW SC8U43K+HIpTt346iYj98ywasGa6U2vg49Z9dqyw8+YqhKSPuPx3GQYYDh+76JezSKWA IBpeXjhiGGx9SxkXhFMW5qd/RApBXH1Nt89YjQtrDzGNex6m1rWWc3T4+i6wN2iniNVu c8fpNwI88SCWzFD0oizlzYOHnC3fMGysjf01o7hmj6+DrNssHWNJ9+hFmUetFCZpW6ed pqJA== X-Forwarded-Encrypted: i=1; AJvYcCW2O7A/FuiotxJQvykCyKXw9/r7wJ48wCjN0TYN9IsndRhcWGY5O7Hyd2HxLWu7+wJu/Hfp0U3rBd8QlhY=@vger.kernel.org X-Gm-Message-State: AOJu0Ywk03y+9lktyX7o52P53/6ntEaHNNIsy1LVMt+izW7uA5p2w8sH Djd68O0gmPrmuuH0QTqZEirQs/8nakrY+7QFlthQGqABO8UgkqIjI533ogI3RADzf+PGdi3yaPc rPFCAVFDlXIxt6iIp+nHXMefV67Afew1G5mVOH4mlR0dtxFYmwzHcHaL7TqmLqzk4W+c= X-Gm-Gg: AZuq6aJ2vP5siBiSO72fz9iGTFKm391YPgFNFEhyQTh1F0kK0hJ2Cnvf9UaxvCXUDyC hyGp1GTGmQu0MgTPSG9PKbpFWYfXAMv2WcSegbXt8+j/crTco9G4DB99evotbHlLv/yYTADf3SY 5o9DDLk5719qqiO6gq7N8Y8W/2ahrIpudZZuS43O+EeWrfpJbgG2d96+qnILSp7WxaYmHkmozYE PqsSwVIJIf2LwwDqJsu+ilLFhv4lScyAdhd5Ar0QI6TpFVcXevp57V9BoVxwz1xY335CGtKihon Xcz48Yb3L21tRR/jQpuM1lAVKuvNuM7lPAmaZzXQEPVhj825p8PkjSPCfpK2akYJbfmdoskFrIQ ie0c8CtgH01kP3vXkuBBW+8hcyy8QxXJruvI3ZIhPLxNt7NLmMX0j5+om X-Received: by 2002:a05:6a00:1d9c:b0:824:a8ec:ed51 with SMTP id d2e1a72fcca58-824c94defa9mr11493630b3a.27.1771327166772; Tue, 17 Feb 2026 03:19:26 -0800 (PST) X-Received: by 2002:a05:6a00:1d9c:b0:824:a8ec:ed51 with SMTP id d2e1a72fcca58-824c94defa9mr11493606b3a.27.1771327166245; Tue, 17 Feb 2026 03:19:26 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-824c6b9a661sm13181914b3a.50.2026.02.17.03.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 03:19:25 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 17 Feb 2026 16:49:08 +0530 Subject: [PATCH v2 3/5] PCI: qcom: Add .get_ltssm() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-d3cold-v2-3-89b322864043@oss.qualcomm.com> References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> In-Reply-To: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771327148; l=1721; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=ZcPk/Vi6V1NIpnr+WX6LGNudzcSd+NdHRwSIluMD/yo=; b=wlf3BtLYbA0NMXS2gRRkF9fo7E6YylcdKwmuOeuLWkmOYXxzeUzOvslTykYolcdSeh7TY+Q2k oYWx3bF2miTC2jawLmAMHHvoQseCHBVoL4fWsMIbES9uNXgRXzf+7Hv X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 3iYl89kE7rdSRdZhDWSS5SalnzCuhUK_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX5uLuKlk7P27c Qaf9yN7ZTil+03uajgujOIcvA9tevPsvBqEFmpJHKJwPPJ30h31B0Vtq+HTm2xCqVXuqueU6FRn 3d9uiSBOjL7n6GecJrVPYK4rBclpiVtQuH9lKZol1zW1JA3YGxcK7hlkDrQbn48vP8tRxf5vnHf zQLH6Bx9S/OiDtfp0HjscsLsphxyGEv+TmV2oDxRGOVDFmP63fn2I0pJzcRrTrWbr17rYlrltjM hRmpD8wxZrmTb8eabZOjqnIz05DWgihoXkeVx7SbHJdg9pHUXHFzMzdOK/sWjMEzLX7TN3wd3xJ 4PoGbfpVbMMEGsqysmDWWbmAm3xcGNKoDe9G1IRrWenVPxAQKmuMd82IMnm8/FD61cnBww04FBt wL4e3++qtfkbZptUTmF0cOI5/1bGo0zOhmW0CsTSHeGXlybMz8A3TnmD4xqHyeXVifXGPv96bVC M+UpLZISpdqbK+OkNeg== X-Authority-Analysis: v=2.4 cv=BpuQAIX5 c=1 sm=1 tr=0 ts=69944ebf cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=Py5lcOcq67Lbq8UMOfUA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: 3iYl89kE7rdSRdZhDWSS5SalnzCuhUK_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094 For older targets like sc7280, we see reading DBI after sending PME turn off message is causing NOC error. To avoid unsafe DBI accesses, introduce qcom_pcie_get_ltssm(), which retrieves the LTSSM state from the PARF_LTSSM register instead. Signed-off-by: Krishna Chaitanya Chundru Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 67a16af69ddc75fca1b123e70715e692a91a9135..2c4dc7134e006d3530a809f1bcc= 1a6488d4632ad 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -131,6 +131,7 @@ =20 /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +#define PARF_LTSSM_STATE_MASK GENMASK(5, 0) =20 /* PARF_NO_SNOOP_OVERRIDE register fields */ #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) @@ -1255,6 +1256,15 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci) return val & PCI_EXP_LNKSTA_DLLLA; } =20 +static enum dw_pcie_ltssm qcom_pcie_get_ltssm(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u32 val; + + val =3D readl(pcie->parf + PARF_LTSSM); + return (enum dw_pcie_ltssm)FIELD_GET(PARF_LTSSM_STATE_MASK, val); +} + static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) { struct qcom_pcie_port *port; @@ -1507,6 +1517,7 @@ static const struct qcom_pcie_cfg cfg_fw_managed =3D { static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D qcom_pcie_link_up, .start_link =3D qcom_pcie_start_link, + .get_ltssm =3D qcom_pcie_get_ltssm, }; =20 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) --=20 2.34.1 From nobody Sun Apr 19 09:28:07 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CCAA330B04 for ; Tue, 17 Feb 2026 11:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327174; cv=none; b=guBFSw8iRk2Nit+Inq9BXqwsULZS2160+z1pjXAzbeWXydk3x//ZYDIDC9RtlLQiqTd5S4J/Qb3OTsBwGkir5k8wp2EDw9aDFxdOFmVutWXtInscnPrX/hyISydGu9J+Ug+Jmxop/pmmExuth4lUmWt/Yy4jOWrK7eJvL4zmuPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327174; c=relaxed/simple; bh=RI4q6fSSubOmDgNNa0gqplTxflnkQiZtd27PDlBbjys=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u3NRXGw7yXFmUt0cepa8H8w1mt0WSj4WFhQiupWXBPXuxoBjvcsxoMerKL14nubK9JoEw/YeThAhe7cvISCInCBezkE0DDILQvG5xV5oAf+Cfmxw+TvM59SyS3spgyUClyZZNDTBhLa36/BXTV3KFZbb5MDr+50IC8QQo0uYpwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NEL5cgui; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=eFtmxDb7; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NEL5cgui"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="eFtmxDb7" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61H0GvPn1973499 for ; Tue, 17 Feb 2026 11:19:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Ufl5jZDzffZq1Bxrg/McQqGCvj9/TyQy203e6kES/BI=; b=NEL5cguilh1bR/cM a7PuV9BQ7AW0HX4J9m2MdiGrG7Fp46J7YHAotQdZJ99z6/tpvSWGq5aapmVf6WIl mVHE48iPMzUegKNvvF+8XDpPBV7klhOu65cFgU4kb6HhUepYDIuWqTZE6VLlc/7E 1gSBeEnAA2psW0prH43t/H3TNRGYcS+PAIrHPpicWQV4fbanLwIBkdwOVheoo7xx tw93XnNt/gsh6CuvrcyOLmlr7h14cePr5rCZVtXh5r+F1JrWOVvFrcdYlnebaykL DsrkIZ/OWeTcCqUv5blkxgBJfWSGrZxbch77/zrE+qeiuACaIloYhimyD/+pAOzX DrcxeA== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cc662t4v8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 11:19:32 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-8249ba7f6e8so1899359b3a.2 for ; Tue, 17 Feb 2026 03:19:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771327171; x=1771931971; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ufl5jZDzffZq1Bxrg/McQqGCvj9/TyQy203e6kES/BI=; b=eFtmxDb79BG5Rkqb+xGKLy77w0mcHOeZHZpr53xwMaCNvO1qM2ebhnXIbpL6FmHcfb fAuQQRfN9E7eUnjL/FFV0HgzDHPMyGYmN9nV8aZN+86eKUjl96FtzJIEuhvNWpyC4C0e lrfXl10UwcBi9cfyquWlfkpt/4PJN7qbF1RD4T+J4BV3U8TyWdKKM/0x/fkkSyrb4dQk tvUrCd8KVqu8hgbl+f9y+DZYR0afaJv3DMn4t8XhABBU/FIqy3XQUjnzRxKoDOzFQXsU 5bnoGzTbKx8n7gaXhMwjP9Cwsp8SAXDqULS3bRgREeywW7UOnHkmqZMD8txrW6R/3oZc TESw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771327171; x=1771931971; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Ufl5jZDzffZq1Bxrg/McQqGCvj9/TyQy203e6kES/BI=; b=SZ8JhFVeRwt/OoOuaLzb3a7BW6LD2U/cPDXH+20cDbEgKJUcN+xMfN4EOzOthEAEDn MA7RcNUsjjmR1LyE6dQGJ+MDDa4EezxWTPYinemFTlhlTUUK8XzRGRZKHR6wRpZOdhmq BLIvZbPu+HLHPX5hLoqjcX5EiwgiNUZHic+7LyYjKVx1GukSu3LlMjU0oXO7TaGmiV1R ZPJPRBo1fERpi5ckZVpyEQBi0HO0MfdrOaxkCWkqTUPRELhyPIgyiYF/k+Uu+XBiRo+b q3GX2PZs4GQB7UDzqQAshjPPkmSkuVP/43I1DHqPSaVfeU/HKPWk6Ji2R1uatv4tyKI5 pswA== X-Forwarded-Encrypted: i=1; AJvYcCV6U4dB9S5iNRZWfTiiAHYjSXWhvGu+DJO4qYfiZGpZzotA3iCUBozDcd0mx1bG3HBl30SGfFDPY5VA3zA=@vger.kernel.org X-Gm-Message-State: AOJu0YzByWTDv9dMKJcBmAZ78t19ju7gg1sl+SJeU4ClTDUpfUb14FA4 qPS0tIFkHqGaKmnoUspNRgEKubwDNj/XZC7Qiu38ySVDCvncPcSI29jcqz4SkvH88o81WyLvEN7 m+Sn/f6T2qz2uy3eLegsrr/O4fAgVEevsGCoMhvFng/3r7KMaJN+MVlfEJmlteJOimq8= X-Gm-Gg: AZuq6aLozM4qxScONM0hEt0kBAb3QC0/PHS5AgqQmno7ift5XI6Mp7e9jgHXAHf2+SR Avzbg3GBjtquF4LMY4VotB++cNjsALjex2c7J8vUgiDzpYhfttmxTGgoOWt6XddXhxk6o6brcyH mN0Ttumkm54jLUjpCvYLYUMyieCYW6YuRKn4cKcT4yGH5FGvgO67NWx4ExY7el6xKx9qWe5aC29 aFU1UOFedQtWH9xkB653hxs5Jjl8P5y8H86QiQFxUEVUGVbnDzNtKoSZ8R98pqFJ1Zg7d6MlJIo wcb+z86gXd3D0paWiVlKmJCyFqogjcxXcveXDaAypKkNXuLrj3sv7hd2rBupd/bAdbdrXerQMQd lE77Zlt6vdfyt9/mfkagGnqkfEY6ojJKJyBYbDK+U7KxYL+KxtoqKHaIC X-Received: by 2002:a05:6a00:4acd:b0:823:1406:8797 with SMTP id d2e1a72fcca58-824d953488cmr8975255b3a.31.1771327171082; Tue, 17 Feb 2026 03:19:31 -0800 (PST) X-Received: by 2002:a05:6a00:4acd:b0:823:1406:8797 with SMTP id d2e1a72fcca58-824d953488cmr8975235b3a.31.1771327170627; Tue, 17 Feb 2026 03:19:30 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-824c6b9a661sm13181914b3a.50.2026.02.17.03.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 03:19:30 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 17 Feb 2026 16:49:09 +0530 Subject: [PATCH v2 4/5] PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-d3cold-v2-4-89b322864043@oss.qualcomm.com> References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> In-Reply-To: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771327148; l=4007; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=RI4q6fSSubOmDgNNa0gqplTxflnkQiZtd27PDlBbjys=; b=li0xu+gi3ab5XV55aDVCdK4EDUgeaa7g/6a4LpfP39jcV9HM2K+TWtxoLN665Lm7JJn/gDR6A p55CKSh6k9fAoU1f+ldOyKH3B3W6LSkcx7zyXglg17snwRy2jUfcT+Y X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX9SXITx62V4Ee 0WGC1npEkpQHeJx465UPjviwbV2XCZqDRBWVTzHpkx2DMiRvBPmDSIMzxJPHEEz8DEVkDd9NtWd egW5kOvwseGijmc3xQcpgoR7mq7E6YABS3/hb4gOSw3P5P45RvaAxFWUsBoKpo4kMDa19Mvw8E5 GWd7+Obo5QI969JCUHP+Mm+fhKFyrrzH1YP4c9cKqT6kBWXKvMbRwMGWZgMz1/o2rQGYulLtTL4 DpOKAgZnYn2ptB8/xf5q8wiD84yrucobFtom9EjOG9keLO3NmT1k279dYiJxx4Mj3SC0M6N5fR2 PhYkWppTK6DPLVyTGCP5pBeLh6FtUoykxpHJD2/5YAHH4l20ObQCZRf/q28IFhXptxv0t2mXpTA GjhItlWWYArcC44d7BjFvEIFEAvWreQ7mRda9QyF3lnNGMdH/2R6/sD9n/fx2aBEDu2frRc6V87 7wmP92ilaEJoQfMwodA== X-Authority-Analysis: v=2.4 cv=Y6b1cxeN c=1 sm=1 tr=0 ts=69944ec4 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=h4B-02p0z56_JbXvspoA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: Dzi4dBDVumtoxxQr1Mx-Sy79IYZraQdM X-Proofpoint-ORIG-GUID: Dzi4dBDVumtoxxQr1Mx-Sy79IYZraQdM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094 Some Qcom PCIe controller variants bring the PHY out of test power-down (PHY_TEST_PWR_DOWN) during init. When the link is later transitioned towards D3cold and the driver disables PCIe clocks and/or regulators without explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain partially powered, leading to avoidable power leakage. Update the init-path comments to reflect that PARF_PHY_CTRL is used to power the PHY on. Also, for controller revisions that enable PHY power in init (2.3.2, 2.3.3, 2.7.0 and 2.9.0), explicitly power the PHY down via PARF_PHY_CTRL in the deinit path before disabling clocks/regulators. This ensures the PHY is put into a defined low-power state prior to removing its supplies, preventing leakage when entering D3cold. Signed-off-by: Krishna Chaitanya Chundru Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/pci/controller/dwc/pcie-qcom.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 2c4dc7134e006d3530a809f1bcc1a6488d4632ad..b02c19bbdf2ea5db252c2a0281a= 569bb3a0cc497 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -513,7 +513,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) u32 val; int ret; =20 - /* enable PCIe clocks and resets */ + /* PHY power ON */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -680,6 +680,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_p= cie *pcie) static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res =3D &pcie->res.v2_3_2; + u32 val; + + /* PHY Power down */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -712,7 +718,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *= pcie) { u32 val; =20 - /* enable PCIe clocks and resets */ + /* PHY Power ON */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -844,6 +850,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_p= cie *pcie) static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; + u32 val; + + /* PHY Power down */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -994,7 +1006,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 - /* enable PCIe clocks and resets */ + /* PHY power ON */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1065,6 +1077,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qc= om_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; + u32 val; + + /* PHY Power down */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); =20 @@ -1169,6 +1187,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom= _pcie *pcie) static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res =3D &pcie->res.v2_9_0; + u32 val; + + /* PHY Power down */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); } --=20 2.34.1 From nobody Sun Apr 19 09:28:07 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1B41236A73 for ; Tue, 17 Feb 2026 11:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327179; cv=none; b=rm6U/iljFAdfNd3Vq+9iT20UxJZxazC2T5fl8AQjwlvTcmj+IZkeshtnhkrjUQag8cutepdYnbIwjLdw4rGkvAOBi3hYhjtufJwBajOay9pjho1QibsnTAXH4nm1v5RNQHJD3UJAvxUi9r/zQrrF7EgaLjGozaAcUFyxoMtzbEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771327179; c=relaxed/simple; bh=IAVEMPt0tOVYVQCFgBm15tr3uSMRBtLlDbxbCnOFZrQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B69nVnjb1IoTLIfV8/BFeR0Vl4/zAAX0S+QL8W16f065bLh/cPp7UprSJs2GTNhze6JgKmCZnYDUSmbQqJkvtbzSvnlJ94TXuNieH1SAfnrrAIIvUZ/LF133hxy1fcBMWqn2p2s19FLpDGJXM+AfnczlyyylppGxvtoGxgDJ6/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=UsNyqI0P; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=boqNUyMY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="UsNyqI0P"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="boqNUyMY" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61HB4ErL1944069 for ; Tue, 17 Feb 2026 11:19:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= rMBPdn2LsAmivgwpb9UlFxbQ9zyThXTU/1K9VkXS3k0=; b=UsNyqI0Pm/RmWoKl ymA2wqIzXteu5X5pBcvJ6asNk1aNLXpsaFUORhO3J/G24jq7mbr7a8smaMha9G3+ LaBYZlcaXmO/UtpQ7ZlD+48WYGsmSUS6MlVLZV+Uff1Uo89y4/mqxccHU8jwYZLt 3nW+V6heBwywIxUGP/zKp/TAfkoiBW6yDjjG2MoHCi3mJJdzjTLctRzkfl47WsJ5 n7rUHjnIEIKzriLWiCYYQ1JMK5UZma7bHyKlq20eiI0nG+J1L0wj2hrCG1GQaCtP KltZ6j0esTAhfMDt8hwm7mFOBrbDVX35HC820e4+l2dVh3hjUEWMIR7sVQMak2U8 ce/Udw== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ccq4g01g7-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Feb 2026 11:19:36 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-b630753cc38so17018750a12.1 for ; Tue, 17 Feb 2026 03:19:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771327176; x=1771931976; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rMBPdn2LsAmivgwpb9UlFxbQ9zyThXTU/1K9VkXS3k0=; b=boqNUyMYdAFS+DFLCLUgqd1vX01La8ck8o3gdMKc2L9Bz97W2ZxQicBDKmHRoZl7ZU sO/EQKjAcIydcTNnBCz8NK60uEW7FNF4ySsA+nVFPW7N2p33lzsF3SUH7OLVXPaCRHbZ 6Rxcpe5iiFx8cIQypokIOzoHs93ss/uK2yKob+V72QhRQ8dBM15Jwx4TpBtKyCv6+YIK oIIQMkhIMokpELWulMx1dhbc1WnM6byplLUGkn5VSCAzgtNTvBPhoWKr84epY1KMgxAs QhkjZnNanRAanoRtzzjtFSmNBODaSxRL2hgbXXVbjo2LzW596n2Pj/cl2mN0gB/UI5LO pRuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771327176; x=1771931976; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rMBPdn2LsAmivgwpb9UlFxbQ9zyThXTU/1K9VkXS3k0=; b=UuIDZJoBixUmmCRJMI5jkBUWIgnAK+e+RfwDoltW5m7YR8ek6uPZseF6KPZVxK6RIy FQbmtl4ecAlsf7cjgo/qCBeohHDgui57nuOBHZ1JwSgqE6NrvL3lShCeYr/uxe1ofEKg YxMsxRox6TG6rdvm7KLE8HlT8MFggxds6O/EJy+ni2CvvXw+c5ELmR6SkbGhVk1YKup2 rj4XDH54P/i6qrbkuGXyITJ5E+DUr1edVvhesi0+prOxZKSyWCYNt6pLakBPfiGGELC2 AjNs5gII8VgMu2/ImHWYAc+cgUDZm7V7vOQjwQNp3EDqzicI/DZijM2cHmXYKJoXVd6U ZkdQ== X-Forwarded-Encrypted: i=1; AJvYcCVk0YdZ943F8KmzGRh2+cUnVfGR1ldFyyS8MjCnZ6HgcyeXCaJReankcL99PrJzVSV+2PD/vykGIqkg5U8=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0uUgpeHReLkOu9+Ksep8Wq0rY++WNr1kJf970fUrDOqYuu/1S 1gZ9mKAvw3sdOWOcPWt2dj5DOpUScGq3W2X324VD+AKCFeab0FBgM3gIKwj2Tv5832sn4mrbIq2 BrpXSMY5rNUsojXYmWUHsFoQnSUkZMqdhRy7SCzMzLCqlxWxYeGCPUbd/AOSBwrcykL0= X-Gm-Gg: AZuq6aLLWjY8tjCheoKqtyZuAlSSwshQEU4e/dSuOdEiDpFOeHV1D8T31JVwj69BzVh Rp1BN71Y2DsYe36veAzFVba36scWDMffwzoadSgyGfnnrkWOi4TWHBRtXZeATpnloU7yVVfNcMj C+Sr2d49ZmVFpFljXm8EJe6zlijQDQzDQnskG621WuEF4+S0jWge50BLy85UH/kmXfm6HAoQqw6 Zs/Kw6T7/Mfv66s8t3xF10+BYI8t/1VOWUBardOYX6bI28Ogb4pd37aOp0hvBOvKSMZJjWUuMxD g9jQhv6cBafnIG6E7NGHGkHxOIS3iz28S+3GU+pGJZV/hfuxU6BvWBkSAXmA3t4KErgqnM+kfRT KzGROFB+BfPBZqHxl79ekfywuI+n1D3SmSGj695yCIE2Fn7D1/1OmOUG/ X-Received: by 2002:a05:6a00:2d28:b0:824:374a:13f7 with SMTP id d2e1a72fcca58-824c613370cmr13273738b3a.55.1771327175582; Tue, 17 Feb 2026 03:19:35 -0800 (PST) X-Received: by 2002:a05:6a00:2d28:b0:824:374a:13f7 with SMTP id d2e1a72fcca58-824c613370cmr13273711b3a.55.1771327175048; Tue, 17 Feb 2026 03:19:35 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-824c6b9a661sm13181914b3a.50.2026.02.17.03.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 03:19:34 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 17 Feb 2026 16:49:10 +0530 Subject: [PATCH v2 5/5] PCI: qcom: Add D3cold support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-d3cold-v2-5-89b322864043@oss.qualcomm.com> References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> In-Reply-To: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771327148; l=6515; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=IAVEMPt0tOVYVQCFgBm15tr3uSMRBtLlDbxbCnOFZrQ=; b=wjF9Ok40l0LOgqKQkkPhl/h8dRDieyHrE+JHl4vXu3qG6H5Qh11tQtZ8Q5SfvNRzzzehxTmMs jJvG1KZaYAcBoHrk9mJo/xorBCcy23VvTGS4SE/tE4tf96AU3a1QeZ7 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX3GWW2EmNiMeH vc897boiTWB2Fr5AheWMjFFz8bDyE5U6B7nu/s76cbqS1NJKXvjNCJvYsQyLVpg5fARUOSjopdM fJeQThU1nRa6zlNQjf9eNVkjnDdhb4GCLX3DGTmbVeO73nBVykxeeymtyJJ2I2Uuz8l4DfyFHi5 2Kyf0WBPhwEBYI6cJumrBAE8dpXJaNOwuzEw2cM2ROLo1/gTRyp8fORDtnAd1gZuGmKkYHvFkhL 7cJMDdjI4oiEDRjEL9enF2YuNgPGDI3J/rSn7F/LmNQ0iA4h2eFNJB4XwByOaGZg0vOxMhA4qJe 8DxLOkh6/BQjjj6P/yZn36uz/VskyrluxjiKt1cp9eRN7KXDQclRXdXUjMdPzH2HufGuJj2hYFX BaEm+JcHHrOJyPEOm6LpjEwHN1qVTTihWuCuHIWjkiqx37XRVV1r2DXz/FJQNdK4yyPjeQ5h3OQ hGWVnNw90Wxfp0zcVIQ== X-Proofpoint-ORIG-GUID: 4c25B8CvKlPWY4DEwb6fDsGdPrVMSQ1I X-Proofpoint-GUID: 4c25B8CvKlPWY4DEwb6fDsGdPrVMSQ1I X-Authority-Analysis: v=2.4 cv=YdiwJgRf c=1 sm=1 tr=0 ts=69944ec8 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=RN3yzfvplrNe8VIVIhoA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094 Add support for transitioning Qcom PCIe controllers into D3cold by integrating with the DWC core suspend/resume helpers. Implement PME_TurnOff message generation via ELBI_SYS_CTRL and hook it into the DWC host operations so the controller follows the standard PME_TurnOff-based power-down sequence before entering D3cold. When the link is suspended into D3cold, fully tear down interconnect bandwidth, OPP votes. If D3cold is not entered, retain existing behavior by keeping the required interconnect and OPP votes. Drop the qcom_pcie::suspended flag and rely on the existing dw_pcie::suspended state, which now drives both the power-management flow and the interconnect/OPP handling. Signed-off-by: Krishna Chaitanya Chundru Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/pci/controller/dwc/pcie-qcom.c | 121 ++++++++++++++++++++---------= ---- 1 file changed, 74 insertions(+), 47 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b02c19bbdf2ea5db252c2a0281a569bb3a0cc497..37442bbe588c36b0b0414cc4d00= 16da2d8424a87 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -145,6 +145,7 @@ =20 /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) =20 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 @@ -283,7 +284,6 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; struct list_head ports; - bool suspended; bool use_pm_opp; }; =20 @@ -1401,10 +1401,18 @@ static void qcom_pcie_host_post_init(struct dw_pcie= _rp *pp) pcie->cfg->ops->host_post_init(pcie); } =20 +static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + + writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, .post_init =3D qcom_pcie_host_post_init, + .pme_turn_off =3D qcom_pcie_host_pme_turn_off, }; =20 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -2069,53 +2077,51 @@ static int qcom_pcie_suspend_noirq(struct device *d= ev) if (!pcie) return 0; =20 - /* - * Set minimum bandwidth required to keep data path functional during - * suspend. - */ - if (pcie->icc_mem) { - ret =3D icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); - if (ret) { - dev_err(dev, - "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", - ret); - return ret; - } - } + ret =3D dw_pcie_suspend_noirq(pcie->pci); + if (ret) + return ret; =20 - /* - * Turn OFF the resources only for controllers without active PCIe - * devices. For controllers with active devices, the resources are kept - * ON and the link is expected to be in L0/L1 (sub)states. - * - * Turning OFF the resources for controllers with active PCIe devices - * will trigger access violation during the end of the suspend cycle, - * as kernel tries to access the PCIe devices config space for masking - * MSIs. - * - * Also, it is not desirable to put the link into L2/L3 state as that - * implies VDD supply will be removed and the devices may go into - * powerdown state. This will affect the lifetime of the storage devices - * like NVMe. - */ - if (!dw_pcie_link_up(pcie->pci)) { - qcom_pcie_host_deinit(&pcie->pci->pp); - pcie->suspended =3D true; - } + if (pcie->pci->suspended) { + ret =3D icc_disable(pcie->icc_mem); + if (ret) + dev_err(dev, "Failed to disable PCIe-MEM interconnect path: %d\n", ret); =20 - /* - * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. - * Because on some platforms, DBI access can happen very late during the - * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC - * error. - */ - if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { ret =3D icc_disable(pcie->icc_cpu); if (ret) dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); =20 if (pcie->use_pm_opp) dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } else { + /* + * Set minimum bandwidth required to keep data path functional during + * suspend. + */ + if (pcie->icc_mem) { + ret =3D icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + if (ret) { + dev_err(dev, + "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + } + + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + ret =3D icc_disable(pcie->icc_cpu); + if (ret) + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", + ret); + + if (pcie->use_pm_opp) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } } return ret; } @@ -2129,25 +2135,46 @@ static int qcom_pcie_resume_noirq(struct device *de= v) if (!pcie) return 0; =20 - if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + if (pcie->pci->suspended) { ret =3D icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); return ret; } - } =20 - if (pcie->suspended) { - ret =3D qcom_pcie_host_init(&pcie->pci->pp); - if (ret) - return ret; + ret =3D icc_enable(pcie->icc_mem); + if (ret) { + dev_err(dev, "Failed to enable PCIe-MEM interconnect path: %d\n", ret); + goto disable_icc_cpu; + } =20 - pcie->suspended =3D false; + /* + * Ignore -ETIMEDOUT here since it is expected when no endpoint is + * connected to the PCIe link. + */ + ret =3D dw_pcie_resume_noirq(pcie->pci); + if (ret && (ret !=3D -ETIMEDOUT)) + goto disable_icc_mem; + } else { + if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + ret =3D icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", + ret); + return ret; + } + } } =20 qcom_pcie_icc_opp_update(pcie); =20 return 0; +disable_icc_mem: + icc_disable(pcie->icc_mem); +disable_icc_cpu: + icc_disable(pcie->icc_cpu); + + return ret; } =20 static const struct of_device_id qcom_pcie_match[] =3D { --=20 2.34.1