From nobody Sun Apr 5 13:20:06 2026 Received: from out-13.smtp.spacemail.com (out-13.smtp.spacemail.com [63.250.43.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B299E2F4A19 for ; Tue, 17 Feb 2026 21:40:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=63.250.43.96 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771364431; cv=none; b=eASa6JkJyWp8WyX+plFksGHg1mNwMVlcusU7RWsghdUF7A8SgvMh2dK8ce+srmerV94MjBipCZA+lFQLEx6Qky7BybMOISP2ZwP1Vt1mhhB+jjwtJD87ALDp/gYRECuInK9rAUIbkpFUyKcUrYFiLDO+SieKoMURE92GesoBe6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771364431; c=relaxed/simple; bh=HWs1IC84v/YwZQbKpNwoGA0gGWlv8oAPh64TkdQpIug=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U0dQHazJJJk/norK+NI2YV4n0LdBovvvYZrv+jHrjuQZ4l6pl1lQqVUoNR3ZdswkZHDN8wdtRW+EX3n1PBgCcllN83/tVGwQWZWsf2loZF16YcrsjrwQfCrAKXUYlZEcUsbcuN48Q1zh2SY40pYpofFcEjK+cVMiOmBNuH1sBhM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=r-sc.ca; spf=pass smtp.mailfrom=r-sc.ca; dkim=pass (2048-bit key) header.d=r-sc.ca header.i=@r-sc.ca header.b=M7VU6osu; arc=none smtp.client-ip=63.250.43.96 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=r-sc.ca Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=r-sc.ca Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=r-sc.ca header.i=@r-sc.ca header.b="M7VU6osu" Received: from mac.pk.shawcable.net (S0106dceb699ec90f.pk.shawcable.net [24.69.43.232]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.spacemail.com (Postfix) with ESMTPSA id 4fFtNX09XLz6tkL; Tue, 17 Feb 2026 21:40:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=r-sc.ca; s=spacemail; t=1771364429; bh=5Uwy6bs1Cu3Ac5nEuDpfkKyR0IflWXmYqx0YiyUoMG8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=M7VU6osuYR6HrU3vBA9eg5GVCmLkn7ea8rhTEYrz9abHI5NTraXwc30RLt8WCXT+c PdyzAFlGLMwYfaio8MnsGdqumgJf/X7nsdQmtUd6h8+zR7H18kyNbq6DUk5eixaUWi +gY4X7iwjBw+p+8jBPQLR9wxXv1t4ga7cdf+ApS7E0ZZMqsThuJMijPMK9I5fIEMz7 d2FOsCJGKkQer58CCusZDisLhFbf4SdE8KMqAzteISVBp6Z8k+mcR6g6gb5tlAOQXr +oiFfSTscMxpOVnIsKqgx0L6dmmtW5Fjh6WjSXvy6EYVgmRQ6sUCtyFOjHTVCapCFc BQRXiuozzwXqA== From: Ross Cawston Date: Tue, 17 Feb 2026 13:39:53 -0800 Subject: [PATCH 5/5] accel/rocket: Use per-task interrupt mask and handle PPU completion interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260217-accel-rocket-clean-base-v1-5-d72354325a25@r-sc.ca> References: <20260217-accel-rocket-clean-base-v1-0-d72354325a25@r-sc.ca> In-Reply-To: <20260217-accel-rocket-clean-base-v1-0-d72354325a25@r-sc.ca> To: Tomeu Vizoso , Oded Gabbay , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ross Cawston X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771364416; l=2929; i=ross@r-sc.ca; s=20260217; h=from:subject:message-id; bh=HWs1IC84v/YwZQbKpNwoGA0gGWlv8oAPh64TkdQpIug=; b=0rgR3wqnVOIYyoNpDkvr/gy3tbo9wKUJ9qM52KuhTyctnPeFJa4yPynjJ/VXvSIOmrmk+l+sr v8eOz6MDQ5RBZbDHgb3VWeRKXUur3aLY6dY+d1SOOl+8LhM964SPt8k X-Developer-Key: i=ross@r-sc.ca; a=ed25519; pk=c50mfTDLKsgS2tlqXEZEvb/VGiLvxjsLOw5M50DxhtM= X-Envelope-From: ross@r-sc.ca The current driver hard-codes interrupt mask and clear to DPU_0 | DPU_1 and only checks DPU completion in the IRQ handler. This causes timeouts on PPU-only tasks and DPU=E2=86=92PPU pipelined jobs. Use the new per-task int_mask field to set INTERRUPT_MASK to the correct terminal block(s): - conv / standalone DPU =E2=86=92 DPU_0 | DPU_1 - PPU / DPU=E2=86=92PPU pipeline =E2=86=92 PPU_0 | PPU_1 Also: - clear all relevant interrupt bits (0x1ffff) instead of just DPU - accept PPU_0 / PPU_1 completions in the IRQ handler Fixes correct completion detection for non-convolutional and pipelined workloads. Signed-off-by: Ross Cawston --- drivers/accel/rocket/rocket_job.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/accel/rocket/rocket_job.c b/drivers/accel/rocket/rocke= t_job.c index 1dcc0c945f7f..ce54913baa46 100644 --- a/drivers/accel/rocket/rocket_job.c +++ b/drivers/accel/rocket/rocket_job.c @@ -162,8 +162,20 @@ static void rocket_job_hw_submit(struct rocket_core *c= ore, struct rocket_job *jo rocket_pc_writel(core, REGISTER_AMOUNTS, PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT((task->regcmd_count + 1) / 2 - 1)); =20 - rocket_pc_writel(core, INTERRUPT_MASK, PC_INTERRUPT_MASK_DPU_0 | PC_INTER= RUPT_MASK_DPU_1); - rocket_pc_writel(core, INTERRUPT_CLEAR, PC_INTERRUPT_CLEAR_DPU_0 | PC_INT= ERRUPT_CLEAR_DPU_1); + /* + * Enable interrupts for the last block in this task's pipeline. + * + * The int_mask field from userspace specifies which block completion + * signals that this task is done: + * - Conv/DPU tasks: DPU_0 | DPU_1 + * - PPU tasks (DPU=E2=86=92PPU pipeline): PPU_0 | PPU_1 + * + * Only enabling the terminal block's interrupt prevents the kernel + * from stopping the pipeline early (e.g. DPU fires before PPU has + * finished writing its output). + */ + rocket_pc_writel(core, INTERRUPT_MASK, task->int_mask); + rocket_pc_writel(core, INTERRUPT_CLEAR, 0x1ffff); =20 rocket_pc_writel(core, TASK_CON, PC_TASK_CON_RESERVED_0(1) | PC_TASK_CON_TASK_COUNT_CLEAR(1) | @@ -449,8 +461,17 @@ static irqreturn_t rocket_job_irq_handler(int irq, voi= d *data) WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR); WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR); =20 - if (!(raw_status & PC_INTERRUPT_RAW_STATUS_DPU_0 || - raw_status & PC_INTERRUPT_RAW_STATUS_DPU_1)) + /* + * Check for any job completion interrupt: DPU or PPU. + * + * Conv and standalone DPU jobs signal via DPU_0/DPU_1. + * PPU pooling jobs signal via PPU_0/PPU_1. + * We must recognize both to avoid PPU job timeouts. + */ + if (!(raw_status & (PC_INTERRUPT_RAW_STATUS_DPU_0 | + PC_INTERRUPT_RAW_STATUS_DPU_1 | + PC_INTERRUPT_RAW_STATUS_PPU_0 | + PC_INTERRUPT_RAW_STATUS_PPU_1))) return IRQ_NONE; =20 rocket_pc_writel(core, INTERRUPT_MASK, 0x0); --=20 2.52.0