From nobody Sun Apr 5 13:04:39 2026 Received: from out-181.mta1.migadu.com (out-181.mta1.migadu.com [95.215.58.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A27522144D7 for ; Mon, 16 Feb 2026 23:38:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771285138; cv=none; b=oucIJ9jM/I0iruy2O9IB3m9bVbF3qUNMdX/tVnG0B2dU9sA0nL0Hq+FaeN5qZ/bfqHlsxmx2mHKFFLyJ4WSu93xcZAIOIS9HMXaTxQaEhaM6jKyZaMwkzv0M9CQzb+Ponv85MLYMvAhe1wDdYL8NxhhdQ6illVezbaVB6HrZSZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771285138; c=relaxed/simple; bh=UZYObOCo+4Uc/zazdoJD2WY1/0RSF+UuBPsgZca65/I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G6bNO7znpeTtQYobIFHmhMWx6xMzcfCc74DBGfit2xUIyNkEYPnFp0wOTgbbg+yFkqyFjDnK0f6+ZJaSZVAHZymCqv/3gbVwyuVhlp9qfuvNn9HdFEmewKsvNHlDTKQpVVQnDpQxUolkU77GMjqU84NDsd8x8xzemCYkENGWEeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=jz+rBCHv; arc=none smtp.client-ip=95.215.58.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="jz+rBCHv" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1771285135; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ILY7v2SmIZw9ZvvKst2oBdkcdWOxzEcSMApNN4USfk8=; b=jz+rBCHvNqWCv6GTD/feeOn+hQoHdzYTTnU0S6uAVNKOj89vp+P1Lgfb8LsgCnvVPbFF6Y kqcMozxcdL6o6n1dQDY6iZNfIR9FIUnHBnR78jGY87lXxky93mQazv2xeIx7Sb0uuC2CCc MPBbPRiKLh7umSVaMre6w4TigoHZWX2f5ZsNHDDqpxHI5NRI9xxoySwnFyNuKC0wb8bO2V AGsu7Bj2I3kzca/a8i61qa4xUy+8jlFiCEPl9UX+fH8PCn0Z+dRrrNiaYcxQkaeSHbm1iv Mgk7LFGDgu4TsFdwIyH44Xgf+adrVqDQcU7WZ5hhsufQkrVKv0rbHx23h5PX3w== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Adam Skladowski Cc: linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Val Packett , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] clk: qcom: dispcc-sm6115: Add missing MDSS resets Date: Mon, 16 Feb 2026 20:25:21 -0300 Message-ID: <20260216233600.13098-5-val@packett.cool> In-Reply-To: <20260216233600.13098-2-val@packett.cool> References: <20260216233600.13098-2-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The MDSS resets were left undescribed, fix that. Fixes: 9b518788631c ("clk: qcom: Add display clock controller driver for SM= 6115") Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm6115.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6= 115.c index 8ae25d51db94..75bd57213079 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -22,6 +22,7 @@ #include "clk-regmap-divider.h" #include "common.h" #include "gdsc.h" +#include "reset.h" =20 enum { DT_BI_TCXO, @@ -511,6 +512,10 @@ static struct clk_branch disp_cc_sleep_clk =3D { }, }; =20 +static const struct qcom_reset_map disp_cc_sm6115_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x2000 }, +}; + static struct gdsc mdss_gdsc =3D { .gdscr =3D 0x3000, .pd =3D { @@ -561,6 +566,8 @@ static const struct qcom_cc_desc disp_cc_sm6115_desc = =3D { .config =3D &disp_cc_sm6115_regmap_config, .clks =3D disp_cc_sm6115_clocks, .num_clks =3D ARRAY_SIZE(disp_cc_sm6115_clocks), + .resets =3D disp_cc_sm6115_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_sm6115_resets), .gdscs =3D disp_cc_sm6115_gdscs, .num_gdscs =3D ARRAY_SIZE(disp_cc_sm6115_gdscs), }; --=20 2.52.0