From nobody Sun Apr 5 13:13:05 2026 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A61281EB5B for ; Mon, 16 Feb 2026 23:38:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771285105; cv=none; b=alPkS/Rq39nzxnI2UiBuEwES3toStkIFl7Bd9qsZdu1Qk1aICjCQvdWmoJ7Em5n2xaUzMhrbB5pXeAVGnqzTd8iW9C0twaFabCtRyaC55zro4KGdotAgpHhfOTDO7m+qH9Xn3ypYj5pKAkE5MKJ1GFFXfdr6Bc+l3hKJpe/hdhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771285105; c=relaxed/simple; bh=kCuopfLu7Oi0EzM4wixJtyFkRBVwm7HLABObJtpowC4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pS0IGhibttkjUMY4rdrOoSr1ThYHbOeihe3W2iCyO8QrXKZJELCEW+reuzJlkkvGh/V2IKCROF29xHvyU8Yq4vJI1rJUhP/40vj4AzG8dLjSfAse0J/iyvMCIV3qLhxxHJ0bdK5RnZeLAQknTYTntmNNfJ8UV2RIf+JdYSnjBvA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=Dk+62Vat; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="Dk+62Vat" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1771285102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NWnN6+c5xsBb3tOefcLzO1lu0M8RbBtdH+rnfm5Rppk=; b=Dk+62VatWm82DrmIg6ZI12X5VxYgb087vuPYvLrZSrcT5plDzZLXdtJJQi20LKPASPxzqi WdwmO0UWXPCzX7G8v08Lr05w/ha9vlA9lVAlDCeTyZDLSYMctyL5GMFO18ahJat6WjOAjp UkwoXxjSWcx/hjsjisTCTHj4vNGZFUMAPqZ4sRtjmHrWeRWmshmtaeCVYgrBOVlscAKfKJ sAs0IS1584FoeWW9rkCgrbUs6lmkmfL3AcshcMGSh6y+PsLtBc9iwN1v27lE10QzWkSoB1 kX+R11gbHb2fJyjtelxChxRmMDxcdqEBTtm5C3bzpHJIm+QHXrjauBuQoT0lUA== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adam Skladowski Cc: linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Val Packett , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets Date: Mon, 16 Feb 2026 20:25:19 -0300 Message-ID: <20260216233600.13098-3-val@packett.cool> In-Reply-To: <20260216233600.13098-2-val@packett.cool> References: <20260216233600.13098-2-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add the missing defines for MDSS resets. While here, align comment style with other SoCs. Fixes: 38557c6fc077 ("dt-bindings: clock: add QCOM SM6115 display clock bin= dings") Signed-off-by: Val Packett --- include/dt-bindings/clock/qcom,sm6115-dispcc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bi= ndings/clock/qcom,sm6115-dispcc.h index d1a6c45b5029..ab8d312ade37 100644 --- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H =20 -/* DISP_CC clocks */ +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_MAIN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -30,7 +30,10 @@ #define DISP_CC_SLEEP_CLK 20 #define DISP_CC_SLEEP_CLK_SRC 21 =20 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 =20 #endif --=20 2.52.0