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charset="utf-8" The existing IBS_{FETCH|OP}_CTL MSRs combine control and status bits which leads to RMW race between HW and SW: HW SW ------------------------ ------------------------------ config =3D rdmsr(IBS_OP_CTL); config &=3D ~EN; Set IBS_OP_CTL[Val] to 1 trigger NMI wrmsr(IBS_OP_CTL, config); // Val is accidentally cleared Future hardware adds a control-only MSR, IBS_{FETCH|OP}_CTL2, which provides a second-level "disable" bit (Dis). IBS is now: Enabled: IBS_{FETCH|OP}_CTL[En] =3D 1 && IBS_{FETCH|OP}_CTL2[Dis] =3D 0 Disabled: IBS_{FETCH|OP}_CTL[En] =3D 0 || IBS_{FETCH|OP}_CTL2[Dis] =3D 1 The separate "Dis" bit lets software disable IBS without touching any status fields, eliminating the hardware/software race. Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 2e8fb0615226..b7f0aad9356c 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -86,9 +86,11 @@ struct cpu_perf_ibs { struct perf_ibs { struct pmu pmu; unsigned int msr; + unsigned int msr2; u64 config_mask; u64 cnt_mask; u64 enable_mask; + u64 disable_mask; u64 valid_mask; u16 min_period; u64 max_period; @@ -292,6 +294,8 @@ static int perf_ibs_init(struct perf_event *event) return -ENOENT; =20 config =3D event->attr.config; + hwc->extra_reg.config =3D 0; + hwc->extra_reg.reg =3D 0; =20 if (event->pmu !=3D &perf_ibs->pmu) return -ENOENT; @@ -319,6 +323,11 @@ static int perf_ibs_init(struct perf_event *event) if (perf_allow_kernel()) hwc->flags |=3D PERF_X86_EVENT_UNPRIVILEGED; =20 + if (ibs_caps & IBS_CAPS_DIS) { + hwc->extra_reg.config &=3D ~perf_ibs->disable_mask; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + if (hwc->sample_period) { if (config & perf_ibs->cnt_mask) /* raw max_cnt may not be set */ @@ -448,6 +457,9 @@ static inline void perf_ibs_enable_event(struct perf_ib= s *perf_ibs, wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); =20 wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); + + if (hwc->extra_reg.reg) + wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); } =20 /* @@ -460,6 +472,11 @@ static inline void perf_ibs_enable_event(struct perf_i= bs *perf_ibs, static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, struct hw_perf_event *hwc, u64 config) { + if (ibs_caps & IBS_CAPS_DIS) { + wrmsrq(hwc->extra_reg.reg, perf_ibs->disable_mask); + return; + } + config &=3D ~perf_ibs->cnt_mask; if (boot_cpu_data.x86 =3D=3D 0x10) wrmsrq(hwc->config_base, config); @@ -812,6 +829,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .check_period =3D perf_ibs_check_period, }, .msr =3D MSR_AMD64_IBSFETCHCTL, + .msr2 =3D MSR_AMD64_IBSFETCHCTL2, .config_mask =3D IBS_FETCH_MAX_CNT | IBS_FETCH_RAND_EN, .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, @@ -837,6 +855,7 @@ static struct perf_ibs perf_ibs_op =3D { .check_period =3D perf_ibs_check_period, }, .msr =3D MSR_AMD64_IBSOPCTL, + .msr2 =3D MSR_AMD64_IBSOPCTL2, .config_mask =3D IBS_OP_MAX_CNT, .cnt_mask =3D IBS_OP_MAX_CNT | IBS_OP_CUR_CNT | IBS_OP_CUR_CNT_RAND, @@ -1394,6 +1413,9 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_= ibs, struct pt_regs *iregs) =20 out: if (!throttle) { + if (ibs_caps & IBS_CAPS_DIS) + wrmsrq(hwc->extra_reg.reg, perf_ibs->disable_mask); + if (perf_ibs =3D=3D &perf_ibs_op) { if (ibs_caps & IBS_CAPS_OPCNTEXT) { new_config =3D period & IBS_OP_MAX_CNT_EXT_MASK; @@ -1465,6 +1487,9 @@ static __init int perf_ibs_fetch_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_fetch.config_mask |=3D IBS_FETCH_L3MISSONLY; =20 + if (ibs_caps & IBS_CAPS_DIS) + perf_ibs_fetch.disable_mask =3D IBS_FETCH_2_DIS; + perf_ibs_fetch.pmu.attr_groups =3D fetch_attr_groups; perf_ibs_fetch.pmu.attr_update =3D fetch_attr_update; =20 @@ -1486,6 +1511,9 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_op.config_mask |=3D IBS_OP_L3MISSONLY; =20 + if (ibs_caps & IBS_CAPS_DIS) + perf_ibs_op.disable_mask =3D IBS_OP_2_DIS; + perf_ibs_op.pmu.attr_groups =3D op_attr_groups; perf_ibs_op.pmu.attr_update =3D op_attr_update; =20 @@ -1732,6 +1760,23 @@ static void clear_APIC_ibs(void) static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) { setup_APIC_ibs(); + + if (ibs_caps & IBS_CAPS_DIS) { + /* + * IBS enable sequence: + * CTL[En] =3D 1; + * CTL2[Dis] =3D 0; + * + * IBS disable sequence: + * CTL2[Dis] =3D 1; + * + * Set CTL2[Dis] when CPU comes up. This is needed to make + * enable sequence effective. + */ + wrmsrq(MSR_AMD64_IBSFETCHCTL2, IBS_FETCH_2_DIS); + wrmsrq(MSR_AMD64_IBSOPCTL2, IBS_OP_2_DIS); + } + return 0; } =20 --=20 2.43.0