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charset="utf-8" Load latency filter threshold is encoded in config1[11:0]. Define a mask for it instead of hardcoded 0xFFF. Unlike "config" fields whose layout maps to PERF_{FETCH|OP}_CTL MSR, layout of "config1" is custom defined so a new set of macros are needed for "config1" fields. Signed-off-by: Ravi Bangoria Reviewed-by: Dapeng Mi --- arch/x86/events/amd/ibs.c | 11 +++++++---- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 32e6456cb5e5..2e8fb0615226 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -32,6 +32,9 @@ static u32 ibs_caps; /* attr.config2 */ #define IBS_SW_FILTER_MASK 1 =20 +/* attr.config1 */ +#define IBS_OP_CONFIG1_LDLAT_MASK (0xFFFULL << 0) + /* * IBS states: * @@ -274,7 +277,7 @@ static bool perf_ibs_ldlat_event(struct perf_ibs *perf_= ibs, { return perf_ibs =3D=3D &perf_ibs_op && (ibs_caps & IBS_CAPS_OPLDLAT) && - (event->attr.config1 & 0xFFF); + (event->attr.config1 & IBS_OP_CONFIG1_LDLAT_MASK); } =20 static int perf_ibs_init(struct perf_event *event) @@ -352,13 +355,13 @@ static int perf_ibs_init(struct perf_event *event) } =20 if (perf_ibs_ldlat_event(perf_ibs, event)) { - u64 ldlat =3D event->attr.config1 & 0xFFF; + u64 ldlat =3D event->attr.config1 & IBS_OP_CONFIG1_LDLAT_MASK; =20 if (ldlat < 128 || ldlat > 2048) return -EINVAL; ldlat >>=3D 7; =20 - config |=3D (ldlat - 1) << 59; + config |=3D (ldlat - 1) << IBS_OP_LDLAT_THRSH_SHIFT; =20 config |=3D IBS_OP_LDLAT_EN; if (cpu_feature_enabled(X86_FEATURE_ZEN5)) @@ -1305,7 +1308,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_= ibs, struct pt_regs *iregs) * within [128, 2048] range. */ if (!op_data3.ld_op || !op_data3.dc_miss || - op_data3.dc_miss_lat <=3D (event->attr.config1 & 0xFFF)) { + op_data3.dc_miss_lat <=3D (event->attr.config1 & IBS_OP_CONFIG1_LDLA= T_MASK)) { throttle =3D perf_event_account_interrupt(event); goto out; } diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index ff5acb8b199b..67ecb989408e 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -671,6 +671,7 @@ struct arch_pebs_cntr_header { */ #define IBS_OP_LDLAT_EN (1ULL<<63) #define IBS_OP_LDLAT_THRSH (0xFULL<<59) +#define IBS_OP_LDLAT_THRSH_SHIFT (59) #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) #define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) --=20 2.43.0 From nobody Fri Apr 3 01:31:23 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010032.outbound.protection.outlook.com [52.101.56.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 989812BE64F; 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charset="utf-8" IBS on upcoming microarch introduced two new control MSRs and couple of new features. Define macros for them. New capabilities: o IBS_CAPS_DIS: Alternate Fetch and Op IBS disable bits o IBS_CAPS_FETCHLAT: Fetch Latency filter o IBS_CAPS_BIT63_FILTER: Virtual address bit 63 based filters for Fetch and Op o IBS_CAPS_STRMST_RMTSOCKET: Streaming store filter and indicator, remote socket indicator New control MSRs for above features: o MSR_AMD64_IBSFETCHCTL2 o MSR_AMD64_IBSOPCTL2 Also do cosmetic alignment changes. Signed-off-by: Ravi Bangoria Reviewed-by: Dapeng Mi --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/include/asm/perf_event.h | 56 ++++++++++++++++++++----------- 2 files changed, 38 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 6d1b69ea01c2..2313623eb0d0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -698,6 +698,8 @@ #define MSR_AMD64_IBSBRTARGET 0xc001103b #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c #define MSR_AMD64_IBSOPDATA4 0xc001103d +#define MSR_AMD64_IBSOPCTL2 0xc001103e +#define MSR_AMD64_IBSFETCHCTL2 0xc001103f #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 67ecb989408e..752cb319d5ea 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -643,6 +643,10 @@ struct arch_pebs_cntr_header { #define IBS_CAPS_OPDATA4 (1U<<10) #define IBS_CAPS_ZEN4 (1U<<11) #define IBS_CAPS_OPLDLAT (1U<<12) +#define IBS_CAPS_DIS (1U<<13) +#define IBS_CAPS_FETCHLAT (1U<<14) +#define IBS_CAPS_BIT63_FILTER (1U<<15) +#define IBS_CAPS_STRMST_RMTSOCKET (1U<<16) #define IBS_CAPS_OPDTLBPGSIZE (1U<<19) =20 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ @@ -657,32 +661,44 @@ struct arch_pebs_cntr_header { #define IBSCTL_LVT_OFFSET_MASK 0x0F =20 /* IBS fetch bits/masks */ -#define IBS_FETCH_L3MISSONLY (1ULL<<59) -#define IBS_FETCH_RAND_EN (1ULL<<57) -#define IBS_FETCH_VAL (1ULL<<49) -#define IBS_FETCH_ENABLE (1ULL<<48) -#define IBS_FETCH_CNT 0xFFFF0000ULL -#define IBS_FETCH_MAX_CNT 0x0000FFFFULL +#define IBS_FETCH_L3MISSONLY (1ULL << 59) +#define IBS_FETCH_RAND_EN (1ULL << 57) +#define IBS_FETCH_VAL (1ULL << 49) +#define IBS_FETCH_ENABLE (1ULL << 48) +#define IBS_FETCH_CNT 0xFFFF0000ULL +#define IBS_FETCH_MAX_CNT 0x0000FFFFULL + +#define IBS_FETCH_2_DIS (1ULL << 0) +#define IBS_FETCH_2_FETCHLAT_FILTER (0xFULL << 1) +#define IBS_FETCH_2_FETCHLAT_FILTER_SHIFT (1) +#define IBS_FETCH_2_EXCL_RIP_63_EQ_1 (1ULL << 5) +#define IBS_FETCH_2_EXCL_RIP_63_EQ_0 (1ULL << 6) =20 /* * IBS op bits/masks * The lower 7 bits of the current count are random bits * preloaded by hardware and ignored in software */ -#define IBS_OP_LDLAT_EN (1ULL<<63) -#define IBS_OP_LDLAT_THRSH (0xFULL<<59) -#define IBS_OP_LDLAT_THRSH_SHIFT (59) -#define IBS_OP_CUR_CNT (0xFFF80ULL<<32) -#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) -#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) -#define IBS_OP_CNT_CTL (1ULL<<19) -#define IBS_OP_VAL (1ULL<<18) -#define IBS_OP_ENABLE (1ULL<<17) -#define IBS_OP_L3MISSONLY (1ULL<<16) -#define IBS_OP_MAX_CNT 0x0000FFFFULL -#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ -#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */ -#define IBS_RIP_INVALID (1ULL<<38) +#define IBS_OP_LDLAT_EN (1ULL << 63) +#define IBS_OP_LDLAT_THRSH (0xFULL << 59) +#define IBS_OP_LDLAT_THRSH_SHIFT (59) +#define IBS_OP_CUR_CNT (0xFFF80ULL << 32) +#define IBS_OP_CUR_CNT_RAND (0x0007FULL << 32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL << 52) +#define IBS_OP_CNT_CTL (1ULL << 19) +#define IBS_OP_VAL (1ULL << 18) +#define IBS_OP_ENABLE (1ULL << 17) +#define IBS_OP_L3MISSONLY (1ULL << 16) +#define IBS_OP_MAX_CNT 0x0000FFFFULL +#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask = */ +#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 bi= ts */ +#define IBS_RIP_INVALID (1ULL << 38) + +#define IBS_OP_2_DIS (1ULL << 0) +#define IBS_OP_2_EXCL_RIP_63_EQ_0 (1ULL << 1) +#define IBS_OP_2_EXCL_RIP_63_EQ_1 (1ULL << 2) +#define IBS_OP_2_STRM_ST_FILTER (1ULL << 3) +#define IBS_OP_2_STRM_ST_FILTER_SHIFT (3) =20 #ifdef CONFIG_X86_LOCAL_APIC extern u32 get_ibs_caps(void); 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charset="utf-8" The existing IBS_{FETCH|OP}_CTL MSRs combine control and status bits which leads to RMW race between HW and SW: HW SW ------------------------ ------------------------------ config =3D rdmsr(IBS_OP_CTL); config &=3D ~EN; Set IBS_OP_CTL[Val] to 1 trigger NMI wrmsr(IBS_OP_CTL, config); // Val is accidentally cleared Future hardware adds a control-only MSR, IBS_{FETCH|OP}_CTL2, which provides a second-level "disable" bit (Dis). IBS is now: Enabled: IBS_{FETCH|OP}_CTL[En] =3D 1 && IBS_{FETCH|OP}_CTL2[Dis] =3D 0 Disabled: IBS_{FETCH|OP}_CTL[En] =3D 0 || IBS_{FETCH|OP}_CTL2[Dis] =3D 1 The separate "Dis" bit lets software disable IBS without touching any status fields, eliminating the hardware/software race. Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 2e8fb0615226..b7f0aad9356c 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -86,9 +86,11 @@ struct cpu_perf_ibs { struct perf_ibs { struct pmu pmu; unsigned int msr; + unsigned int msr2; u64 config_mask; u64 cnt_mask; u64 enable_mask; + u64 disable_mask; u64 valid_mask; u16 min_period; u64 max_period; @@ -292,6 +294,8 @@ static int perf_ibs_init(struct perf_event *event) return -ENOENT; =20 config =3D event->attr.config; + hwc->extra_reg.config =3D 0; + hwc->extra_reg.reg =3D 0; =20 if (event->pmu !=3D &perf_ibs->pmu) return -ENOENT; @@ -319,6 +323,11 @@ static int perf_ibs_init(struct perf_event *event) if (perf_allow_kernel()) hwc->flags |=3D PERF_X86_EVENT_UNPRIVILEGED; =20 + if (ibs_caps & IBS_CAPS_DIS) { + hwc->extra_reg.config &=3D ~perf_ibs->disable_mask; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + if (hwc->sample_period) { if (config & perf_ibs->cnt_mask) /* raw max_cnt may not be set */ @@ -448,6 +457,9 @@ static inline void perf_ibs_enable_event(struct perf_ib= s *perf_ibs, wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); =20 wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); + + if (hwc->extra_reg.reg) + wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); } =20 /* @@ -460,6 +472,11 @@ static inline void perf_ibs_enable_event(struct perf_i= bs *perf_ibs, static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, struct hw_perf_event *hwc, u64 config) { + if (ibs_caps & IBS_CAPS_DIS) { + wrmsrq(hwc->extra_reg.reg, perf_ibs->disable_mask); + return; + } + config &=3D ~perf_ibs->cnt_mask; if (boot_cpu_data.x86 =3D=3D 0x10) wrmsrq(hwc->config_base, config); @@ -812,6 +829,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .check_period =3D perf_ibs_check_period, }, .msr =3D MSR_AMD64_IBSFETCHCTL, + .msr2 =3D MSR_AMD64_IBSFETCHCTL2, .config_mask =3D IBS_FETCH_MAX_CNT | IBS_FETCH_RAND_EN, .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, @@ -837,6 +855,7 @@ static struct perf_ibs perf_ibs_op =3D { .check_period =3D perf_ibs_check_period, }, .msr =3D MSR_AMD64_IBSOPCTL, + .msr2 =3D MSR_AMD64_IBSOPCTL2, .config_mask =3D IBS_OP_MAX_CNT, .cnt_mask =3D IBS_OP_MAX_CNT | IBS_OP_CUR_CNT | IBS_OP_CUR_CNT_RAND, @@ -1394,6 +1413,9 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_= ibs, struct pt_regs *iregs) =20 out: if (!throttle) { + if (ibs_caps & IBS_CAPS_DIS) + wrmsrq(hwc->extra_reg.reg, perf_ibs->disable_mask); + if (perf_ibs =3D=3D &perf_ibs_op) { if (ibs_caps & IBS_CAPS_OPCNTEXT) { new_config =3D period & IBS_OP_MAX_CNT_EXT_MASK; @@ -1465,6 +1487,9 @@ static __init int perf_ibs_fetch_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_fetch.config_mask |=3D IBS_FETCH_L3MISSONLY; =20 + if (ibs_caps & IBS_CAPS_DIS) + perf_ibs_fetch.disable_mask =3D IBS_FETCH_2_DIS; + perf_ibs_fetch.pmu.attr_groups =3D fetch_attr_groups; perf_ibs_fetch.pmu.attr_update =3D fetch_attr_update; =20 @@ -1486,6 +1511,9 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_op.config_mask |=3D IBS_OP_L3MISSONLY; =20 + if (ibs_caps & IBS_CAPS_DIS) + perf_ibs_op.disable_mask =3D IBS_OP_2_DIS; + perf_ibs_op.pmu.attr_groups =3D op_attr_groups; perf_ibs_op.pmu.attr_update =3D op_attr_update; =20 @@ -1732,6 +1760,23 @@ static void clear_APIC_ibs(void) static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) { setup_APIC_ibs(); + + if (ibs_caps & IBS_CAPS_DIS) { + /* + * IBS enable sequence: + * CTL[En] =3D 1; + * CTL2[Dis] =3D 0; + * + * IBS disable sequence: + * CTL2[Dis] =3D 1; + * + * Set CTL2[Dis] when CPU comes up. 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charset="utf-8" IBS Fetch on future hardware adds fetch latency filtering which generates interrupt only when FetchLat value exceeds a programmable threshold. Hardware allows threshold in 128-cycle increment (i.e. 128, 256, 384 etc.) from 128 to 1920 cycles. Like the existing IBS filters, samples that fail the latency test are dropped and IBS restarts internally. Since hardware supports threshold in multiple of 128, add a software filter on top to support latency threshold with the granularity of 1 cycle in between [128-1920]. Example: # perf record -e ibs_fetch/fetchlat=3D128/ -c 10000 -a -- sleep 5 Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 66 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index b7f0aad9356c..cb3ae4e4744c 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -35,6 +35,8 @@ static u32 ibs_caps; /* attr.config1 */ #define IBS_OP_CONFIG1_LDLAT_MASK (0xFFFULL << 0) =20 +#define IBS_FETCH_CONFIG1_FETCHLAT_MASK (0x7FFULL << 0) + /* * IBS states: * @@ -282,6 +284,14 @@ static bool perf_ibs_ldlat_event(struct perf_ibs *perf= _ibs, (event->attr.config1 & IBS_OP_CONFIG1_LDLAT_MASK); } =20 +static bool perf_ibs_fetch_lat_event(struct perf_ibs *perf_ibs, + struct perf_event *event) +{ + return perf_ibs =3D=3D &perf_ibs_fetch && + (ibs_caps & IBS_CAPS_FETCHLAT) && + (event->attr.config1 & IBS_FETCH_CONFIG1_FETCHLAT_MASK); +} + static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; @@ -377,6 +387,17 @@ static int perf_ibs_init(struct perf_event *event) config |=3D IBS_OP_L3MISSONLY; } =20 + if (perf_ibs_fetch_lat_event(perf_ibs, event)) { + u64 fetchlat =3D event->attr.config1 & IBS_FETCH_CONFIG1_FETCHLAT_MASK; + + if (fetchlat < 128 || fetchlat > 1920) + return -EINVAL; + fetchlat >>=3D 7; + + hwc->extra_reg.reg =3D perf_ibs->msr2; + hwc->extra_reg.config |=3D fetchlat << IBS_FETCH_2_FETCHLAT_FILTER_SHIFT; + } + /* * If we modify hwc->sample_period, we also need to update * hwc->last_period and hwc->period_left. @@ -665,6 +686,8 @@ PMU_EVENT_ATTR_STRING(ldlat, ibs_op_ldlat_format, "conf= ig1:0-11"); PMU_EVENT_ATTR_STRING(zen4_ibs_extensions, zen4_ibs_extensions, "1"); PMU_EVENT_ATTR_STRING(ldlat, ibs_op_ldlat_cap, "1"); PMU_EVENT_ATTR_STRING(dtlb_pgsize, ibs_op_dtlb_pgsize_cap, "1"); +PMU_EVENT_ATTR_STRING(fetchlat, ibs_fetch_lat_format, "config1:0-10"); +PMU_EVENT_ATTR_STRING(fetchlat, ibs_fetch_lat_cap, "1"); =20 static umode_t zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *att= r, int i) @@ -672,6 +695,12 @@ zen4_ibs_extensions_is_visible(struct kobject *kobj, s= truct attribute *attr, int return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0; } =20 +static umode_t +ibs_fetch_lat_is_visible(struct kobject *kobj, struct attribute *attr, int= i) +{ + return ibs_caps & IBS_CAPS_FETCHLAT ? attr->mode : 0; +} + static umode_t ibs_op_ldlat_is_visible(struct kobject *kobj, struct attribute *attr, int = i) { @@ -700,6 +729,16 @@ static struct attribute *zen4_ibs_extensions_attrs[] = =3D { NULL, }; =20 +static struct attribute *ibs_fetch_lat_format_attrs[] =3D { + &ibs_fetch_lat_format.attr.attr, + NULL, +}; + +static struct attribute *ibs_fetch_lat_cap_attrs[] =3D { + &ibs_fetch_lat_cap.attr.attr, + NULL, +}; + static struct attribute *ibs_op_ldlat_cap_attrs[] =3D { &ibs_op_ldlat_cap.attr.attr, NULL, @@ -727,6 +766,18 @@ static struct attribute_group group_zen4_ibs_extension= s =3D { .is_visible =3D zen4_ibs_extensions_is_visible, }; =20 +static struct attribute_group group_ibs_fetch_lat_cap =3D { + .name =3D "caps", + .attrs =3D ibs_fetch_lat_cap_attrs, + .is_visible =3D ibs_fetch_lat_is_visible, +}; + +static struct attribute_group group_ibs_fetch_lat_format =3D { + .name =3D "format", + .attrs =3D ibs_fetch_lat_format_attrs, + .is_visible =3D ibs_fetch_lat_is_visible, +}; + static struct attribute_group group_ibs_op_ldlat_cap =3D { .name =3D "caps", .attrs =3D ibs_op_ldlat_cap_attrs, @@ -748,6 +799,8 @@ static const struct attribute_group *fetch_attr_groups[= ] =3D { static const struct attribute_group *fetch_attr_update[] =3D { &group_fetch_l3missonly, &group_zen4_ibs_extensions, + &group_ibs_fetch_lat_cap, + &group_ibs_fetch_lat_format, NULL, }; =20 @@ -1191,7 +1244,8 @@ static int perf_ibs_get_offset_max(struct perf_ibs *p= erf_ibs, { if (event->attr.sample_type & PERF_SAMPLE_RAW || perf_ibs_is_mem_sample_type(perf_ibs, event) || - perf_ibs_ldlat_event(perf_ibs, event)) + perf_ibs_ldlat_event(perf_ibs, event) || + perf_ibs_fetch_lat_event(perf_ibs, event)) return perf_ibs->offset_max; else if (check_rip) return 3; @@ -1333,6 +1387,16 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf= _ibs, struct pt_regs *iregs) } } =20 + if (perf_ibs_fetch_lat_event(perf_ibs, event)) { + union ibs_fetch_ctl fetch_ctl; + + fetch_ctl.val =3D ibs_data.regs[ibs_fetch_msr_idx(MSR_AMD64_IBSFETCHCTL)= ]; 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charset="utf-8" IBS on future hardware adds the ability to filter IBS events by examining RIP bit 63. Because Linux kernel addresses always have bit 63 set while user-space addresses never do, this capability can be used as a privilege filter. So far, IBS supports privilege filtering in software (swfilt=3D1), where samples are dropped in the NMI handler. The RIP bit63 hardware filter enables IBS to be usable by unprivileged users without passing swfilt flag. So, swfilt flag will silently be ignored when the hardware filtering capability is present. Example (non-root user): $ perf record -e ibs_op//u -- Signed-off-by: Ravi Bangoria Reported-by: Ian Rogers Reviewed-by: Ian Rogers --- arch/x86/events/amd/ibs.c | 46 ++++++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index cb3ae4e4744c..13ecc8d92b23 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -321,11 +321,6 @@ static int perf_ibs_init(struct perf_event *event) event->attr.exclude_idle) return -EINVAL; =20 - if (!(event->attr.config2 & IBS_SW_FILTER_MASK) && - (event->attr.exclude_kernel || event->attr.exclude_user || - event->attr.exclude_hv)) - return -EINVAL; - ret =3D validate_group(event); if (ret) return ret; @@ -338,6 +333,32 @@ static int perf_ibs_init(struct perf_event *event) hwc->extra_reg.reg =3D perf_ibs->msr2; } =20 + if (ibs_caps & IBS_CAPS_BIT63_FILTER) { + if (perf_ibs =3D=3D &perf_ibs_fetch) { + if (event->attr.exclude_kernel) { + hwc->extra_reg.config |=3D IBS_FETCH_2_EXCL_RIP_63_EQ_1; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + if (event->attr.exclude_user) { + hwc->extra_reg.config |=3D IBS_FETCH_2_EXCL_RIP_63_EQ_0; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + } else { + if (event->attr.exclude_kernel) { + hwc->extra_reg.config |=3D IBS_OP_2_EXCL_RIP_63_EQ_1; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + if (event->attr.exclude_user) { + hwc->extra_reg.config |=3D IBS_OP_2_EXCL_RIP_63_EQ_0; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + } + } else if (!(event->attr.config2 & IBS_SW_FILTER_MASK) && + (event->attr.exclude_kernel || event->attr.exclude_user || + event->attr.exclude_hv)) { + return -EINVAL; + } + if (hwc->sample_period) { if (config & perf_ibs->cnt_mask) /* raw max_cnt may not be set */ @@ -1280,7 +1301,7 @@ static bool perf_ibs_is_kernel_br_target(struct perf_= event *event, op_data.op_brn_ret && kernel_ip(br_target)); } =20 -static bool perf_ibs_swfilt_discard(struct perf_ibs *perf_ibs, struct perf= _event *event, +static bool perf_ibs_discard_sample(struct perf_ibs *perf_ibs, struct perf= _event *event, struct pt_regs *regs, struct perf_ibs_data *ibs_data, int br_target_idx) { @@ -1435,8 +1456,9 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_= ibs, struct pt_regs *iregs) regs.flags |=3D PERF_EFLAGS_EXACT; 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charset="utf-8" IBS OP on future hardware supports recording samples only for instructions that does streaming store. Like the existing IBS filters, samples pointing to instruction which does not cause streaming store are discarded and IBS restarts internally. Example: $ perf record -e ibs_op/strmst=3D1/ -- Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 51 ++++++++++++++++++++++++++++++++++ arch/x86/include/asm/amd/ibs.h | 3 +- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 13ecc8d92b23..0a8313ea6331 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -34,6 +34,8 @@ static u32 ibs_caps; =20 /* attr.config1 */ #define IBS_OP_CONFIG1_LDLAT_MASK (0xFFFULL << 0) +#define IBS_OP_CONFIG1_STRMST_MASK (1ULL << 12) +#define IBS_OP_CONFIG1_STRMST_SHIFT (12) =20 #define IBS_FETCH_CONFIG1_FETCHLAT_MASK (0x7FFULL << 0) =20 @@ -292,6 +294,14 @@ static bool perf_ibs_fetch_lat_event(struct perf_ibs *= perf_ibs, (event->attr.config1 & IBS_FETCH_CONFIG1_FETCHLAT_MASK); } =20 +static bool perf_ibs_strmst_event(struct perf_ibs *perf_ibs, + struct perf_event *event) +{ + return perf_ibs =3D=3D &perf_ibs_op && + (ibs_caps & IBS_CAPS_STRMST_RMTSOCKET) && + (event->attr.config1 & IBS_OP_CONFIG1_STRMST_MASK); +} + static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; @@ -419,6 +429,15 @@ static int perf_ibs_init(struct perf_event *event) hwc->extra_reg.config |=3D fetchlat << IBS_FETCH_2_FETCHLAT_FILTER_SHIFT; } =20 + if (perf_ibs_strmst_event(perf_ibs, event)) { + u64 strmst =3D event->attr.config1 & IBS_OP_CONFIG1_STRMST_MASK; + + strmst >>=3D IBS_OP_CONFIG1_STRMST_SHIFT; + + hwc->extra_reg.reg =3D perf_ibs->msr2; + hwc->extra_reg.config |=3D strmst << IBS_OP_2_STRM_ST_FILTER_SHIFT; + } + /* * If we modify hwc->sample_period, we also need to update * hwc->last_period and hwc->period_left. @@ -709,6 +728,8 @@ PMU_EVENT_ATTR_STRING(ldlat, ibs_op_ldlat_cap, "1"); PMU_EVENT_ATTR_STRING(dtlb_pgsize, ibs_op_dtlb_pgsize_cap, "1"); PMU_EVENT_ATTR_STRING(fetchlat, ibs_fetch_lat_format, "config1:0-10"); PMU_EVENT_ATTR_STRING(fetchlat, ibs_fetch_lat_cap, "1"); +PMU_EVENT_ATTR_STRING(strmst, ibs_op_strmst_format, "config1:12"); +PMU_EVENT_ATTR_STRING(strmst, ibs_op_strmst_cap, "1"); =20 static umode_t zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *att= r, int i) @@ -722,6 +743,12 @@ ibs_fetch_lat_is_visible(struct kobject *kobj, struct = attribute *attr, int i) return ibs_caps & IBS_CAPS_FETCHLAT ? attr->mode : 0; } =20 +static umode_t +ibs_op_strmst_is_visible(struct kobject *kobj, struct attribute *attr, int= i) +{ + return ibs_caps & IBS_CAPS_STRMST_RMTSOCKET ? attr->mode : 0; +} + static umode_t ibs_op_ldlat_is_visible(struct kobject *kobj, struct attribute *attr, int = i) { @@ -770,6 +797,11 @@ static struct attribute *ibs_op_dtlb_pgsize_cap_attrs[= ] =3D { NULL, }; =20 +static struct attribute *ibs_op_strmst_cap_attrs[] =3D { + &ibs_op_strmst_cap.attr.attr, + NULL, +}; + static struct attribute_group group_fetch_formats =3D { .name =3D "format", .attrs =3D fetch_attrs, @@ -811,6 +843,12 @@ static struct attribute_group group_ibs_op_dtlb_pgsize= _cap =3D { .is_visible =3D ibs_op_dtlb_pgsize_is_visible, }; =20 +static struct attribute_group group_ibs_op_strmst_cap =3D { + .name =3D "caps", + .attrs =3D ibs_op_strmst_cap_attrs, + .is_visible =3D ibs_op_strmst_is_visible, +}; + static const struct attribute_group *fetch_attr_groups[] =3D { &group_fetch_formats, &empty_caps_group, @@ -856,6 +894,11 @@ static struct attribute *ibs_op_ldlat_format_attrs[] = =3D { NULL, }; =20 +static struct attribute *ibs_op_strmst_format_attrs[] =3D { + &ibs_op_strmst_format.attr.attr, + NULL, +}; + static struct attribute_group group_cnt_ctl =3D { .name =3D "format", .attrs =3D cnt_ctl_attrs, @@ -880,6 +923,12 @@ static struct attribute_group group_ibs_op_ldlat_forma= t =3D { .is_visible =3D ibs_op_ldlat_is_visible, }; =20 +static struct attribute_group group_ibs_op_strmst_format =3D { + .name =3D "format", + .attrs =3D ibs_op_strmst_format_attrs, + .is_visible =3D ibs_op_strmst_is_visible, +}; + static const struct attribute_group *op_attr_update[] =3D { &group_cnt_ctl, &group_op_l3missonly, @@ -887,6 +936,8 @@ static const struct attribute_group *op_attr_update[] = =3D { &group_ibs_op_ldlat_cap, &group_ibs_op_ldlat_format, &group_ibs_op_dtlb_pgsize_cap, + &group_ibs_op_strmst_cap, + &group_ibs_op_strmst_format, NULL, }; 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charset="utf-8" IBS OP on future hardware can indicate data source from remote socket as well. Advertise this capability to userspace so that userspace tools can decode IBS data accordingly. Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 19 +++++++++++++++++++ arch/x86/include/asm/amd/ibs.h | 3 ++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 0a8313ea6331..eeb607b84dda 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -730,6 +730,7 @@ PMU_EVENT_ATTR_STRING(fetchlat, ibs_fetch_lat_format, "= config1:0-10"); PMU_EVENT_ATTR_STRING(fetchlat, ibs_fetch_lat_cap, "1"); PMU_EVENT_ATTR_STRING(strmst, ibs_op_strmst_format, "config1:12"); PMU_EVENT_ATTR_STRING(strmst, ibs_op_strmst_cap, "1"); +PMU_EVENT_ATTR_STRING(rmtsocket, ibs_op_rmtsocket_cap, "1"); =20 static umode_t zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *att= r, int i) @@ -749,6 +750,12 @@ ibs_op_strmst_is_visible(struct kobject *kobj, struct = attribute *attr, int i) return ibs_caps & IBS_CAPS_STRMST_RMTSOCKET ? attr->mode : 0; } =20 +static umode_t +ibs_op_rmtsocket_is_visible(struct kobject *kobj, struct attribute *attr, = int i) +{ + return ibs_caps & IBS_CAPS_STRMST_RMTSOCKET ? attr->mode : 0; +} + static umode_t ibs_op_ldlat_is_visible(struct kobject *kobj, struct attribute *attr, int = i) { @@ -802,6 +809,11 @@ static struct attribute *ibs_op_strmst_cap_attrs[] =3D= { NULL, }; =20 +static struct attribute *ibs_op_rmtsocket_cap_attrs[] =3D { + &ibs_op_rmtsocket_cap.attr.attr, + NULL, +}; + static struct attribute_group group_fetch_formats =3D { .name =3D "format", .attrs =3D fetch_attrs, @@ -849,6 +861,12 @@ static struct attribute_group group_ibs_op_strmst_cap = =3D { .is_visible =3D ibs_op_strmst_is_visible, }; =20 +static struct attribute_group group_ibs_op_rmtsocket_cap =3D { + .name =3D "caps", + .attrs =3D ibs_op_rmtsocket_cap_attrs, + .is_visible =3D ibs_op_rmtsocket_is_visible, +}; + static const struct attribute_group *fetch_attr_groups[] =3D { &group_fetch_formats, &empty_caps_group, @@ -938,6 +956,7 @@ static const struct attribute_group *op_attr_update[] = =3D { &group_ibs_op_dtlb_pgsize_cap, &group_ibs_op_strmst_cap, &group_ibs_op_strmst_format, + &group_ibs_op_rmtsocket_cap, NULL, }; =20 diff --git a/arch/x86/include/asm/amd/ibs.h b/arch/x86/include/asm/amd/ibs.h index 020916eb7b4e..4eac36c42db6 100644 --- a/arch/x86/include/asm/amd/ibs.h +++ b/arch/x86/include/asm/amd/ibs.h @@ -100,7 +100,8 @@ union ibs_op_data2 { cache_hit_st:1, /* 5: cache hit state */ data_src_hi:2, /* 6-7: data source high */ strm_st:1, /* 8: streaming store */ - reserved1:55; /* 9-63: reserved */ + rmt_socket:1, /* 9: remote socket */ + reserved1:54; /* 10-63: reserved */ }; }; =20 --=20 2.43.0