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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc769437bsm236867966b.61.2026.02.16.00.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 00:57:19 -0800 (PST) From: Luca Weiss Date: Mon, 16 Feb 2026 09:54:20 +0100 Subject: [PATCH v4 2/3] media: qcom: camss: Add SM6350 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260216-sm6350-camss-v4-2-b9df35f87edb@fairphone.com> References: <20260216-sm6350-camss-v4-0-b9df35f87edb@fairphone.com> In-Reply-To: <20260216-sm6350-camss-v4-0-b9df35f87edb@fairphone.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771232235; l=16255; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=yQZA7Muu+RPhM4ceHt5ok0QGV5J19GhHbbDuVsedxIo=; b=oRGfm1Vp8/k6T4Piqpo8ODPgt2Z9N+WXyBw16ZbZaaht4Mi47ggs6pa9Ul9M6ijJ1UYK5gDRP O1k+IaTsLfXA/WuNOm71nDCNRUZtQRKzC3k7BLBmZBHKF5x+UoTWfxN X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the necessary support for CAMSS on the SM6350 SoC. Reviewed-by: Bryan O'Donoghue Signed-off-by: Luca Weiss Reviewed-by: Vladimir Zapolskiy --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 125 ++++++++++ drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 261 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 389 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 415483274552..dac8d2ecf799 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -399,6 +399,126 @@ csiphy_lane_regs lane_regs_sm8250[] =3D { {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.2.3 2PH */ +static const struct +csiphy_lane_regs lane_regs_sm6350[] =3D { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005c, 0xc0, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0x0d, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c80, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c88, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a00, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025c, 0xc0, 0x00, CSIPHY_SKEW_CAL}, + {0x0260, 0x0d, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b00, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045c, 0xc0, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0x0d, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c00, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0c04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x065c, 0xc0, 0x00, CSIPHY_SKEW_CAL}, + {0x0660, 0x0d, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, +}; + /* 14nm 2PH v 2.0.1 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_qcm2290[] =3D { @@ -1011,6 +1131,7 @@ static bool csiphy_is_gen2(u32 version) switch (version) { case CAMSS_2290: case CAMSS_6150: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: @@ -1105,6 +1226,10 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_qcm2290[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); break; + case CAMSS_6350: + regs->lane_regs =3D &lane_regs_sm6350[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); + break; case CAMSS_7280: case CAMSS_8250: regs->lane_regs =3D &lane_regs_sm8250[0]; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 5baf0e3d4bc4..7dc937d018f6 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -343,6 +343,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_660: case CAMSS_2290: case CAMSS_6150: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8x96: case CAMSS_8250: @@ -2003,6 +2004,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) =20 switch (vfe->camss->res->version) { case CAMSS_6150: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 00b87fd9afbd..b53fb94ab54a 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1703,6 +1703,253 @@ static const struct resources_icc icc_res_sm6150[] = =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_sm6350[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy0-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy0-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy0", "csiphy0_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy1-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy1-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy1", "csiphy1_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy2-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy2-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy2", "csiphy2_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy3-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy3-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy3", "csiphy3_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + } +}; + +static const struct camss_subdev_resources csid_res_sm6350[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "vfe0_csid", "vfe0_cphy_rx", "vfe0" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "vfe1_csid", "vfe1_cphy_rx", "vfe1" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "vfe2_csid", "vfe2_cphy_rx", "vfe2" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite" }, + .interrupt =3D { "csid_lite" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + } +}; + +static const struct camss_subdev_resources vfe_res_sm6350[] =3D { + /* VFE0 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe0", + "vfe0_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe1", + "vfe1_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe2", + "vfe2_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe_lite", + "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite" }, + .interrupt =3D { "vfe_lite" }, + .vfe =3D { + .is_lite =3D true, + .line_num =3D 4, + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + +static const struct resources_icc icc_res_sm6350[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 0, + .icc_bw_tbl.peak =3D 300000, + }, + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_icp_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, +}; + static const struct camss_subdev_resources csiphy_res_8250[] =3D { /* CSIPHY0 */ { @@ -5233,6 +5480,19 @@ static const struct camss_resources sm6150_resources= =3D { .vfe_num =3D ARRAY_SIZE(vfe_res_sm6150), }; =20 +static const struct camss_resources sm6350_resources =3D { + .version =3D CAMSS_6350, + .pd_name =3D "top", + .csiphy_res =3D csiphy_res_sm6350, + .csid_res =3D csid_res_sm6350, + .vfe_res =3D vfe_res_sm6350, + .icc_res =3D icc_res_sm6350, + .icc_path_num =3D ARRAY_SIZE(icc_res_sm6350), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_sm6350), + .csid_num =3D ARRAY_SIZE(csid_res_sm6350), + .vfe_num =3D ARRAY_SIZE(vfe_res_sm6350), +}; + static const struct camss_resources sm8250_resources =3D { .version =3D CAMSS_8250, .pd_name =3D "top", @@ -5329,6 +5589,7 @@ static const struct of_device_id camss_dt_match[] =3D= { { .compatible =3D "qcom,sdm670-camss", .data =3D &sdm670_resources }, { .compatible =3D "qcom,sdm845-camss", .data =3D &sdm845_resources }, { .compatible =3D "qcom,sm6150-camss", .data =3D &sm6150_resources }, + { .compatible =3D "qcom,sm6350-camss", .data =3D &sm6350_resources }, { .compatible =3D "qcom,sm8250-camss", .data =3D &sm8250_resources }, { .compatible =3D "qcom,sm8550-camss", .data =3D &sm8550_resources }, { .compatible =3D "qcom,sm8650-camss", .data =3D &sm8650_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 6d048414c919..d323c105d185 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -81,6 +81,7 @@ enum camss_version { CAMSS_660, CAMSS_2290, CAMSS_6150, + CAMSS_6350, CAMSS_7280, CAMSS_8x16, CAMSS_8x39, --=20 2.53.0