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The reset flow also differs, so add the .assert_reset(), .deassert_reset(), and .idi_enable() callbacks to support it. Reviewed-by: Michael Riesch Signed-off-by: Frank Li --- Change in v3 - tune commit message according to Micheal's feedback. - Add Micheal's review tags - remove first comment about read before ndelay() because it use read value. - but second read() before ndelay() is dummy read(). change in v2 - move macro define to header - use new register access method - Keep check register exist to avoid print error message. keep slicence to access unexisting register may hide problem. --- drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 159 +++++++++++++++++++= +++- 1 file changed, 155 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/med= ia/platform/synopsys/dw-mipi-csi2rx.c index 536e5df2b4172256def2e2a35b362cfbddf712fa..036f9c7a1b68360dcb5744018d3= 85d4b1a15d506 100644 --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c @@ -34,6 +34,22 @@ #define DW_REG_EXIST BIT(31) #define DW_REG(x) (DW_REG_EXIST | (x)) =20 +#define DPHY_TEST_CTRL0_TEST_CLR BIT(0) + +#define IPI_VCID_VC(x) FIELD_PREP(GENMASK(1, 0), (x)) +#define IPI_VCID_VC_0_1(x) FIELD_PREP(GENMASK(3, 2), (x)) +#define IPI_VCID_VC_2 BIT(4) + +#define IPI_DATA_TYPE_DT(x) FIELD_PREP(GENMASK(5, 0), (x)) +#define IPI_DATA_TYPE_EMB_DATA_EN BIT(8) + +#define IPI_MODE_CONTROLLER BIT(1) +#define IPI_MODE_COLOR_MODE16 BIT(8) +#define IPI_MODE_CUT_THROUGH BIT(16) +#define IPI_MODE_ENABLE BIT(24) + +#define IPI_MEM_FLUSH_AUTO BIT(8) + enum dw_mipi_csi2rx_regs_index { DW_MIPI_CSI2RX_N_LANES, DW_MIPI_CSI2RX_RESETN, @@ -43,6 +59,16 @@ enum dw_mipi_csi2rx_regs_index { DW_MIPI_CSI2RX_MSK1, DW_MIPI_CSI2RX_MSK2, DW_MIPI_CSI2RX_CONTROL, + /* imx93 (v150) new register */ + DW_MIPI_CSI2RX_DPHY_RSTZ, + DW_MIPI_CSI2RX_PHY_TST_CTRL0, + DW_MIPI_CSI2RX_PHY_TST_CTRL1, + DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, + DW_MIPI_CSI2RX_IPI_DATATYPE, + DW_MIPI_CSI2RX_IPI_MEM_FLUSH, + DW_MIPI_CSI2RX_IPI_MODE, + DW_MIPI_CSI2RX_IPI_SOFTRSTN, + DW_MIPI_CSI2RX_IPI_VCID, =20 DW_MIPI_CSI2RX_MAX, }; @@ -53,8 +79,13 @@ enum { DW_MIPI_CSI2RX_PAD_MAX, }; =20 +struct dw_mipi_csi2rx_device; + struct dw_mipi_csi2rx_drvdata { const u32 *regs; + void (*dphy_assert_reset)(struct dw_mipi_csi2rx_device *csi2); + void (*dphy_deassert_reset)(struct dw_mipi_csi2rx_device *csi2); + void (*ipi_enable)(struct dw_mipi_csi2rx_device *csi2); }; =20 struct dw_mipi_csi2rx_format { @@ -100,6 +131,21 @@ static const struct dw_mipi_csi2rx_drvdata rk3568_drvd= ata =3D { .regs =3D rk3568_regs, }; =20 +static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] =3D { + [DW_MIPI_CSI2RX_N_LANES] =3D DW_REG(0x4), + [DW_MIPI_CSI2RX_RESETN] =3D DW_REG(0x8), + [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] =3D DW_REG(0x40), + [DW_MIPI_CSI2RX_DPHY_RSTZ] =3D DW_REG(0x44), + [DW_MIPI_CSI2RX_PHY_STATE] =3D DW_REG(0x48), + [DW_MIPI_CSI2RX_PHY_TST_CTRL0] =3D DW_REG(0x50), + [DW_MIPI_CSI2RX_PHY_TST_CTRL1] =3D DW_REG(0x54), + [DW_MIPI_CSI2RX_IPI_MODE] =3D DW_REG(0x80), + [DW_MIPI_CSI2RX_IPI_VCID] =3D DW_REG(0x84), + [DW_MIPI_CSI2RX_IPI_DATATYPE] =3D DW_REG(0x88), + [DW_MIPI_CSI2RX_IPI_MEM_FLUSH] =3D DW_REG(0x8c), + [DW_MIPI_CSI2RX_IPI_SOFTRSTN] =3D DW_REG(0xa0), +}; + static const struct v4l2_mbus_framefmt default_format =3D { .width =3D 3840, .height =3D 2160, @@ -320,14 +366,32 @@ static int dw_mipi_csi2rx_start(struct dw_mipi_csi2rx= _device *csi2) return -EINVAL; } =20 + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); + + if (csi2->drvdata->dphy_assert_reset) + csi2->drvdata->dphy_assert_reset(csi2); + control |=3D SW_DATATYPE_FS(0x00) | SW_DATATYPE_FE(0x01) | SW_DATATYPE_LS(0x02) | SW_DATATYPE_LE(0x03); =20 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_N_LANES, lanes - 1); - dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_CONTROL, control); + + if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_CONTROL)) + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_CONTROL, control); + + ret =3D phy_power_on(csi2->phy); + if (ret) + return ret; + + if (csi2->drvdata->dphy_deassert_reset) + csi2->drvdata->dphy_deassert_reset(csi2); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 1); =20 - return phy_power_on(csi2->phy); + if (csi2->drvdata->ipi_enable) + csi2->drvdata->ipi_enable(csi2); + + return 0; } =20 static void dw_mipi_csi2rx_stop(struct dw_mipi_csi2rx_device *csi2) @@ -335,8 +399,12 @@ static void dw_mipi_csi2rx_stop(struct dw_mipi_csi2rx_= device *csi2) phy_power_off(csi2->phy); =20 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); - dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK1, ~0); - dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK2, ~0); + + if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_MSK1)) + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK1, ~0); + + if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_MSK2)) + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK2, ~0); } =20 static const struct media_entity_operations dw_mipi_csi2rx_media_ops =3D { @@ -686,7 +754,90 @@ static void dw_mipi_csi2rx_unregister(struct dw_mipi_c= si2rx_device *csi2) v4l2_async_nf_cleanup(&csi2->notifier); } =20 +static void imx93_csi2rx_dphy_assert_reset(struct dw_mipi_csi2rx_device *c= si2) +{ + u32 val; + + /* Release Synopsys DPHY test codes from reset */ + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0); + + val =3D dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0); + val &=3D ~DPHY_TEST_CTRL0_TEST_CLR; + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val); + + val =3D dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0); + /* Wait for at least 15ns */ + ndelay(15); + val |=3D DPHY_TEST_CTRL0_TEST_CLR; + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val); +} + +static void imx93_csi2rx_dphy_deassert_reset(struct dw_mipi_csi2rx_device = *csi2) +{ + /* Release PHY from reset */ + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0x1); + /* + * ndelay() is not necessary have MMIO operation, need dummy read to + * ensure that the write operation above reaches its target. + */ + dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ); + ndelay(5); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0x1); + + dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ); + ndelay(5); +} + +static void imx93_csi2rx_dphy_ipi_enable(struct dw_mipi_csi2rx_device *csi= 2) +{ + int dt =3D csi2->formats->csi_dt; + u32 val; + + /* Do IPI soft reset */ + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_SOFTRSTN, 0x0); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_SOFTRSTN, 0x1); + + /* Select virtual channel and data type to be processed by IPI */ + val =3D IPI_DATA_TYPE_DT(dt); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_DATATYPE, val); + + /* Set virtual channel 0 as default */ + val =3D IPI_VCID_VC(0); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_VCID, val); + + /* + * Select IPI camera timing mode and allow the pixel stream + * to be non-continuous when pixel interface FIFO is empty + */ + val =3D dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_IPI_MODE); + val &=3D ~IPI_MODE_CONTROLLER; + val &=3D ~IPI_MODE_COLOR_MODE16; + val |=3D IPI_MODE_CUT_THROUGH; + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); + + /* Memory is automatically flushed at each Frame Start */ + val =3D IPI_MEM_FLUSH_AUTO; + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MEM_FLUSH, val); + + /* Enable IPI */ + val =3D dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_IPI_MODE); + val |=3D IPI_MODE_ENABLE; + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); +} + +static const struct dw_mipi_csi2rx_drvdata imx93_drvdata =3D { + .regs =3D imx93_regs, + .dphy_assert_reset =3D imx93_csi2rx_dphy_assert_reset, + .dphy_deassert_reset =3D imx93_csi2rx_dphy_deassert_reset, + .ipi_enable =3D imx93_csi2rx_dphy_ipi_enable, +}; + static const struct of_device_id dw_mipi_csi2rx_of_match[] =3D { + { + .compatible =3D "fsl,imx93-mipi-csi2", + .data =3D &imx93_drvdata, + }, { .compatible =3D "rockchip,rk3568-mipi-csi2", .data =3D &rk3568_drvdata, --=20 2.43.0