From nobody Fri Apr 3 05:04:22 2026 Received: from mail-yw1-f171.google.com (mail-yw1-f171.google.com [209.85.128.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E986248886 for ; Mon, 16 Feb 2026 22:16:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771280207; cv=none; b=N5G2gsDqMi30d6oVGJZSaq6r66rdzo2DaQdKZ6ZQcIIkbTLtIOlfaqrCV76hwkNKKlc6p9g2WCMykHfRsCTdgQkPdnMZ+Fg3copjS2qzuHUvT+72FPATro7Bq578CYp5+CVimX6bB4VCJgmJ3P56yE5VB+XZjH824GvWByGarq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771280207; c=relaxed/simple; bh=LRpRrPlFr3WG/Hf0VC5ZlSqIsbeePRU3gQpC8DT4EfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LWqgbl07/LL1kjaAmA9wHq4+Olig1df/ERnhMlaTYiDDTxYT5HmO0VSNgnNJryhUm/w0h+JmBjm9PUXSjmjNwVIS7ZFyeT4QPBCpcdpmsGBCSvkGCWvnudTB/n7vYYgfcy8xiyW1OTegijzfuGMTgrZouT4OTcMBOZ90OOWRI5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=oss.tenstorrent.com; spf=pass smtp.mailfrom=tenstorrent.com; dkim=pass (2048-bit key) header.d=tenstorrent.com header.i=@tenstorrent.com header.b=TjlR6okq; arc=none smtp.client-ip=209.85.128.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=oss.tenstorrent.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tenstorrent.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tenstorrent.com header.i=@tenstorrent.com header.b="TjlR6okq" Received: by mail-yw1-f171.google.com with SMTP id 00721157ae682-79456d5ebf9so32322597b3.2 for ; Mon, 16 Feb 2026 14:16:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tenstorrent.com; s=google; t=1771280204; x=1771885004; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Vr9AQ16LUCsHISAxFNb9nZcdT/t7sl0hcy6miHE+OBw=; b=TjlR6okqhMKZyI6HVG/2m87mLXaiQ37y0lDiTjz5H+8WhMxfKzTj4moU91DjkV8VW7 4s+bBJO6FSYuCM3wir1HqsbGFGxuj5X0hCWEsvx3WwT8bM940/p8CT2/RkDyk9saMV9/ TTdRpfemfC+Osnt4KefJDBgsMCXgzqV4N1VSaSXkqASG0QuZnred2OawW9h17yWTQgUz kSFbaiciLrzQN6eIvfvzTZ+f5A9tqIXV47ypz+XU05bGnMB7NHWpSS0LIuZYjnLU1U+q gr52D8GlVfa5ClNK9KPxEee23u7ABWKw/p1Vsq3h12mnCCZhcZQFcjWrcJ9alI1T8MoX iBWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771280204; x=1771885004; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Vr9AQ16LUCsHISAxFNb9nZcdT/t7sl0hcy6miHE+OBw=; b=kDOOo9ImcA33BY4C7or7Ky5MYwiO/Ux1/ZxcN6/JMRTBbaWYSOLul6fDNfgf/XEuN4 tAvkMohFhcPJQvSeEAn+r+c2v2InJ7h4mOmsc1WfZQbdVMwjc7c0FEGbhIABpezdyT4X 1BRVBCkXeWAPhDYvccSsep9jSWcTREFgY4edzfj4Luot2fRLvMXWtBi2IUixw8yJwFlN roqYkxybI6Uv7vUzPUjVMXiwUv8BYE0QSYO+n5VZDOr0X3ugy4w1NAQNGSVlieh2vMFX mJwKHaqY2juRq3y8vT214BPIkJZzeR7HaCv4xqHbkLJTRAxOGdpVeM2gCjWyKwcc++eH JAOg== X-Forwarded-Encrypted: i=1; AJvYcCXDkqWKkcHIuTasYahZfZtz1nw62Qf9cEAYqYlgD+6TYelVdYzmLNBf8uuWQPOZsfv8939h1ql9INBBrmM=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9jS+oA3O1519xUDpfeglnMq5KqwnxA5h5zUcN1VIGFDy0/p0E q+PEvNztTJVWIyHDEuoDdtDFfxf7U5U9TP28QgWxlahVSq+dcnPTu5xYyLYrQWiqQ+M= X-Gm-Gg: AZuq6aKyEgTnISz4z2TlrxalCPGVkdHjCoF9+uH0A8TgxconaCo7HX0q3+MGC61eLjS /ZI/Vj0WFYBYSvrHneladlkfcBD83BD7vH4+O+lwBDg+MXFF1iTwBaxm5qNAIsSuqLpL4xhupSH gaYoP4TN20MaYZohtAx2eD0rhD8MMLQ+FAFOIyL/ejJoW16sVZyIgJmoeGinITjPzfGOSOQjzgL ukNo2YRxkSRl2N98+nJky9ZbDichlJFXQKWHgrgKPMdKqU01Es75K1aQ9Qv62YoL/PzcICPs0F3 6yYWM7IEp8Pp4+BnesyFhVVZcC9EwPfOJCOIfjYUAO7+w7/l6NZlToB0Zw8VT8c4YXYW9wpGN22 UoVd7JMisooq9qJokfhmqN1GFXrMOdgHIUWrw12pSDwfDOO9wN9UCREQlw/3IzJeh5cJ4o2XPgT Hp59yKyoMKZhRkCgj7+tGdogb/ckVAt8rSTPVKWktZuEoWn0ItA9ZgWED5eSn9GuT7LebZuxCLv YniYL4xd3A= X-Received: by 2002:a05:690c:4884:b0:794:ef94:120d with SMTP id 00721157ae682-797ac5263d8mr72932517b3.24.1771280204562; Mon, 16 Feb 2026 14:16:44 -0800 (PST) Received: from [192.168.5.15] ([68.95.197.245]) by smtp.gmail.com with ESMTPSA id 00721157ae682-7966c1a8222sm106705757b3.23.2026.02.16.14.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Feb 2026 14:16:44 -0800 (PST) From: Anirudh Srinivasan Date: Mon, 16 Feb 2026 16:16:32 -0600 Subject: [PATCH v6 1/3] dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260216-atlantis-clocks-v6-1-cb46d6a59c73@oss.tenstorrent.com> References: <20260216-atlantis-clocks-v6-0-cb46d6a59c73@oss.tenstorrent.com> In-Reply-To: <20260216-atlantis-clocks-v6-0-cb46d6a59c73@oss.tenstorrent.com> To: Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Anirudh Srinivasan , Philipp Zabel Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, fustini@kernel.org, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com, bmasney@redhat.com X-Mailer: b4 0.14.3 Document bindings for Tenstorrent Atlantis PRCM that manages clocks and resets. This block is instantiated multiple times in the SoC. This commit documents the clocks from the RCPU PRCM block. Signed-off-by: Anirudh Srinivasan Reviewed-by: Krzysztof Kozlowski --- .../clock/tenstorrent,atlantis-prcm-rcpu.yaml | 54 +++++++++++ MAINTAINERS | 2 + .../clock/tenstorrent,atlantis-prcm-rcpu.h | 103 +++++++++++++++++= ++++ 3 files changed, 159 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/tenstorrent,atlantis-p= rcm-rcpu.yaml b/Documentation/devicetree/bindings/clock/tenstorrent,atlanti= s-prcm-rcpu.yaml new file mode 100644 index 000000000000..7fa16526efce --- /dev/null +++ b/Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcp= u.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/tenstorrent,atlantis-prcm-rcpu.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tenstorrent Atlantis PRCM (Power, Reset, Clock Management) Module + +maintainers: + - Anirudh Srinivasan + +description: + Multifunctional register block found in Tenstorrent Atlantis SoC whose m= ain + function is to control clocks and resets. This block is instantiated mul= tiple + times in the SoC, each block controls clock and resets for a different + subsystem. RCPU prcm serves low speed IO interfaces. + +properties: + compatible: + enum: + - tenstorrent,atlantis-prcm-rcpu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + description: + See for valid i= ndices. + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@a8000000 { + compatible =3D "tenstorrent,atlantis-prcm-rcpu"; + reg =3D <0xa8000000 0x10000>; + clocks =3D <&osc_24m>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index dc731d37c8fe..24cd2bbe1c78 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22534,8 +22534,10 @@ M: Joel Stanley L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/tenstorrent/linux.git +F: Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.= yaml F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml F: arch/riscv/boot/dts/tenstorrent/ +F: include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h =20 RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h b/i= nclude/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h new file mode 100644 index 000000000000..c1c875e016f8 --- /dev/null +++ b/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Tenstorrent Atlantis PRCM Clock and Reset Indices + * + * Copyright (c) 2026 Tenstorrent + */ + +#ifndef _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H +#define _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H + +/* + * RCPU Domain Clock IDs + */ +#define CLK_RCPU_PLL 0 +#define CLK_RCPU_ROOT 1 +#define CLK_RCPU_DIV2 2 +#define CLK_RCPU_DIV4 3 +#define CLK_RCPU_RTC 4 +#define CLK_SMNDMA0_ACLK 5 +#define CLK_SMNDMA1_ACLK 6 +#define CLK_WDT0_PCLK 7 +#define CLK_WDT1_PCLK 8 +#define CLK_TIMER_PCLK 9 +#define CLK_PVTC_PCLK 10 +#define CLK_PMU_PCLK 11 +#define CLK_MAILBOX_HCLK 12 +#define CLK_SEC_SPACC_HCLK 13 +#define CLK_SEC_OTP_HCLK 14 +#define CLK_TRNG_PCLK 15 +#define CLK_SEC_CRC_HCLK 16 +#define CLK_SMN_HCLK 17 +#define CLK_AHB0_HCLK 18 +#define CLK_SMN_PCLK 19 +#define CLK_SMN_CLK 20 +#define CLK_SCRATCHPAD_CLK 21 +#define CLK_RCPU_CORE_CLK 22 +#define CLK_RCPU_ROM_CLK 23 +#define CLK_OTP_LOAD_CLK 24 +#define CLK_NOC_PLL 25 +#define CLK_NOCC_CLK 26 +#define CLK_NOCC_DIV2 27 +#define CLK_NOCC_DIV4 28 +#define CLK_NOCC_RTC 29 +#define CLK_NOCC_CAN 30 +#define CLK_QSPI_SCLK 31 +#define CLK_QSPI_HCLK 32 +#define CLK_I2C0_PCLK 33 +#define CLK_I2C1_PCLK 34 +#define CLK_I2C2_PCLK 35 +#define CLK_I2C3_PCLK 36 +#define CLK_I2C4_PCLK 37 +#define CLK_UART0_PCLK 38 +#define CLK_UART1_PCLK 39 +#define CLK_UART2_PCLK 40 +#define CLK_UART3_PCLK 41 +#define CLK_UART4_PCLK 42 +#define CLK_SPI0_PCLK 43 +#define CLK_SPI1_PCLK 44 +#define CLK_SPI2_PCLK 45 +#define CLK_SPI3_PCLK 46 +#define CLK_GPIO_PCLK 47 +#define CLK_CAN0_HCLK 48 +#define CLK_CAN0_CLK 49 +#define CLK_CAN1_HCLK 50 +#define CLK_CAN1_CLK 51 +#define CLK_CAN0_TIMER_CLK 52 +#define CLK_CAN1_TIMER_CLK 53 + +/* RCPU domain reset */ +#define RST_SMNDMA0 0 +#define RST_SMNDMA1 1 +#define RST_WDT0 2 +#define RST_WDT1 3 +#define RST_TMR 4 +#define RST_PVTC 5 +#define RST_PMU 6 +#define RST_MAILBOX 7 +#define RST_SPACC 8 +#define RST_OTP 9 +#define RST_TRNG 10 +#define RST_CRC 11 +#define RST_QSPI 12 +#define RST_I2C0 13 +#define RST_I2C1 14 +#define RST_I2C2 15 +#define RST_I2C3 16 +#define RST_I2C4 17 +#define RST_UART0 18 +#define RST_UART1 19 +#define RST_UART2 20 +#define RST_UART3 21 +#define RST_UART4 22 +#define RST_SPI0 23 +#define RST_SPI1 24 +#define RST_SPI2 25 +#define RST_SPI3 26 +#define RST_GPIO 27 +#define RST_CAN0 28 +#define RST_CAN1 29 +#define RST_I2S0 30 +#define RST_I2S1 31 + +#endif /* _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H */ --=20 2.43.0