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Sun, 15 Feb 2026 05:56:24 -0800 (PST) From: Khalil X-Google-Original-From: Khalil To: broonie@kernel.org, hdegoede@kernel.org, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Khalil Laleh Subject: [RFC PATCH 2/2] spi: pxa2xx: Handle dynamic clock gating for GPIO chip select devices Date: Sun, 15 Feb 2026 14:55:24 +0100 Message-ID: <20260215135524.1171065-3-khalil@rentman.nl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260215135524.1171065-1-khalil@rentman.nl> References: <20260215135524.1171065-1-khalil@rentman.nl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To: broonie@kernel.org, hdegoede@kernel.org, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org On Intel LPSS SPI controllers (Cannon Lake and later), the cs_clk_stays_gated flag is set, meaning the SPI clock is dynamically gated based on the native chip select state. When using GPIO chip select (spi_is_csgpiod() returns true), the native CS register is never asserted through the normal path, so the SPI clock never runs and all reads return zeros. Fix this by handling GPIO chip select devices explicitly in cs_assert and cs_deassert: - cs_assert: Assert the native CS in the control register (to enable the clock domain) and force the clock gate on via LPSS_PRIV_CLOCK_GATE. - cs_deassert: Deassert the native CS and restore the clock gate to auto mode. The SPI framework handles the actual GPIO toggle; this code only manages the LPSS clock gating. SPI_CONTROLLER_GPIO_SS must be set on the controller (done by serial-multi-instantiate) so the framework calls both the GPIO toggle and this set_cs callback. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D221064 Link: https://bugs.launchpad.net/ubuntu/+source/alsa-driver/+bug/2131138 Link: https://github.com/thesofproject/linux/issues/5621 Signed-off-by: Khalil Laleh --- drivers/spi/spi-pxa2xx.c | 35 +++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -419,20 +419,43 @@ { struct driver_data *drv_data =3D spi_controller_get_devdata(spi->controller); + const struct lpss_config *config; if (drv_data->ssp_type =3D=3D CE4100_SSP) { pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); return; } - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, true); + if (is_lpss_ssp(drv_data)) { + config =3D lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* + * GPIO handles the actual chip select to the device. + * On LPSS controllers with dynamic clock gating, the + * SPI clock won't run unless the native CS state says + * "asserted" in the CS control register. Assert native + * CS in the register to enable the clock, and force + * the clock gate on. + */ + lpss_ssp_cs_control(spi, true); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON); + } + } else { + lpss_ssp_cs_control(spi, true); + } + } } static void cs_deassert(struct spi_device *spi) { struct driver_data *drv_data =3D spi_controller_get_devdata(spi->controller); + const struct lpss_config *config; unsigned long timeout; if (drv_data->ssp_type =3D=3D CE4100_SSP) @@ -444,8 +467,22 @@ !time_after(jiffies, timeout)) cpu_relax(); - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, false); + if (is_lpss_ssp(drv_data)) { + config =3D lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* Deassert native CS and restore clock gating */ + lpss_ssp_cs_control(spi, false); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF); + } + } else { + lpss_ssp_cs_control(spi, false); + } + } } static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)