From nobody Thu Apr 2 23:53:19 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86EBD52F88 for ; Sun, 15 Feb 2026 03:58:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771127892; cv=none; b=ZPD/KhYDcf/LIsZaGZJsW1kohT2XlKsCWduHxCUd4sGztHKBb8KbGp03N9+E6Tks1V5KvOha9sybGdq7dxvfsrZC+erf4xish0T6rjp3TqAaPwLTvirC/GJ/AZzTUOKBBRykHlC91uddfKWIirE7qv+DyXVAn8ypPE6Ah5AgAX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771127892; c=relaxed/simple; bh=jsM6rUIEAwjwmIUoIADEtW5CiHC9ZcogfvHijHZpuys=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=e2zQfyWtRJZxNdKulLV/9ZmCfSsdnOjPdZ1ewu3syo+26V5dlD4T/Rw/zXDOGwlgpE7aaaEfzjm8VM9pjoioQB3yWikq59+v3KByyQN+2oYTGoVYX2bUJfViZLmK0K1XWDNi4rn0/ScTigkafeRtLAiklMRxwMI/Ue8LbdNVFQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AXEQZIue; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AXEQZIue" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 809A0C4CEF7; Sun, 15 Feb 2026 03:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771127892; bh=jsM6rUIEAwjwmIUoIADEtW5CiHC9ZcogfvHijHZpuys=; h=From:To:Cc:Subject:Date:From; b=AXEQZIueajJ7DSzROwzTv2ACIB0cWHnp8cKrN44oY7F4k5wUfahMoqA1vTzqNfbic RwRxyMU+tZqNsGzixcYy6Ki0Qfr23XH4NNGEbFTo5/8YzsXtaSCg3EyCjZYPvGq+nn 7HXhlPR3evjZ+YVDMQV+NrTqlGmIDV1D4j+kMXdIgp95bsUYdMg3Q3DWAMcTQKsZji zS04TsnIjwFpvY09XV8HoOOTzoZ5yFJ3X/3byZt7Ur66jeGGpy7QAsqqBb6hXRrXBw b8j+qnMVgtbnVUUoDY5Py9xed73WuybqloJ/+Mc/QaiAlzD5jqskm8p75qTOXUul0E mSLg6dyP46nLw== From: Jisheng Zhang To: Catalin Marinas , Will Deacon , Dennis Zhou , Tejun Heo , Christoph Lameter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: [PATCH] arm64: remove HAVE_CMPXCHG_LOCAL Date: Sun, 15 Feb 2026 11:39:44 +0800 Message-ID: <20260215033944.16374-1-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It turns out the generic disable/enable irq this_cpu_cmpxchg implementation is faster than LL/SC or lse implementation. Remove HAVE_CMPXCHG_LOCAL for better performance on arm64. Tested on Quad 1.9GHZ CA55 platform: average mod_node_page_state() cost decreases from 167ns to 103ns the spawn (30 duration) benchmark in unixbench is improved from 147494 lps to 150561 lps, improved by 2.1% Tested on Quad 2.1GHZ CA73 platform: average mod_node_page_state() cost decreases from 113ns to 85ns the spawn (30 duration) benchmark in unixbench is improved from 209844 lps to 212581 lps, improved by 1.3% Signed-off-by: Jisheng Zhang --- arch/arm64/Kconfig | 1 - arch/arm64/include/asm/percpu.h | 24 ------------------------ 2 files changed, 25 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 38dba5f7e4d2..5e7e2e65d5a5 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -205,7 +205,6 @@ config ARM64 select HAVE_EBPF_JIT select HAVE_C_RECORDMCOUNT select HAVE_CMPXCHG_DOUBLE - select HAVE_CMPXCHG_LOCAL select HAVE_CONTEXT_TRACKING_USER select HAVE_DEBUG_KMEMLEAK select HAVE_DMA_CONTIGUOUS diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percp= u.h index b57b2bb00967..70ffe566cb4b 100644 --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -232,30 +232,6 @@ PERCPU_RET_OP(add, add, ldadd) #define this_cpu_xchg_8(pcp, val) \ _pcp_protect_return(xchg_relaxed, pcp, val) =20 -#define this_cpu_cmpxchg_1(pcp, o, n) \ - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) -#define this_cpu_cmpxchg_2(pcp, o, n) \ - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) -#define this_cpu_cmpxchg_4(pcp, o, n) \ - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) -#define this_cpu_cmpxchg_8(pcp, o, n) \ - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) - -#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n) - -#define this_cpu_cmpxchg128(pcp, o, n) \ -({ \ - typedef typeof(pcp) pcp_op_T__; \ - u128 old__, new__, ret__; \ - pcp_op_T__ *ptr__; \ - old__ =3D o; \ - new__ =3D n; \ - preempt_disable_notrace(); \ - ptr__ =3D raw_cpu_ptr(&(pcp)); \ - ret__ =3D cmpxchg128_local((void *)ptr__, old__, new__); \ - preempt_enable_notrace(); \ - ret__; \ -}) =20 #ifdef __KVM_NVHE_HYPERVISOR__ extern unsigned long __hyp_per_cpu_offset(unsigned int cpu); --=20 2.51.0