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Sat, 14 Feb 2026 02:52:09 -0800 (PST) Received: from nuvole.lan ([2408:824c:a13:29e0::c83]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a6f9d34sm18436865ad.11.2026.02.14.02.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Feb 2026 02:52:09 -0800 (PST) From: Pengyu Luo To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: Pengyu Luo , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/msm/dsi: fix hdisplay calculation when programming dsi registers Date: Sat, 14 Feb 2026 18:51:28 +0800 Message-ID: <20260214105145.105308-1-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Recently, the hdisplay calculation is working for 3:1 compressed ratio only. If we have a video panel with DSC BPP =3D 8, and BPC =3D 10, we still use the default bits_per_pclk =3D 24, then we get the wrong hdisplay. We can draw the conclusion by cross-comparing the calculation with the calculation in dsi_adjust_pclk_for_compression(). Since CMD mode does not use this, we can remove !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) safely. Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI") Signed-off-by: Pengyu Luo Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index e0de545d4..e8e83ee61 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -993,7 +993,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_h= ost, bool is_bonded_dsi) =20 if (msm_host->dsc) { struct drm_dsc_config *dsc =3D msm_host->dsc; - u32 bytes_per_pclk; + u32 bits_per_pclk; =20 /* update dsc params with timing params */ if (!dsc || !mode->hdisplay || !mode->vdisplay) { @@ -1015,7 +1015,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm= _host, bool is_bonded_dsi) =20 /* * DPU sends 3 bytes per pclk cycle to DSI. If widebus is - * enabled, bus width is extended to 6 bytes. + * enabled, MDP always sends out 48-bit compressed data per + * pclk and on average, DSI consumes an amount of compressed + * data equivalent to the uncompressed pixel depth per pclk. * * Calculate the number of pclks needed to transmit one line of * the compressed data. @@ -1027,12 +1029,12 @@ static void dsi_timing_setup(struct msm_dsi_host *m= sm_host, bool is_bonded_dsi) * unused anyway. */ h_total -=3D hdisplay; - if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) - bytes_per_pclk =3D 6; + if (wide_bus_enabled) + bits_per_pclk =3D mipi_dsi_pixel_format_to_bpp(msm_host->format); else - bytes_per_pclk =3D 3; + bits_per_pclk =3D 24; =20 - hdisplay =3D DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), byt= es_per_pclk); + hdisplay =3D DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc) * 8,= bits_per_pclk); =20 h_total +=3D hdisplay; ha_end =3D ha_start + hdisplay; --=20 2.53.0