From nobody Thu Apr 2 23:55:40 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03524318BB8 for ; Fri, 13 Feb 2026 23:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771026684; cv=none; b=NmSeSGKvSmRHERmvLBI0mf5yjZDu3dCSXEoQ1lhSYNqk9wJZRTCwOQ7ekkn1WkGCvUckvDt51kjZEde30UensQXcdozqzb/k40zGkg09WGo54leFiFJzVkTH46HviV/+80fsiXuGTBiXthIWzumTDCnv0DSDlD7qz/D26W3dBic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771026684; c=relaxed/simple; bh=X+3OaUCM7JMNxjttAcXah1qLd9IMX4XRKjhynJqmqAo=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=oH63jEM6hCLcP4L/k3qgnVYJM/0rErGLJh0Q/nUp0wQudzZyPQB22C8EGhuflFqSwmc4aYISc98LK31K3nizAPL7sP6MF4iVCn8kxmSVv7ZcrO0t1a95r51Iy9hM1yXzP1GO2F+/ZTNVkFM7k7IrPH+UvRkFX799utrzljE4qQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gjmKwYRt; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gjmKwYRt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771026683; x=1802562683; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=X+3OaUCM7JMNxjttAcXah1qLd9IMX4XRKjhynJqmqAo=; b=gjmKwYRtvBjenD6RcNnd0Y46T9OwSR+mflW0+LBzS6FDYYsZ/7hM29te HiwsgBN3+4DUEugCoxm2QQpYvvElYfAd8UpFu3Fm6I1Ppgc2QxQjq3mkx f2z9HXDL66d8bFiSyNYJ9SbIvyDLIXx20Lu2twbmynNSiSlyUcHZSbYIB B3T4gE0HpAMIfrG3aoPYOIfPhIDjbeSwHhiGwa4HN3/kG+VJ3KeI/KieI IN0ry9XCfXalLFD5sXTPuzu+oJsRzBxYFoT1RlDKAegGDMo//6zMtfNpN YjErQZBaC57k5gPJvJp19Qy3w+zT/bHnHVnx3luZbL7Wciy7K8amzHrl+ g==; X-CSE-ConnectionGUID: fR105tLoTt+Yxw/AVxXx9w== X-CSE-MsgGUID: YitTBkONSxCQauJMBr4CWA== X-IronPort-AV: E=McAfee;i="6800,10657,11700"; a="89803976" X-IronPort-AV: E=Sophos;i="6.21,289,1763452800"; d="scan'208";a="89803976" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2026 15:51:23 -0800 X-CSE-ConnectionGUID: uCoG8ykpSZWabUoQiTsTTA== X-CSE-MsgGUID: I8oeHROZS5q6PplOraa3EA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,289,1763452800"; d="scan'208";a="212895745" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa009.jf.intel.com with ESMTP; 13 Feb 2026 15:51:23 -0800 Subject: [PATCH 2/4] x86/cpu: Add platform ID to CPU info structure To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, zhao1.liu@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Fri, 13 Feb 2026 15:51:22 -0800 References: <20260213235119.6A9A0F80@davehans-spike.ostc.intel.com> In-Reply-To: <20260213235119.6A9A0F80@davehans-spike.ostc.intel.com> Message-Id: <20260213235122.2BAD7962@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The end goal here is to be able to do x86_match_cpu() and match on a specific platform ID. While it would be possible to stash this ID off somewhere or read it dynamically, that approaches would not be consistent with the other fields which can be matched. Read the platform ID and store it in cpuinfo_x86. There are lots of sites to set this new field. Place it near the place c->microcode is established since the platform ID is so closely intertwined with microcode updates. Note: This should not grow the size of 'struct cpuinfo_x86' in practice since the u8 fits next to another u8 in the structure. Signed-off-by: Dave Hansen Reviewed-by: Sohil Mehta Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler -- Changes from v2: * rename x86_platform_id=3D>intel_platform_id and remove initialization from generic code * Add a amd_unused so it's clear the AMD folks have a free field to play with. --- b/arch/x86/include/asm/microcode.h | 2 ++ b/arch/x86/include/asm/processor.h | 5 +++++ b/arch/x86/kernel/cpu/intel.c | 1 + b/arch/x86/kernel/cpu/microcode/intel.c | 2 +- 4 files changed, 9 insertions(+), 1 deletion(-) diff -puN arch/x86/include/asm/microcode.h~cpu-x86_stepping arch/x86/includ= e/asm/microcode.h --- a/arch/x86/include/asm/microcode.h~cpu-x86_stepping 2026-02-13 15:51:01= .027353195 -0800 +++ b/arch/x86/include/asm/microcode.h 2026-02-13 15:51:01.069354824 -0800 @@ -61,6 +61,8 @@ static inline int intel_microcode_get_da return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; } =20 +extern u32 intel_get_platform_id(void); + static inline u32 intel_get_microcode_revision(void) { u32 rev, dummy; diff -puN arch/x86/include/asm/processor.h~cpu-x86_stepping arch/x86/includ= e/asm/processor.h --- a/arch/x86/include/asm/processor.h~cpu-x86_stepping 2026-02-13 15:51:01= .032353389 -0800 +++ b/arch/x86/include/asm/processor.h 2026-02-13 15:51:01.069354824 -0800 @@ -140,6 +140,11 @@ struct cpuinfo_x86 { __u32 x86_vfm; }; __u8 x86_stepping; + union { + // MSR_IA32_PLATFORM_ID[52-50] + __u8 intel_platform_id; + __u8 amd_unused; + }; #ifdef CONFIG_X86_64 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ int x86_tlbsize; diff -puN arch/x86/kernel/cpu/intel.c~cpu-x86_stepping arch/x86/kernel/cpu/= intel.c --- a/arch/x86/kernel/cpu/intel.c~cpu-x86_stepping 2026-02-13 15:51:01.0453= 53894 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2026-02-13 15:51:01.069354824 -0800 @@ -205,6 +205,7 @@ static void early_init_intel(struct cpui =20 if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode =3D intel_get_microcode_revision(); + c->intel_platform_id =3D intel_get_platform_id(); =20 /* Now if any of them are set, check the blacklist and clear the lot */ if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || diff -puN arch/x86/kernel/cpu/microcode/intel.c~cpu-x86_stepping arch/x86/k= ernel/cpu/microcode/intel.c --- a/arch/x86/kernel/cpu/microcode/intel.c~cpu-x86_stepping 2026-02-13 15:= 51:01.066354708 -0800 +++ b/arch/x86/kernel/cpu/microcode/intel.c 2026-02-13 15:51:01.069354824 -= 0800 @@ -133,7 +133,7 @@ static u32 intel_cpuid_vfm(void) return IFM(fam, model); } =20 -static u32 intel_get_platform_id(void) +u32 intel_get_platform_id(void) { unsigned int val[2]; =20 _