From nobody Thu Apr 2 23:55:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF1382248AF for ; Fri, 13 Feb 2026 23:51:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771026683; cv=none; b=ddd9lKnFdMJ+zpNkZjm1jovV0SmPhQps2rYN18KsdnqDCb7t2k4ThXywOGzJ59p6OJHbZObIkj1XDjxgOc9qRVMfYPWvT7kJyPuum4UwVFonKXspyRego/6T2OzCR5v4cDKs+4agOUnGd62Lm0YNn/8lA6i42TPmtuXvL1JggQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771026683; c=relaxed/simple; bh=pslURc/4s9MKSeRBS2baQDAN/eUJWzMVuKZgyGzcWKc=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=jg6WAQ9crvcRxr5Y4Pix0wtzJXa0LKf/sEPA7e8BtiqSm8vTUx+F2NacYOxbRDiDHOgX/97THOnBGZTyRGc6+najFj68coMH1iwyf5NuDnpIrCh6ewW/OBceU+Vu4FYfZ1XJzxCkRriWMB8mbMM2KTDRw53d4s8E0WTrqz1wgUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aJ9NlFAh; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aJ9NlFAh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771026682; x=1802562682; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=pslURc/4s9MKSeRBS2baQDAN/eUJWzMVuKZgyGzcWKc=; b=aJ9NlFAhcsjwrURNEcL4DiBbiWfg38oTabgjocsF4cVHYkaPPYOslsRL R6HdCX5T5o++b7AZU8XRogAeZ62hVvA4UZ5Ctvb9lo0uY3xEAd7nyYIuE yRqxthU/tWtuFdhaCnbV9KcmapBhjP009MMUQPnHwaN0qAiCVgO9XGnf6 sdtYdVKMhM2lxDHMtXs2FvKhFwo14UC3mkUzW/Vu0IJnu4D7SqguT7tnn +GF9XPQJinSpUlUxOx7yMmXc5tdiC+PBLqRe8Ma1jV5hcKlMBguZit3oq xeg04XZgScfGfEZ25/QTDqMl7I1yt2XynKdC8hHz1hLvQIbWWcWBtJgvJ A==; X-CSE-ConnectionGUID: NaoyVxpmSY2ywWhAZB5ZBQ== X-CSE-MsgGUID: 7fzL0G2gSoyhvHsclT5S4w== X-IronPort-AV: E=McAfee;i="6800,10657,11700"; a="89803969" X-IronPort-AV: E=Sophos;i="6.21,289,1763452800"; d="scan'208";a="89803969" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2026 15:51:21 -0800 X-CSE-ConnectionGUID: Ri6hAbOHTAyiB+kzX2/90w== X-CSE-MsgGUID: cP48vUuAS6GezX+lPFP2Bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,289,1763452800"; d="scan'208";a="212895737" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa009.jf.intel.com with ESMTP; 13 Feb 2026 15:51:21 -0800 Subject: [PATCH 1/4] x86/microcode: Refactor platform ID enumeration into a helper To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, zhao1.liu@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Fri, 13 Feb 2026 15:51:21 -0800 References: <20260213235119.6A9A0F80@davehans-spike.ostc.intel.com> In-Reply-To: <20260213235119.6A9A0F80@davehans-spike.ostc.intel.com> Message-Id: <20260213235121.58F9C720@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen Today, the only code that cares about the platform ID is the microcode update code itself. To facilitate storing the platform ID in a more generic place and using it outside of the microcode update itself, put the enumeration into a helper function. Mirror intel_get_microcode_revision()'s naming and location. But, moving away from intel_collect_cpu_info() means that the model and family information in CPUID is not readily available. Just call CPUID again. Note that the microcode header is a mask of supported platform IDs. Only stick the ID part in the helper. Leave the 1< Reviewed-by: Sohil Mehta Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler --- b/arch/x86/kernel/cpu/microcode/intel.c | 40 ++++++++++++++++++++++++---= ----- 1 file changed, 31 insertions(+), 9 deletions(-) diff -puN arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flag= s arch/x86/kernel/cpu/microcode/intel.c --- a/arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags 20= 26-02-13 15:51:00.488332290 -0800 +++ b/arch/x86/kernel/cpu/microcode/intel.c 2026-02-13 15:51:00.492332445 -= 0800 @@ -120,19 +120,41 @@ static inline unsigned int exttable_size return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } =20 +/* + * Use CPUID to generate a "vfm" value. Useful + * before 'cpuinfo_x86' structures are populated. + */ +static u32 intel_cpuid_vfm(void) +{ + u32 eax =3D cpuid_eax(1); + u32 fam =3D x86_family(eax); + u32 model =3D x86_model(eax); + + return IFM(fam, model); +} + +static u32 intel_get_platform_id(void) +{ + unsigned int val[2]; + + /* + * This can be called early. Use CPUID directly to + * generate the VFM value for this CPU. + */ + if (intel_cpuid_vfm() < INTEL_PENTIUM_III_DESCHUTES) + return 0; + + /* get processor flags from MSR 0x17 */ + native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + + return (val[1] >> 18) & 7; +} + void intel_collect_cpu_info(struct cpu_signature *sig) { sig->sig =3D cpuid_eax(1); - sig->pf =3D 0; sig->rev =3D intel_get_microcode_revision(); - - if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >=3D INTEL_PENTIUM_III= _DESCHUTES) { - unsigned int val[2]; - - /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - sig->pf =3D 1 << ((val[1] >> 18) & 7); - } + sig->pf =3D 1 << intel_get_platform_id(); } EXPORT_SYMBOL_GPL(intel_collect_cpu_info); =20 _