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Fri, 13 Feb 2026 09:51:12 -0500 From: Antoniu Miclaus To: Lars-Peter Clausen , Michael Hennerich , Antoniu Miclaus , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Mark Brown , , , , Subject: [PATCH v3 4/5] dt-bindings: iio: adc: ad4080: add AD4880 support Date: Fri, 13 Feb 2026 16:47:36 +0200 Message-ID: <20260213144742.16394-5-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260213144742.16394-1-antoniu.miclaus@analog.com> References: <20260213144742.16394-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEzMDExNSBTYWx0ZWRfX1Es5LUNdqdyE Ly2hGRwXjAgQ5hZf06LuPray/6GYyvMsbNarBVFUqFI1dtvamnRQozmJVPNbzssQ3AwmUUtD6zU kTyQ26adfubKKkg2y1uTm8xCaQaIRLLU6mIgwIFj0h7wPFBc8NWq8lGagpnxW/EGUmQWygsNm2t aiSz+w+bmzEhL1s86Cm1JHony4ziE8x4bqWs8RU78l8PEkOiBJVVqTjYrvE7E37kXDxFVZIYHVU 11LAilfnUjA7hLezTWGJ0M7T1dWcd+xmcI98eYnrTgw2hfvNqVQy1U5Bu/tSgVFM1LsNvA0BLZ0 ZhCNArXjK2VJyTLhgVpEDBabYt74JN82Nkl2eiCEAJXY/W/VQmjfd4f6o2geyfCR/mwpkG7lzFk D65TQz/KmQ8co3C0V5TUgoXzFYXPigsgBBp4yZuds+bOIofHPigzFBTlyc3ZxYz8ZbJJaTQXfOW tJ1C6pPGk9DK+L5+YVA== X-Proofpoint-GUID: 62J2WAGO4UIyVhFqFpY1AuVNdsuh_UvU X-Proofpoint-ORIG-GUID: 62J2WAGO4UIyVhFqFpY1AuVNdsuh_UvU X-Authority-Analysis: v=2.4 cv=CPsnnBrD c=1 sm=1 tr=0 ts=698f3a69 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gAnH3GRIAAAA:8 a=eYjWAXzLS8b0uuH4XOwA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-13_03,2026-02-12_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602130115 Content-Type: text/plain; charset="utf-8" Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC with integrated fully differential amplifiers (FDA). The AD4880 has two independent ADC channels, each with its own SPI configuration interface. This requires: - Two entries in reg property for primary and secondary channel chip selects - Two io-backends entries for the two data channels Signed-off-by: Antoniu Miclaus --- Changes in v3: - Add items descriptions for io-backends entries - Fix reg example format: reg =3D <0 1> -> reg =3D <0>, <1> .../bindings/iio/adc/adi,ad4080.yaml | 54 ++++++++++++++++++- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index ccd6a0ac1539..871bbdd7e1ce 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -18,7 +18,11 @@ description: | service a wide variety of precision, wide bandwidth data acquisition applications. =20 + The AD4880 is a dual-channel variant with two independent ADC channels, + each with its own SPI configuration interface. + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 80.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad48= 80.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -31,9 +35,15 @@ properties: - adi,ad4084 - adi,ad4086 - adi,ad4087 + - adi,ad4880 =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + description: + SPI chip select(s). For single-channel devices, one chip select. + For multi-channel devices like AD4880, two chip selects are required + as each channel has its own SPI configuration interface. =20 spi-max-frequency: description: Configuration of the SPI bus. @@ -57,7 +67,11 @@ properties: vrefin-supply: true =20 io-backends: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: Backend for channel A (primary) + - description: Backend for channel B (secondary) =20 adi,lvds-cnv-enable: description: Enable the LVDS signal type on the CNV pin. Default is CM= OS. @@ -78,6 +92,25 @@ required: - vdd33-supply - vrefin-supply =20 +allOf: + - if: + properties: + compatible: + contains: + const: adi,ad4880 + then: + properties: + reg: + minItems: 2 + io-backends: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + io-backends: + maxItems: 1 + additionalProperties: false =20 examples: @@ -98,4 +131,21 @@ examples: io-backends =3D <&iio_backend>; }; }; + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4880"; + reg =3D <0>, <1>; + spi-max-frequency =3D <10000000>; + vdd33-supply =3D <&vdd33>; + vddldo-supply =3D <&vddldo>; + vrefin-supply =3D <&vrefin>; + clocks =3D <&cnv>; + clock-names =3D "cnv"; + io-backends =3D <&iio_backend_cha>, <&iio_backend_chb>; + }; + }; ... --=20 2.43.0