From nobody Fri Apr 17 21:54:36 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 915B31E376C for ; Fri, 13 Feb 2026 14:17:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770992244; cv=none; b=eCyMgJVlyZI/oGFddXgqj87+AwbMAZ/mg4ytljdaH5jH7SZ2p1kafGMl1slPNhCxStO1vwPNt42TJozx4g8eHdTUXuiWkKbkjQpwEg/UnVDPblOvY2DQBm3KqmMzT8MsnGU7EZffP8cyT7cGBG2AvTpU1G6YClSdxstlOznyYuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770992244; c=relaxed/simple; bh=zMgXfy0AVIYjbtYMGNYd/7d7nMva7d3/0wcRBrdhm/Y=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type; b=WIXenZSUfcTLk7ffplMHKURLsyjxgjLS1WEdc8z48990erSzNMtayPulb65VwO1QqYYgmeJ4zYmK56a8Wn130frSVuBCNH6kDR/14qBsNSSx8Sd9KFpAWQw7HgV5QjiE48UpjsMCBAbuJsWl+fjDRkk3/VoHIhVAxJyUdUA6HlY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=Iiek6Azk; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Iiek6Azk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770992242; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=aGM67z7MBG7JNFtGawWZM4e/8S6RBoOC2Sl8x67NLQ8=; b=Iiek6AzkLxiUqp3OpU4q8JWqlNKVeNfWUXA5w5gjPaM1ig0JEpPNBJhvAwa74XT1yE+gM8 jYsxFMRJZ2+F9MJxYDMh9P/Pw7meUIhlP4g5SxfjDcm1jYyNaKh8uapmLxKXJIVDSAmCzm /u8/QGvm5CZJMg5Finnmsfz4+H4dQJc= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-121-jZXz3ExRNgOiIfbg2brh-Q-1; Fri, 13 Feb 2026 09:17:17 -0500 X-MC-Unique: jZXz3ExRNgOiIfbg2brh-Q-1 X-Mimecast-MFC-AGG-ID: jZXz3ExRNgOiIfbg2brh-Q_1770992235 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id ED48C1800367; Fri, 13 Feb 2026 14:17:14 +0000 (UTC) Received: from ShadowPeak.redhat.com (unknown [10.45.225.39]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 2E99619560B9; Fri, 13 Feb 2026 14:17:10 +0000 (UTC) From: Petr Oros To: netdev@vger.kernel.org Cc: ivecera@redhat.com, Petr Oros , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Arkadiusz Kubalewski , Simon Horman , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH net] ice: fix missing SMA pin initialization in DPLL subsystem Date: Fri, 13 Feb 2026 15:16:51 +0100 Message-ID: <20260213141651.2231124-1-poros@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 The DPLL SMA/U.FL pin redesign introduced ice_dpll_sw_pin_frequency_get() which gates frequency reporting on the pin's active flag. This flag is determined by ice_dpll_sw_pins_update() from the PCA9575 GPIO expander state. Before the redesign, SMA pins were exposed as direct HW input/output pins and ice_dpll_frequency_get() returned the CGU frequency unconditionally =E2=80=94 the PCA9575 state was never consulted. The PCA9575 powers on with all outputs high, setting ICE_SMA1_DIR_EN, ICE_SMA1_TX_EN, ICE_SMA2_DIR_EN and ICE_SMA2_TX_EN. Nothing in the driver writes the register during initialization, so ice_dpll_sw_pins_update() sees all pins as inactive and ice_dpll_sw_pin_frequency_get() permanently returns 0 Hz for every SW pin. Fix this by writing a default SMA configuration in ice_dpll_init_info_sw_pins(): clear all SMA bits, then set SMA1 and SMA2 as active inputs (DIR_EN=3D0) with U.FL1 output and U.FL2 input disabled. Each SMA/U.FL pair shares a physical signal path so only one pin per pair can be active at a time. U.FL pins still report frequency 0 after this fix: U.FL1 (output-only) is disabled by ICE_SMA1_TX_EN which keeps the TX output buffer off, and U.FL2 (input-only) is disabled by ICE_SMA2_UFL2_RX_DIS. They can be activated by changing the corresponding SMA pin direction via dpll netlink. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Signed-off-by: Petr Oros Reported-by: Liang Li Reviewed-by: Arkadiusz Kubalewski Reviewed-by: Ivan Vecera --- drivers/net/ethernet/intel/ice/ice_dpll.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 53b54e395a2ed8..c2ad39bfe177db 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -3545,6 +3545,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *= pf) struct ice_dpll_pin *pin; u32 phase_adj_max, caps; int i, ret; + u8 data; =20 if (pf->hw.device_id =3D=3D ICE_DEV_ID_E810C_QSFP) input_idx_offset =3D ICE_E810_RCLK_PINS_NUM; @@ -3604,6 +3605,22 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf = *pf) } ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } + + /* Initialize the SMA control register to a known-good default state. + * Without this write the PCA9575 GPIO expander retains its power-on + * default (all outputs high) which makes all SW pins appear inactive. + * Set SMA1 and SMA2 as active inputs, disable U.FL1 output and + * U.FL2 input. + */ + ret =3D ice_read_sma_ctrl(&pf->hw, &data); + if (ret) + return ret; + data &=3D ~ICE_ALL_SMA_MASK; + data |=3D ICE_SMA1_TX_EN | ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS; + ret =3D ice_write_sma_ctrl(&pf->hw, data); + if (ret) + return ret; + ret =3D ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, NULL); if (ret) --=20 2.52.0