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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65bace3fc4esm674231a12.0.2026.02.13.05.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 05:15:03 -0800 (PST) From: Luca Weiss Date: Fri, 13 Feb 2026 14:15:01 +0100 Subject: [PATCH v3 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-sm6350-camss-v3-1-30a845b0b7cc@fairphone.com> References: <20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com> In-Reply-To: <20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770988501; l=16702; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=rTJAFXheRFItVqL+IO8ZybQvFNagM/AJXl6pms2q4U8=; b=D3xx9MXy2VKrzzAZVqdc06DERtGVQE35K7DRZUE4/6VFgArcThmIpSqcBKn0aTxjxlmz7fLDW hT7iVqtROTZD5ZvpyUDmOw1MqcztQEIWaIVGGdDGk+lyY1HbU702qL5 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add bindings for the Camera Subsystem on the SM6350 SoC. Signed-off-by: Luca Weiss --- .../bindings/media/qcom,sm6350-camss.yaml | 471 +++++++++++++++++= ++++ 1 file changed, 471 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml= b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml new file mode 100644 index 000000000000..d9dde154edeb --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml @@ -0,0 +1,471 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm6350-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Camera Subsystem (CAMSS) + +maintainers: + - Luca Weiss + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm6350-camss + + reg: + maxItems: 24 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite + - const: a5_csr + - const: a5_qgic + - const: a5_sierra + - const: bps + - const: camnoc + - const: core_top_csr_tcsr + - const: cpas_cdm + - const: cpas_top + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: lrme + + clocks: + maxItems: 39 + + clock-names: + items: + - const: cam_axi + - const: soc_ahb + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe2_axi + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe2_csid + - const: vfe_lite + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: bps + - const: bps_ahb + - const: bps_areg + - const: bps_axi + - const: icp + - const: ipe0 + - const: ipe0_ahb + - const: ipe0_areg + - const: ipe0_axi + - const: jpeg + - const: lrme + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite + - const: a5 + - const: cpas + - const: cpas_cdm + - const: jpeg_dma + - const: jpeg_enc + - const: lrme + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 14 + + power-domains: + maxItems: 6 + + power-domain-names: + items: + - const: bps + - const: ife0 + - const: ife1 + - const: ife2 + - const: ipe + - const: top + + vdd-csiphy0-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY0. + + vdd-csiphy0-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY0. + + vdd-csiphy1-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY1. + + vdd-csiphy1-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY1. + + vdd-csiphy2-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY2. + + vdd-csiphy2-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY2. + + vdd-csiphy3-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY3. + + vdd-csiphy3-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY3. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@acb3000 { + compatible =3D "qcom,sm6350-camss"; + + reg =3D <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0ac68000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac6f000 0x0 0x8000>, + <0x0 0x0ac42000 0x0 0x4600>, + <0x0 0x01fc0000 0x0 0x40000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac87000 0x0 0xa000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0xa00>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5_csr", + "a5_qgic", + "a5_sierra", + "bps", + "camnoc", + "core_top_csr_tcsr", + "cpas_cdm", + "cpas_top", + "ipe", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + clocks =3D <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CORE_AHB_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_CLK>, + <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_CSID_CLK>, + <&camcc CAMCC_BPS_CLK>, + <&camcc CAMCC_BPS_AHB_CLK>, + <&camcc CAMCC_BPS_AREG_CLK>, + <&camcc CAMCC_BPS_AXI_CLK>, + <&camcc CAMCC_ICP_CLK>, + <&camcc CAMCC_IPE_0_CLK>, + <&camcc CAMCC_IPE_0_AHB_CLK>, + <&camcc CAMCC_IPE_0_AREG_CLK>, + <&camcc CAMCC_IPE_0_AXI_CLK>, + <&camcc CAMCC_JPEG_CLK>, + <&camcc CAMCC_LRME_CLK>; + clock-names =3D "cam_axi", + "soc_ahb", + "camnoc_axi", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_areg", + "bps_axi", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5", + "cpas", + "cpas_cdm", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIV= E_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWA= YS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x820 0xc0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0xc0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0xc40 0x20>, + <&apps_smmu 0xc60 0x20>, + <&apps_smmu 0xc80 0x0>, + <&apps_smmu 0xca2 0x0>, + <&apps_smmu 0xcc0 0x20>, + <&apps_smmu 0xce0 0x20>, + <&apps_smmu 0xd00 0x20>, + <&apps_smmu 0xd20 0x20>, + <&apps_smmu 0xd40 0x20>, + <&apps_smmu 0xd60 0x20>; + + power-domains =3D <&camcc BPS_GDSC>, + <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IPE_0_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names =3D "bps", + "ife0", + "ife1", + "ife2", + "ipe", + "top"; + + vdd-csiphy0-0p9-supply =3D <&vreg_l18a>; + vdd-csiphy0-1p25-supply =3D <&vreg_l22a>; + vdd-csiphy1-0p9-supply =3D <&vreg_l18a>; + vdd-csiphy1-1p25-supply =3D <&vreg_l22a>; + vdd-csiphy2-0p9-supply =3D <&vreg_l18a>; + vdd-csiphy2-1p25-supply =3D <&vreg_l22a>; + vdd-csiphy3-0p9-supply =3D <&vreg_l18a>; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65bace3fc4esm674231a12.0.2026.02.13.05.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 05:15:05 -0800 (PST) From: Luca Weiss Date: Fri, 13 Feb 2026 14:15:02 +0100 Subject: [PATCH v3 2/3] media: qcom: camss: Add SM6350 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-sm6350-camss-v3-2-30a845b0b7cc@fairphone.com> References: <20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com> In-Reply-To: <20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770988501; l=16195; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=TvUhDjM6zXcYKCp6b8M4X+IbmdcSfgsD/ePyNdzN+cc=; b=asIhzfwbzdYpLc2/H4Q2StVl4cwiq0oZprETTVVw0CRUBcD40Mr3c8An/VEZToBjkGd4fWpkP q9a74cW4p9uCrLLX1mUhONXeCl5P0nLWwF11Eh+DL8V6Vat9yAqYWAx X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the necessary support for CAMSS on the SM6350 SoC. Signed-off-by: Luca Weiss --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 125 ++++++++++ drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 261 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 389 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 415483274552..2b0c21c90e30 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -399,6 +399,126 @@ csiphy_lane_regs lane_regs_sm8250[] =3D { {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.2.3 2PH */ +static const struct +csiphy_lane_regs lane_regs_sm6350[] =3D { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0260, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x065C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0660, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, +}; + /* 14nm 2PH v 2.0.1 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_qcm2290[] =3D { @@ -1011,6 +1131,7 @@ static bool csiphy_is_gen2(u32 version) switch (version) { case CAMSS_2290: case CAMSS_6150: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: @@ -1105,6 +1226,10 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_qcm2290[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); break; + case CAMSS_6350: + regs->lane_regs =3D &lane_regs_sm6350[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); + break; case CAMSS_7280: case CAMSS_8250: regs->lane_regs =3D &lane_regs_sm8250[0]; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 5baf0e3d4bc4..7dc937d018f6 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -343,6 +343,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_660: case CAMSS_2290: case CAMSS_6150: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8x96: case CAMSS_8250: @@ -2003,6 +2004,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) =20 switch (vfe->camss->res->version) { case CAMSS_6150: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 00b87fd9afbd..b53fb94ab54a 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1703,6 +1703,253 @@ static const struct resources_icc icc_res_sm6150[] = =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_sm6350[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy0-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy0-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy0", "csiphy0_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy1-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy1-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy1", "csiphy1_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy2-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy2-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy2", "csiphy2_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy3-0p9", .init_load_uA =3D 80000 }, + { .supply =3D "vdd-csiphy3-1p25", .init_load_uA =3D 80000 }, + }, + .clock =3D { "csiphy3", "csiphy3_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + } +}; + +static const struct camss_subdev_resources csid_res_sm6350[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "vfe0_csid", "vfe0_cphy_rx", "vfe0" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "vfe1_csid", "vfe1_cphy_rx", "vfe1" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "vfe2_csid", "vfe2_cphy_rx", "vfe2" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite" }, + .interrupt =3D { "csid_lite" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + } +}; + +static const struct camss_subdev_resources vfe_res_sm6350[] =3D { + /* VFE0 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe0", + "vfe0_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe1", + "vfe1_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe2", + "vfe2_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "camnoc_axi", "vfe_lite", + "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000 }, + { 0 }, + { 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite" }, + .interrupt =3D { "vfe_lite" }, + .vfe =3D { + .is_lite =3D true, + .line_num =3D 4, + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + +static const struct resources_icc icc_res_sm6350[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 0, + .icc_bw_tbl.peak =3D 300000, + }, + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_icp_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, +}; + static const struct camss_subdev_resources csiphy_res_8250[] =3D { /* CSIPHY0 */ { @@ -5233,6 +5480,19 @@ static const struct camss_resources sm6150_resources= =3D { .vfe_num =3D ARRAY_SIZE(vfe_res_sm6150), }; =20 +static const struct camss_resources sm6350_resources =3D { + .version =3D CAMSS_6350, + .pd_name =3D "top", + .csiphy_res =3D csiphy_res_sm6350, + .csid_res =3D csid_res_sm6350, + .vfe_res =3D vfe_res_sm6350, + .icc_res =3D icc_res_sm6350, + .icc_path_num =3D ARRAY_SIZE(icc_res_sm6350), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_sm6350), + .csid_num =3D ARRAY_SIZE(csid_res_sm6350), + .vfe_num =3D ARRAY_SIZE(vfe_res_sm6350), +}; + static const struct camss_resources sm8250_resources =3D { .version =3D CAMSS_8250, .pd_name =3D "top", @@ -5329,6 +5589,7 @@ static const struct of_device_id camss_dt_match[] =3D= { { .compatible =3D "qcom,sdm670-camss", .data =3D &sdm670_resources }, { .compatible =3D "qcom,sdm845-camss", .data =3D &sdm845_resources }, { .compatible =3D "qcom,sm6150-camss", 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65bace3fc4esm674231a12.0.2026.02.13.05.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 05:15:06 -0800 (PST) From: Luca Weiss Date: Fri, 13 Feb 2026 14:15:03 +0100 Subject: [PATCH v3 3/3] arm64: dts: qcom: sm6350: Add CAMSS node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-sm6350-camss-v3-3-30a845b0b7cc@fairphone.com> References: <20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com> In-Reply-To: <20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770988501; l=7482; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ydhmJSCIZaIH22AlYiY5zbtcSZF7dLVsHrUi82mpK0s=; b=RL7EdMIv+OMN80Kmw4Nf5DmJG6mHymFBALfSHtD/yo7ntH77Zgug+cQn//pCyoHG0+hTdPD6A /NOlgCzivb2CPcR79dceAklPuPy9H6cjQdigmKIHrCkG22eXg9ip9vQ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a node for the CAMSS on the SM6350 SoC. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 233 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 233 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 9f9b9f9af0da..07887a07644f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2161,6 +2161,239 @@ cci1_i2c0: i2c-bus@0 { /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstrea= m */ }; =20 + camss: isp@acb3000 { + compatible =3D "qcom,sm6350-camss"; + + reg =3D <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0ac68000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac6f000 0x0 0x8000>, + <0x0 0x0ac42000 0x0 0x4600>, + <0x0 0x01fc0000 0x0 0x40000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac87000 0x0 0xa000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0xa00>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5_csr", + "a5_qgic", + "a5_sierra", + "bps", + "camnoc", + "core_top_csr_tcsr", + "cpas_cdm", + "cpas_top", + "ipe", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + clocks =3D <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CORE_AHB_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_CLK>, + <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_CSID_CLK>, + <&camcc CAMCC_BPS_CLK>, + <&camcc CAMCC_BPS_AHB_CLK>, + <&camcc CAMCC_BPS_AREG_CLK>, + <&camcc CAMCC_BPS_AXI_CLK>, + <&camcc CAMCC_ICP_CLK>, + <&camcc CAMCC_IPE_0_CLK>, + <&camcc CAMCC_IPE_0_AHB_CLK>, + <&camcc CAMCC_IPE_0_AREG_CLK>, + <&camcc CAMCC_IPE_0_AXI_CLK>, + <&camcc CAMCC_JPEG_CLK>, + <&camcc CAMCC_LRME_CLK>; + clock-names =3D "cam_axi", + "soc_ahb", + "camnoc_axi", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_areg", + "bps_axi", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5", + "cpas", + "cpas_cdm", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x820 0xc0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0xc0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0xc40 0x20>, + <&apps_smmu 0xc60 0x20>, + <&apps_smmu 0xc80 0x0>, + <&apps_smmu 0xca2 0x0>, + <&apps_smmu 0xcc0 0x20>, + <&apps_smmu 0xce0 0x20>, + <&apps_smmu 0xd00 0x20>, + <&apps_smmu 0xd20 0x20>, + <&apps_smmu 0xd40 0x20>, + <&apps_smmu 0xd60 0x20>; + + power-domains =3D <&camcc BPS_GDSC>, + <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IPE_0_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names =3D "bps", + "ife0", + "ife1", + "ife2", + "ipe", + "top"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sm6350-camcc"; reg =3D <0x0 0x0ad00000 0x0 0x16000>; --=20 2.53.0