From nobody Thu Apr 2 23:55:51 2026 Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 571973559C4 for ; Fri, 13 Feb 2026 14:54:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770994491; cv=none; b=fBvACOhheZb2/2YjIt+okC6rJ/78kwZu+K9Zrzbl+zIMeGgdkF4f6/cK5/eT8r9kHRQWAQFlsXWmJpVneVa/j7Y32y1Y5l100AhqQSB7+g6lUjbXjFsOMBnSUZS+BXoMsZvt1shVM08JBgoL1hJEHhPBht2DZByhXoGrMEziLHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770994491; c=relaxed/simple; bh=0lT7RY7u/q/OvDkV4Xni5NMBZEHeI41cYul1o1LxOgY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YS5/ywzyQ4ihO/u5sIufQRYdDiFws4QlByqZa+tF/1p46lQam2aTc85mNSyXamfsRi1S921IfGcy1lk1WkYQBYS1tN/IQMlQR9TFjcCr90R/H527xRqPusZJK1OVQVtpDoX7eVI3d0umbb33Ra9au53jASjNrQk3Tbi8uiXEG/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GoHT6pul; arc=none smtp.client-ip=209.85.215.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GoHT6pul" Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-c6e1e748dc1so817634a12.1 for ; Fri, 13 Feb 2026 06:54:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770994489; x=1771599289; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+ROwhGAC+uM/YVDPTZ7SWeJKccnx9vcVwkY+8qPNgeE=; b=GoHT6pulgN+PmyX9dow7W8H5OQJihRjF1b0753weR+5VbmV1VGbHgsOCwBgd1W4CHk YhVXQun3Ar7kUmBZtFF97aC0cyh6eJPSqzn9SCkSP8M1/LFnjxMDuijPsH/xuAYdmqfa 29A2yk6IqUmIQVZizTLVUlMb9RrleTN3inzcHCNLwtHjpRsjFNBkI3M4lDnm2B78ez9i aHjEh9EipOKX0lfwxbE9qIy8GTPYI8PZpkuXilTcI0loORwMTMstAUXQ293dGF1QMfDs XxcVQDLZrpS9u+XulguCr4gRb9GHf/oJjUN6wGSPp1jEYrPBBO4gQUYvivUeCmyGwzfT r3bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770994489; x=1771599289; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+ROwhGAC+uM/YVDPTZ7SWeJKccnx9vcVwkY+8qPNgeE=; b=SyUPtRonzvVsO61bLfUQRhNe/wRfj58k0zu0DaXHg7JFn95OADhVBKYCCSaWavIr6k /aYvH5wfcKtA3SJdf4WfEi2mDexnbW2h0PjaKvYzvTFQdhfpufn9T31r6rPPS3wi0HNQ Hxi5US4glhAktND1a6sq0tpIvFUX03XWHo2PaRB0UzNl1xigDN895gWAMk2ik6E4zr8I Iyn+mzQAuB0sl9v/79q143PKU8HvckOK7M45DihonI3DKRMaqz3jF4gW13NKTmwdgYh2 DQcOo1JroWkNHt5focMBf9jytWdbYflvQS0J8g1sXBfHwTcf6C5h2FJuZjeN2LGLA/Sk +vmg== X-Forwarded-Encrypted: i=1; AJvYcCVuvu7QSzhwKfXTyL2AkY02zMRdhn8ip19m6o50bZsbn1mjQIOG7e9GiQ+LGz9yBA1dgtFzO63xb+qEIAI=@vger.kernel.org X-Gm-Message-State: AOJu0Yw/0Adj4V1GU2XxVs+egvDfehz/wFZBcqjSOgwFir1ho0U91Fzo 35XdDfy00HRbS6NVd0lpJQDNpZcu66DDh7UEf6uOEZMddflDYUmbNUpF7vkkZqA0cMw= X-Gm-Gg: AZuq6aKuqKaC124pUUSvnun8hmbLU/2Yoaz2H2m7W1TrD4TquFtzQxnU4JSi2eGMcnr wTqfKCxRz2tru/ayV4TuM1tZv46GzrWwp11rpbz1xvOmGa/Ncz/jlt736xwm4KiieVrZNgGDkA6 pgiYs4cLZ1+Kz9ojNkxvHQHyVvmv0ZWXwFAxspe8kBpgckdVHxpTkQ1+fG+/VNcSvhjtbNUeunO L2JhoFCo7dA3IiWX7aiCOQ1ZeOc4wMtu9g7x5K35r2BHyetdHk49oFvW+hf8YgWjinxqg6WYS61 Zr1qG4PQlUEsd/ZKffGX+JwzSxcMtWdilgc5bDMbqawsH9rRadvQvfV5fE50m6Wjd3mtyt0InEU 6O7O90gTxSsv60mjLnJv4IEJIC5dSAtzzhQjU3k2Zyo8h5aG0NZ36qvlU3k4UUqKuuL/vAwiT6z GIay5zVhqzd1G0To61KOFcJ1C3bAx+g4DenU4q2bhDo8Dro4P+zTC4k7XHOj4q9lQeqtg= X-Received: by 2002:a17:90b:3c03:b0:34c:7212:7a67 with SMTP id 98e67ed59e1d1-357b518b298mr278498a91.12.1770994488494; Fri, 13 Feb 2026 06:54:48 -0800 (PST) Received: from [127.0.1.1] (210-61-187-172.hinet-ip.hinet.net. [210.61.187.172]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567eba9b2esm8814759a91.9.2026.02.13.06.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 06:54:48 -0800 (PST) From: Jun Nie Date: Fri, 13 Feb 2026 22:54:25 +0800 Subject: [PATCH v18 1/4] drm/msm/dpu: Extract plane splitting into a dedicated function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-msm-next-quad-pipe-split-v18-1-5815158d3635@linaro.org> References: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> In-Reply-To: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770994473; l=3875; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=0lT7RY7u/q/OvDkV4Xni5NMBZEHeI41cYul1o1LxOgY=; b=x3weaFm2PlNMn3CfL4RIoYr1Kac9Rcr4tlBVb35PAKV9faheYU9eInS4/w7+FocmSsmDz96H1 i/T4SkPRpHuD3sgBTd56hxtfXhSSxA78YpK1OCyYy+qbvIfHGpKQEly X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= dpu_plane_atomic_check_nosspp() currently handles both plane validation and plane splitting. For better simplicity and to facilitate future refactoring, move the splitting logic into its own dedicated function. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 51 ++++++++++++++++++++++-----= ---- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 9b7a8b46bfa91..66f240ce29d07 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -821,13 +821,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, { int i, ret =3D 0, min_scale, max_scale; struct dpu_plane *pdpu =3D to_dpu_plane(plane); - struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); - u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; - uint32_t max_linewidth; =20 min_scale =3D FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale =3D MAX_DOWNSCALE_RATIO << 16; @@ -850,14 +845,6 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, return -EINVAL; } =20 - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); - - pipe_cfg->dst_rect =3D new_plane_state->dst; - fb_rect.x2 =3D new_plane_state->fb->width; fb_rect.y2 =3D new_plane_state->fb->height; =20 @@ -879,6 +866,34 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) return -E2BIG; =20 + pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); + + return 0; +} + +static int dpu_plane_split(struct drm_plane *plane, + struct drm_plane_state *new_plane_state, + const struct drm_crtc_state *crtc_state) +{ + struct dpu_plane *pdpu =3D to_dpu_plane(plane); + struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); + u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; + struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; + uint32_t max_linewidth; + + if (!new_plane_state->visible) + return 0; + + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + + pipe_cfg->dst_rect =3D new_plane_state->dst; + max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 drm_rect_rotate(&pipe_cfg->src_rect, @@ -910,8 +925,6 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); - return 0; } =20 @@ -1129,6 +1142,10 @@ static int dpu_plane_atomic_check(struct drm_plane *= plane, if (ret) return ret; =20 + ret =3D dpu_plane_split(plane, new_plane_state, crtc_state); + if (ret) + return ret; + if (!new_plane_state->visible) return 0; =20 @@ -1169,6 +1186,10 @@ static int dpu_plane_virtual_atomic_check(struct drm= _plane *plane, if (ret) return ret; =20 + ret =3D dpu_plane_split(plane, plane_state, crtc_state); + if (ret) + return ret; + if (!plane_state->visible) { /* * resources are freed by dpu_crtc_assign_plane_resources(), --=20 2.43.0