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[210.61.187.172]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567eba9b2esm8814759a91.9.2026.02.13.06.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 06:54:48 -0800 (PST) From: Jun Nie Date: Fri, 13 Feb 2026 22:54:25 +0800 Subject: [PATCH v18 1/4] drm/msm/dpu: Extract plane splitting into a dedicated function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-msm-next-quad-pipe-split-v18-1-5815158d3635@linaro.org> References: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> In-Reply-To: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770994473; l=3875; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=0lT7RY7u/q/OvDkV4Xni5NMBZEHeI41cYul1o1LxOgY=; b=x3weaFm2PlNMn3CfL4RIoYr1Kac9Rcr4tlBVb35PAKV9faheYU9eInS4/w7+FocmSsmDz96H1 i/T4SkPRpHuD3sgBTd56hxtfXhSSxA78YpK1OCyYy+qbvIfHGpKQEly X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= dpu_plane_atomic_check_nosspp() currently handles both plane validation and plane splitting. For better simplicity and to facilitate future refactoring, move the splitting logic into its own dedicated function. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 51 ++++++++++++++++++++++-----= ---- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 9b7a8b46bfa91..66f240ce29d07 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -821,13 +821,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, { int i, ret =3D 0, min_scale, max_scale; struct dpu_plane *pdpu =3D to_dpu_plane(plane); - struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); - u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; - uint32_t max_linewidth; =20 min_scale =3D FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale =3D MAX_DOWNSCALE_RATIO << 16; @@ -850,14 +845,6 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, return -EINVAL; } =20 - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); - - pipe_cfg->dst_rect =3D new_plane_state->dst; - fb_rect.x2 =3D new_plane_state->fb->width; fb_rect.y2 =3D new_plane_state->fb->height; =20 @@ -879,6 +866,34 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) return -E2BIG; =20 + pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); + + return 0; +} + +static int dpu_plane_split(struct drm_plane *plane, + struct drm_plane_state *new_plane_state, + const struct drm_crtc_state *crtc_state) +{ + struct dpu_plane *pdpu =3D to_dpu_plane(plane); + struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); + u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; + struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; + uint32_t max_linewidth; + + if (!new_plane_state->visible) + return 0; + + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + + pipe_cfg->dst_rect =3D new_plane_state->dst; + max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 drm_rect_rotate(&pipe_cfg->src_rect, @@ -910,8 +925,6 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); - return 0; } =20 @@ -1129,6 +1142,10 @@ static int dpu_plane_atomic_check(struct drm_plane *= plane, if (ret) return ret; =20 + ret =3D dpu_plane_split(plane, new_plane_state, crtc_state); + if (ret) + return ret; + if (!new_plane_state->visible) return 0; =20 @@ -1169,6 +1186,10 @@ static int dpu_plane_virtual_atomic_check(struct drm= _plane *plane, if (ret) return ret; =20 + ret =3D dpu_plane_split(plane, plane_state, crtc_state); + if (ret) + return ret; + if (!plane_state->visible) { /* * resources are freed by dpu_crtc_assign_plane_resources(), --=20 2.43.0 From nobody Thu Apr 2 22:24:28 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46A52362121 for ; Fri, 13 Feb 2026 14:54:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770994497; cv=none; b=JbJoI0mRKdQhIoGuIEpyMu0TQ1C8uty7eyplyl9ajF2pFUswbWwIR2u1EDeUVEDMm7ooWM1vwHbB9DhNRBfEnzGTK4OhL8AqTn5RyZ7UyOcF5Va4QI6ugXkndhE6hyLbDiM8MHe0V7aR7IiDWpfr01bZ3ReP4HJs6a0A8Ap1GOo= ARC-Message-Signature: i=1; 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[210.61.187.172]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567eba9b2esm8814759a91.9.2026.02.13.06.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 06:54:55 -0800 (PST) From: Jun Nie Date: Fri, 13 Feb 2026 22:54:26 +0800 Subject: [PATCH v18 2/4] drm/msm/dpu: Defer SSPP allocation until CRTC check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-msm-next-quad-pipe-split-v18-2-5815158d3635@linaro.org> References: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> In-Reply-To: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770994473; l=9685; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=i1RzzvrabPDykfHEg1NdrWB/7Psq7/tLp+Qwsh/cZPk=; b=nr7UC/X9qLl1fHVfTwnuqUJxOxnsm/m4g0kvNNqOcNxbzasp4NRSTg/+c8/2G4mlqNns6S52K H8bBOWmtDoPBjCp43KDF0ZfAOm/UtVlqmpvYNVPxnmYXvQVJSgFx1s9 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, mapping plane to SSPP occurs during the plane check phase for non-virtual plane case. The SSPP allocation and plane mapping occurs during crtc check phase for virtual plane case. Defer these SSPP operations until CRTC check stage to unify the 2 cases, and ease later revisement for quad-pipe change. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 155 +++++++++++++-------------= ---- 2 files changed, 66 insertions(+), 92 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 6bf7c46379aed..797296b14264e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1534,8 +1534,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crt= c, return rc; } =20 - if (dpu_use_virtual_planes && - (crtc_state->planes_changed || crtc_state->zpos_changed)) { + if (crtc_state->planes_changed || crtc_state->zpos_changed) { rc =3D dpu_crtc_reassign_planes(crtc, crtc_state); if (rc < 0) return rc; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 66f240ce29d07..be1a7fcf11b81 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1119,102 +1119,24 @@ static int dpu_plane_atomic_check(struct drm_plane= *plane, struct drm_plane_state *new_plane_state =3D drm_atomic_get_new_plane_stat= e(state, plane); int ret =3D 0; - struct dpu_plane *pdpu =3D to_dpu_plane(plane); - struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; - const struct drm_crtc_state *crtc_state =3D NULL; - uint32_t max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; + struct drm_crtc_state *crtc_state =3D NULL; =20 if (new_plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); =20 - pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - - if (!pipe->sspp) - return -EINVAL; - ret =3D dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); if (ret) return ret; =20 - ret =3D dpu_plane_split(plane, new_plane_state, crtc_state); - if (ret) - return ret; - if (!new_plane_state->visible) return 0; =20 - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(new_plane_state->fb), - max_linewidth)) { - DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT - " max_line:%u, can't use split source\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), - DRM_RECT_ARG(&r_pipe_cfg->src_rect), - max_linewidth); - return -E2BIG; - } - - return dpu_plane_atomic_check_sspp(plane, state, crtc_state); -} - -static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) -{ - struct drm_plane_state *plane_state =3D - drm_atomic_get_plane_state(state, plane); - struct drm_plane_state *old_plane_state =3D - drm_atomic_get_old_plane_state(state, plane); - struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); - struct drm_crtc_state *crtc_state =3D NULL; - int ret, i; - - if (IS_ERR(plane_state)) - return PTR_ERR(plane_state); - - if (plane_state->crtc) - crtc_state =3D drm_atomic_get_new_crtc_state(state, - plane_state->crtc); - - ret =3D dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state); - if (ret) - return ret; - - ret =3D dpu_plane_split(plane, plane_state, crtc_state); - if (ret) - return ret; - - if (!plane_state->visible) { - /* - * resources are freed by dpu_crtc_assign_plane_resources(), - * but clean them here. - */ - for (i =3D 0; i < PIPES_PER_PLANE; i++) - pstate->pipe[i].sspp =3D NULL; - - return 0; - } - /* - * Force resource reallocation if the format of FB or src/dst have - * changed. We might need to allocate different SSPP or SSPPs for this - * plane than the one used previously. + * To trigger the callback of dpu_assign_plane_resources() to + * finish the sspp assignment or allocation and check. */ - if (!old_plane_state || !old_plane_state->fb || - old_plane_state->src_w !=3D plane_state->src_w || - old_plane_state->src_h !=3D plane_state->src_h || - old_plane_state->crtc_w !=3D plane_state->crtc_w || - old_plane_state->crtc_h !=3D plane_state->crtc_h || - msm_framebuffer_format(old_plane_state->fb) !=3D - msm_framebuffer_format(plane_state->fb)) - crtc_state->planes_changed =3D true; - + crtc_state->planes_changed =3D true; return 0; } =20 @@ -1261,9 +1183,9 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, struct drm_plane_state *plane_state, + const struct drm_crtc_state *crtc_state, struct drm_plane_state **prev_adjacent_plane_state) { - const struct drm_crtc_state *crtc_state =3D NULL; struct drm_plane *plane =3D plane_state->plane; struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; @@ -1273,10 +1195,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, const struct msm_format *fmt; int i, ret; =20 - if (plane_state->crtc) - crtc_state =3D drm_atomic_get_new_crtc_state(state, - plane_state->crtc); - pstate =3D to_dpu_plane_state(plane_state); for (i =3D 0; i < STAGES_PER_PLANE; i++) prev_adjacent_pstate[i] =3D prev_adjacent_plane_state[i] ? @@ -1288,6 +1206,10 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, if (!plane_state->fb) return -EINVAL; =20 + ret =3D dpu_plane_split(plane, plane_state, crtc_state); + if (ret) + return ret; + fmt =3D msm_framebuffer_format(plane_state->fb); reqs.yuv =3D MSM_FORMAT_IS_YUV(fmt); reqs.scale =3D (plane_state->src_w >> 16 !=3D plane_state->crtc_w) || @@ -1318,14 +1240,56 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } =20 +static int dpu_plane_assign_resources(struct drm_crtc *crtc, + struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_plane_state *plane_state, + const struct drm_crtc_state *crtc_state, + struct drm_plane_state **prev_adjacent_plane_state) +{ + struct drm_plane *plane =3D plane_state->plane; + struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; + struct dpu_plane *pdpu =3D to_dpu_plane(plane); + int ret; + + pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + if (!pipe->sspp) + return -EINVAL; + + ret =3D dpu_plane_split(plane, plane_state, crtc_state); + if (ret) + return ret; + + if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT + " max_line:%u, can't use split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect), + dpu_kms->catalog->caps->max_linewidth); + return -E2BIG; + } + + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); +} + int dpu_assign_plane_resources(struct dpu_global_state *global_state, struct drm_atomic_state *state, struct drm_crtc *crtc, struct drm_plane_state **states, unsigned int num_planes) { - unsigned int i; struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] =3D {= NULL }; + const struct drm_crtc_state *crtc_state =3D NULL; + unsigned int i; + int ret; =20 for (i =3D 0; i < num_planes; i++) { struct drm_plane_state *plane_state =3D states[i]; @@ -1334,8 +1298,19 @@ int dpu_assign_plane_resources(struct dpu_global_sta= te *global_state, !plane_state->visible) continue; =20 - int ret =3D dpu_plane_virtual_assign_resources(crtc, global_state, + if (plane_state->crtc) + crtc_state =3D drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + if (!dpu_use_virtual_planes) + ret =3D dpu_plane_assign_resources(crtc, global_state, + state, plane_state, + crtc_state, + prev_adjacent_plane_state); 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[210.61.187.172]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567eba9b2esm8814759a91.9.2026.02.13.06.54.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 06:55:06 -0800 (PST) From: Jun Nie Date: Fri, 13 Feb 2026 22:54:27 +0800 Subject: [PATCH v18 3/4] drm/msm/dpu: support plane splitting in quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-msm-next-quad-pipe-split-v18-3-5815158d3635@linaro.org> References: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> In-Reply-To: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770994473; l=9909; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=fweWEpFUPkhuB8qLiuep4kjFOtkQyJ3oObfCoqQhEMU=; b=CB3ePUFFE20hwEjVr8jJyneuLYg/R/gfHgfVMQnxibx0lGKZq+gcDwTibdlJ8rXZui0IGswq6 GmSW0tVfgZ7AyUriYsMAr99SiPnsacigGLIH04IZ0T2RSB+K5S2mxTM X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= The content of every half of screen is sent out via one interface in dual-DSI case. The content for every interface is blended by a LM pair in quad-pipe case, thus a LM pair should not blend any content that cross the half of screen in this case. Clip plane into pipes per left and right half screen ROI if topology is quad pipe case. The clipped rectangle on every half of screen is futher handled by two pipes if its width exceeds a limit for a single pipe. For non-virtual-plane case, there is always one stage config to serve a LM or LM pair. So the clipping does not occur when interating stages in this case. The plane is mapped to 2 pipes only when width or clock rate exceeds hardware constrain within stage check. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Patchwork: https://patchwork.freedesktop.org/patch/675416/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16= -9-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 146 +++++++++++++++++++++-----= ---- 3 files changed, 117 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 797296b14264e..0bbe6c38b771a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1656,6 +1656,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } =20 +/** + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline + * @state: Pointer to drm crtc state object + */ +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) +{ + struct dpu_crtc_state *cstate =3D to_dpu_crtc_state(state); + + return cstate->num_mixers; +} + #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 94392b9b92454..6eaba5696e8e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -267,4 +267,6 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_cl= ient_type( =20 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); =20 +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); + #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index be1a7fcf11b81..c528bf924d515 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -881,50 +881,114 @@ static int dpu_plane_split(struct drm_plane *plane, struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; + const struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; uint32_t max_linewidth; + u32 num_lm; + int stage_id, num_stages; =20 if (!new_plane_state->visible) return 0; =20 - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 - pipe_cfg->dst_rect =3D new_plane_state->dst; + /* In non-virtual plane case, one mixer pair is always needed. */ + num_lm =3D dpu_crtc_get_num_lm(crtc_state); + if (dpu_use_virtual_planes) + num_stages =3D (num_lm + 1) / 2; + else + num_stages =3D 1; =20 - max_linewidth =3D pdpu->catalog->caps->max_linewidth; + /* + * For wide plane that exceeds SSPP rectangle constrain, it needed to + * be split and mapped to 2 rectangles with 1 config for 2:2:1. + * For 2 interfaces cases, such as dual DSI, 2:2:2 topology is needed. + * If the width or clock exceeds hardware limitation in every half of + * screen, 4:4:2 topology is needed and virtual plane feature should + * be enabled to map plane to more than 1 SSPP. 2 stage configs are + * needed to serve 2 mixer pairs in this 4:4:2 case. So both left/right + * half of plane splitting, and splitting within the half of screen is + * needed in quad-pipe case. Check dest rectangle left/right clipping + * and iterate mixer configs for this plane first, then check wide + * rectangle splitting in every half next. + */ + for (stage_id =3D 0; stage_id < num_stages; stage_id++) { + struct drm_rect mixer_rect =3D { + .x1 =3D stage_id * mode->hdisplay / num_stages, + .y1 =3D 0, + .x2 =3D (stage_id + 1) * mode->hdisplay / num_stages, + .y2 =3D mode->vdisplay + }; + int cfg_idx =3D stage_id * PIPES_PER_STAGE; =20 - drm_rect_rotate(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); + pipe_cfg =3D &pstate->pipe_cfg[cfg_idx]; + r_pipe_cfg =3D &pstate->pipe_cfg[cfg_idx + 1]; =20 - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_= clk_rate) { - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + + drm_rect_rotate(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + + pipe_cfg->dst_rect =3D new_plane_state->dst; + + DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT + " vs clip window " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&mixer_rect)); + + /* + * If this plane does not fall into mixer rect, check next + * mixer rect. + */ + if (!drm_rect_clip_scaled(&pipe_cfg->src_rect, + &pipe_cfg->dst_rect, + &mixer_rect)) { + memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg)); + + continue; } =20 - *r_pipe_cfg =3D *pipe_cfg; - pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2= ) >> 1; - pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2= ) >> 1; - r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; - } else { - memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); - } + pipe_cfg->dst_rect.x1 -=3D mixer_rect.x1; + pipe_cfg->dst_rect.x2 -=3D mixer_rect.x1; + + DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT= "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect)); + + /* Split wide rect into 2 rect */ + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) { + + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg)); + pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x= 2) >> 1; + pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x= 2) >> 1; + r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; + DPU_DEBUG_PLANE(pdpu, "Split wide plane into:" + DRM_RECT_FMT " and " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + } else { + memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); + } =20 - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, + new_plane_state->fb->height, new_plane_state->rotation); =20 + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, + new_plane_state->fb->height, + new_plane_state->rotation); + } + return 0; } =20 @@ -998,20 +1062,18 @@ static int dpu_plane_atomic_check_sspp(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; 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[210.61.187.172]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567eba9b2esm8814759a91.9.2026.02.13.06.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 06:55:17 -0800 (PST) From: Jun Nie Date: Fri, 13 Feb 2026 22:54:28 +0800 Subject: [PATCH v18 4/4] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-msm-next-quad-pipe-split-v18-4-5815158d3635@linaro.org> References: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> In-Reply-To: <20260213-msm-next-quad-pipe-split-v18-0-5815158d3635@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770994473; l=9265; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=70PbSNDu9x4Wj/tEPz62OV1hX90As7ZyNvi4Eury5NM=; b=4zyh7DkjPUbbGpw8FZEfqQe29yptwSjlWuLyOFUYMgTpfMz0Gu121XNASW+eRkw6Z9lfDhYep W0VSnJQv0Z1BoO8NrjyZ8HJWVK1MB9hGIbDf6INg5GPrG2ReI0/3MHw X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= To support high-resolution cases that exceed the width constrain or scenarios that surpass the maximum MDP clock rate, additional pipes are necessary to enable parallel data processing within the width constraints and MDP clock rate. Expand pipe array size to 4. Request 4 mixers and 4 DSCs for high-resolution cases where dual interfaces are enabled for virtual plane case. More use cases can be incorporated later if quad-pipe capabilities are required. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Patchwork: https://patchwork.freedesktop.org/patch/675418/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16= -10-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 48 ++++++++++++++++----= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 47 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 0bbe6c38b771a..92a182d69edd0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; =20 int rc =3D 0; int i; @@ -1377,6 +1377,9 @@ static struct msm_display_topology dpu_crtc_get_topol= ogy( struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; struct msm_display_topology topology =3D {0}; struct drm_encoder *drm_enc; + struct msm_drm_private *priv =3D crtc->dev->dev_private; + struct dpu_kms *kms =3D to_dpu_kms(priv->kms); + u32 num_rt_intf; =20 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, @@ -1389,31 +1392,44 @@ static struct msm_display_topology dpu_crtc_get_top= ology( * * Dual display * 2 LM, 2 INTF ( Split display using 2 interfaces) + * 4 LM, 2 INTF ( Split display using 2 interfaces and stream merge + to support high resolution interfaces if virtual + plane is enabled) + * If DSC is enabled, use 2:2:2 for 2 LMs case, and 4:4:2 for 4 LMs + * case. * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * - * If DSC is enabled, use 2 LMs for 2:2:1 topology + * If DSC is enabled, use 2 LMs for 2:2:1 topology for single display + * to support legacy devices that use this topology. * * Add dspps to the reservation requirements if ctm or gamma_lut are requ= ested - * - * Only hardcode num_lm to 2 for cases where num_intf =3D=3D 2 and CWB is= not - * enabled. This is because in cases where CWB is enabled, num_intf will - * count both the WB and real-time phys encoders. - * - * For non-DSC CWB usecases, have the num_lm be decided by the - * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. */ =20 - if (topology.num_intf =3D=3D 2 && !topology.cwb_enabled) - topology.num_lm =3D 2; - else if (topology.num_dsc =3D=3D 2) - topology.num_lm =3D 2; - else if (dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm =3D (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + num_rt_intf =3D topology.num_intf; + if (topology.cwb_enabled) + num_rt_intf--; + + if ((mode->hdisplay > (MAX_HDISPLAY_SPLIT * num_rt_intf)) || + ((u64)mode->hdisplay * mode->vtotal * drm_mode_vrefresh(mode) > + kms->perf.max_core_clk_rate)) + topology.num_lm =3D num_rt_intf * 2; else - topology.num_lm =3D 1; + topology.num_lm =3D num_rt_intf; + + if (!dpu_use_virtual_planes) + topology.num_lm =3D min(2, topology.num_lm); + + if (!dpu_kms->catalog->caps->has_3d_merge) + topology.num_lm =3D min(num_rt_intf, topology.num_lm); + + if (topology.num_dsc) { + if (num_rt_intf =3D=3D 1) + topology.num_lm =3D 2; + topology.num_dsc =3D topology.num_lm; + } =20 if (crtc_state->ctm || crtc_state->gamma_lut) topology.num_dspp =3D topology.num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 6eaba5696e8e6..455073c7025b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -210,7 +210,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -218,10 +218,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; =20 enum dpu_crtc_crc_source crc_source; int crc_frame_skip_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index eba1d52211f68..058a7c8727f7c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -55,7 +55,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 #define MAX_CWB_PER_ENC 2 =20 #define IDLE_SHORT_TIMEOUT 1 @@ -661,7 +661,6 @@ void dpu_encoder_update_topology(struct drm_encoder *dr= m_enc, struct dpu_encoder_virt *dpu_enc =3D to_dpu_encoder_virt(drm_enc); struct msm_drm_private *priv =3D dpu_enc->base.dev->dev_private; struct msm_display_info *disp_info =3D &dpu_enc->disp_info; - struct dpu_kms *dpu_kms =3D to_dpu_kms(priv->kms); struct drm_connector *connector; struct drm_connector_state *conn_state; struct drm_framebuffer *fb; @@ -675,22 +674,12 @@ void dpu_encoder_update_topology(struct drm_encoder *= drm_enc, =20 dsc =3D dpu_encoder_get_dsc_config(drm_enc); =20 - /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ - if (dsc) { - /* - * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces - * when Display Stream Compression (DSC) is enabled, - * and when enough DSC blocks are available. - * This is power-optimal and can drive up to (including) 4k - * screens. - */ - WARN(topology->num_intf > 2, - "DSC topology cannot support more than 2 interfaces\n"); - if (topology->num_intf >=3D 2 || dpu_kms->catalog->dsc_count >=3D 2) - topology->num_dsc =3D 2; - else - topology->num_dsc =3D 1; - } + /* + * Set DSC number as 1 to mark the enabled status, will be adjusted + * in dpu_crtc_get_topology() + */ + if (dsc) + topology->num_dsc =3D 1; =20 connector =3D drm_atomic_get_new_connector_for_encoder(state, drm_enc); if (!connector) @@ -2180,8 +2169,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) { int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 /* reset all mixers for this encoder */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 61b22d9494546..09395d7910ac8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers !=3D 1) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 70d5ed4732f2e..b93442f75c2eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,7 +24,7 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff =20 -#define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 046b683d4c66d..31451241f0839 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,7 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 -#define STAGES_PER_PLANE 1 +#define STAGES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE) #ifndef DPU_MAX_DE_CURVES --=20 2.43.0