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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-387068924c3sm13635831fa.1.2026.02.13.03.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 03:07:54 -0800 (PST) From: Marcus Folkesson Date: Fri, 13 Feb 2026 12:06:50 +0100 Subject: [PATCH v5 1/5] i2c: core: add callback to change bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-i2c-mux-v5-1-fb2cbf9979b3@gmail.com> References: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> In-Reply-To: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1616; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=eRPT6fwWSu39UFp184/6KNALMdSEu1tiZOm0jan9AEk=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpjwYAOcTbfDdGyuIUMkxx9uPWkK7ETY2/cJ3ME 4K7m74QleuJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaY8GAAAKCRCIgE5vWV1S MqLYD/9U0GGb/59bRkWRe3Vd9n15zS9gSWS6D5pjlLovgKJzfMpAwTJCt6jhJlISgg0/ZSZCOiJ kT6IvfdKCas38bNpTPq06XdOIlGuWYXocy4SMUmmurTDe2RDP3wY14o2cgbe+e8alLWml701cHE sea+iijidaNNBFldYucq0Oo4ItfjqyEKZ64cmtt1jbu6WNDa5VYT0DDiD4YwYP3yimIeo57gASN W6VZvh5T84OxXFDCKXvArAgqu9/Nmz4JGrpeXXhABd3dNzdinkIRv2wbxK1BEg+Dmki/FiggZUq wShfC0Hy+YGNfKAXKDpOSJPnoV/suh7EPUy3nefT9XClLty4JwETs+/8uCqe5j3mXXfFLBeWKkZ xAkNHu2V2JbjbNxPPZLlg9XZTvLdWekZRhVbXYi5ZTiiiUx1ohpSh8Qlp65clxA+hQVCutN9yQn dTio5Yf24T+8S/oj0VpQNZxT3wa9JYLhR400yXtW7MrRTFaV2SVMYCbAVtC/CwyG0EYaFI+wb42 2Y29s/Ls0SdmOvtadHSir0Wh4lZIQ197eNnrIJv6+jH7ulfberV6hREs5nStMGI7QUwxzVMtDee EnOUHuH37xGpsrdERAtAUT2JmTvLJnznqG4FwSVzKziv71l73MPvvcwg5PE8R7bYNH/Z2PscB4R Wq1P1dKs4WudEEQ== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 All devices on the same I2C bus share the same clock line and the bus frequency has therefor be chosen so that all attached devices are able to tolarate that clock rate. IOW, the bus speed must be set for the slowest attached device. With I2C multiplexers/switches on the other hand, it would be possible to have different "domains" that runs with different speeds. Prepare for such a feature by provide an optional callback function to change bus frequency. Signed-off-by: Marcus Folkesson --- include/linux/i2c.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 20fd41b51d5c..d147e388dbab 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -742,6 +742,8 @@ struct i2c_adapter { struct rt_mutex mux_lock; =20 int timeout; /* in jiffies */ + int clock_hz; + int (*set_clk_freq)(struct i2c_adapter *adap, u32 clock_hz); /* Optional = */ int retries; struct device dev; /* the adapter device */ unsigned long locked_flags; /* owned by the I2C core */ @@ -835,6 +837,17 @@ i2c_unlock_bus(struct i2c_adapter *adapter, unsigned i= nt flags) adapter->lock_ops->unlock_bus(adapter, flags); } =20 +static inline int +i2c_adapter_set_clk_freq(struct i2c_adapter *adapter, u32 clock_hz) +{ + int ret =3D -EOPNOTSUPP; + + if (adapter->set_clk_freq) + ret =3D adapter->set_clk_freq(adapter, clock_hz); + + return ret; +} + /** * i2c_mark_adapter_suspended - Report suspended state of the adapter to t= he core * @adap: Adapter to mark as suspended --=20 2.52.0 From nobody Fri Feb 13 17:30:51 2026 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FFDA354AE2 for ; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-387068924c3sm13635831fa.1.2026.02.13.03.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 03:07:55 -0800 (PST) From: Marcus Folkesson Date: Fri, 13 Feb 2026 12:06:51 +0100 Subject: [PATCH v5 2/5] i2c: mux: add support for per channel bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-i2c-mux-v5-2-fb2cbf9979b3@gmail.com> References: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> In-Reply-To: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8549; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=GAwGUaz+GqwpeQvnl1X7ahiwstVZRIvpf/1yMqLpIBk=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpjwYGuIK8exFqsvf3DBLtCgfwK6lnbHil0tXTZ Aas9o6VEqGJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaY8GBgAKCRCIgE5vWV1S Mg74EACm7dC1fqEhgRgE5JXfEyDwBbH77gywCuRIOdeyj9V9C82JIK4FmHsOKeSkiIbKk3es44d WG4C7U2KzJgAycihRJB5utVeK65J53nrnRvF4obR+Mae/LDkJRKnr/71hteNBx2og9T72plfmPp 1cTBBC/uK+vX2R27qaSZ6S1C6kHXvOQhANQTcuurY8trP2qangIPpFnsZXzrvyw0dGVEp5FUWcr rkEkJCrSeg4SdJzXFWIadFYpMehHfvCLYcB28OLFigOmMk2IKpH7+yWEoeoh49ss73/sBgEgJtj KprPDX/Gu9M+LeGbjs15MzsafBr/VwCrs+gAKPukbgV8sPlNU+GlaF13tHJmfJ2KKDhXQL5SDtu dW/SUpf9o4NMhBlI1U42CAP2BQuVeT2qjiqdAcqJiZ6KOjaHsOsEUH+8FzimBX5p392P14aAqY0 t2VZHTBmna+RAYLKTlUG4hvl/AGasxT9roOCS4AUKrJm1vRAkiUHa9GDM+buy9KgxggwHvgG9b+ fv7xDYjz2uTrPcpp6kpxScsF/ZFfMP0Xd0G93j1utlAJG7zBZQFT4gOXvaamwMxXZhlXpuajE7T Chefgjvqdvi6J4MtwXnYADgybTXPmDufSpmJoCnqrERkEXXtdo1wGE+4MiOeHvo455rOgfdz3/C 3rBSZQYm6fCuxkw== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 There may be several reasons why you may need to use a certain speed on an I2C bus. E.g. - When several devices are attached to the bus, the speed must be selected according to the slowest device. - Electrical conditions may limit the usuable speed on the bus for different reasons. With an I2C multiplexer, it is possible to group the attached devices after their preferred speed by e.g. put all "slow" devices on a separate channel on the multiplexer. Consider the following topology: .----------. 100kHz .--------. .--------. 400kHz | |--------| dev D1 | | root |--+-----| I2C MUX | '--------' '--------' | | |--. 400kHz .--------. | '----------' '-------| dev D2 | | .--------. '--------' '--| dev D3 | '--------' One requirement with this design is that a multiplexer may only use the same or lower bus speed as its parent. Otherwise, if the multiplexer would have to increase the bus frequency, then all siblings (D3 in this case) would run into a clock speed it may not support. The bus frequency for each channel is set in the devicetree. As the i2c-mux bindings import the i2c-controller schema, the clock-frequency property is already allowed. If no clock-frequency property is set, the channel inherit their parent bus speed. The following example uses dt bindings to illustrate the topology above: i2c { clock-frequency =3D <400000>; i2c-mux { i2c@0 { clock-frequency =3D <100000>; D1 { ... }; }; i2c@1 { D2 { ... }; }; }; D3 { ... } }; Signed-off-by: Marcus Folkesson --- drivers/i2c/i2c-mux.c | 145 +++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 133 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index d59644e50f14..9116ee3fd979 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -36,6 +36,100 @@ struct i2c_mux_priv { u32 chan_id; }; =20 +static struct i2c_mux_core *i2c_mux_topmost_mux_locked(struct i2c_adapter = *adap) +{ + struct i2c_adapter *curr =3D adap; + struct i2c_adapter *parent; + struct i2c_mux_core *result =3D NULL; + + do { + parent =3D i2c_parent_is_i2c_adapter(curr); + if (parent) { + struct i2c_mux_priv *priv =3D curr->algo_data; + + if (priv && priv->muxc && priv->muxc->mux_locked) + result =3D priv->muxc; + } + curr =3D parent; + } while (parent); + + return result; +} + +static int i2c_mux_select_chan(struct i2c_adapter *adap, u32 chan_id) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + struct i2c_mux_core *mux_locked_ancestor =3D NULL; + struct i2c_adapter *root; + int ret; + + if (priv->adap.clock_hz && priv->adap.clock_hz !=3D parent->clock_hz) { + mux_locked_ancestor =3D i2c_mux_topmost_mux_locked(adap); + root =3D i2c_root_adapter(&adap->dev); + + /* + * If there's a mux-locked mux in our ancestry, lock the parent + * of the topmost one. Mux-locked muxes don't propagate locking + * to their parents, so we must explicitly acquire the lock above + * the highest mux-locked ancestor to reach the root adapter. + */ + if (mux_locked_ancestor) + i2c_lock_bus(mux_locked_ancestor->parent, I2C_LOCK_ROOT_ADAPTER); + + ret =3D i2c_adapter_set_clk_freq(root, priv->adap.clock_hz); + + if (mux_locked_ancestor) + i2c_unlock_bus(mux_locked_ancestor->parent, I2C_LOCK_ROOT_ADAPTER); + + if (ret < 0) { + dev_err(&adap->dev, + "Failed to set clock frequency %dHz on root adapter %s: %d\n", + priv->adap.clock_hz, root->name, ret); + + return ret; + } + } + + return muxc->select(muxc, priv->chan_id); +} + +static void i2c_mux_deselect_chan(struct i2c_adapter *adap, u32 chan_id) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + struct i2c_mux_core *mux_locked_ancestor =3D NULL; + struct i2c_adapter *root; + int ret; + + if (parent->clock_hz && parent->clock_hz !=3D priv->adap.clock_hz) { + mux_locked_ancestor =3D i2c_mux_topmost_mux_locked(adap); + root =3D i2c_root_adapter(&parent->dev); + + /* + * If there's a mux-locked mux in our ancestry, lock the parent + * of the topmost one. Mux-locked muxes don't propagate locking + * to their parents, so we must explicitly acquire the lock above + * the highest mux-locked ancestor to reach the root adapter. + */ + if (mux_locked_ancestor) + i2c_lock_bus(mux_locked_ancestor->parent, I2C_LOCK_ROOT_ADAPTER); + + ret =3D i2c_adapter_set_clk_freq(root, parent->clock_hz); + + if (mux_locked_ancestor) + i2c_unlock_bus(mux_locked_ancestor->parent, I2C_LOCK_ROOT_ADAPTER); + + if (ret < 0) + return; + } + + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); +} + static int __i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { @@ -46,11 +140,11 @@ static int __i2c_mux_master_xfer(struct i2c_adapter *a= dap, =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D __i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -65,11 +159,11 @@ static int i2c_mux_master_xfer(struct i2c_adapter *ada= p, =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -86,12 +180,12 @@ static int __i2c_mux_smbus_xfer(struct i2c_adapter *ad= ap, =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D __i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -108,12 +202,12 @@ static int i2c_mux_smbus_xfer(struct i2c_adapter *ada= p, =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -223,6 +317,7 @@ struct i2c_adapter *i2c_root_adapter(struct device *dev) } EXPORT_SYMBOL_GPL(i2c_root_adapter); =20 + struct i2c_mux_core *i2c_mux_alloc(struct i2c_adapter *parent, struct device *dev, int max_adapters, int sizeof_priv, u32 flags, @@ -362,6 +457,32 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, } } =20 + of_property_read_u32(child, "clock-frequency", &priv->adap.clock_hz); + + /* If the mux adapter has no clock-frequency property, inherit from pare= nt */ + if (!priv->adap.clock_hz) + priv->adap.clock_hz =3D parent->clock_hz; + + /* + * Warn if the mux adapter is not parent-locked as + * this may cause issues for some hardware topologies. + */ + if ((priv->adap.clock_hz < parent->clock_hz) && muxc->mux_locked) + dev_warn(muxc->dev, + "channel %u is slower than parent on a non parent-locked mux\n", + chan_id); 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-387068924c3sm13635831fa.1.2026.02.13.03.07.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 03:07:57 -0800 (PST) From: Marcus Folkesson Date: Fri, 13 Feb 2026 12:06:52 +0100 Subject: [PATCH v5 3/5] i2c: davinci: calculate bus freq from Hz instead of kHz Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-i2c-mux-v5-3-fb2cbf9979b3@gmail.com> References: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> In-Reply-To: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2849; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=NgWDqx3izSY9aW9W75gFytkLHJndTcTMdemaHAZbfa4=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpjwYL/mBgptLRECM6Xhb4gqTFs3FQSjGviRzOv JLmo5EhXpSJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaY8GCwAKCRCIgE5vWV1S MvCZD/9WMtRGpgF1nsGmzHotYBXEo3UiFoeK7+Nu+zc50fy5TcIUV8PLiDl9zLOnr/WKONF/c72 FYdeNB+ufxhjtKxNGOIoqlw+xkIR5HtF1iehNbmPanpjW69FJ45g9dWU8iq491iNx6zyDvINhN3 AuuhvYJmDzuLsnwgAPMALlDA7WskPKu3uigAhraJNLUb8zbtrZBHzWgY8QVF+70RWB7JjWvrvNX zB9eFtd6uA5iowL74VBvk4cJgknFWoo76C2jgFKNawr1E+mOQjHxp5KKcoM+2JtNINsk3R4wjoq xPN3TwGPNJO9bA6tS19h9fnEFLJLO+xyXB6GTnEBWo36z7mG5pssbevtsI+kN+na8+H+9+RY0cd PxOFsJyIBrcb0XHZ9EV68dZC0LQl7DulfGCLh6hiTn+DwiFn0KH9bNoTk3qbsTQWP/i2hihMyxD YV2SbP8oC56SwxAb7hQzx4vpit/Cs7aKxdbGU47uYS9wSkt/DgRpFQld5yhMqbsth2fDte6fRFL Y1uo4i70kLXeyP6aUK8w8SH30CO3kmPh3bMdVF6TzMO9MUnYKnmTV9r6W2p1EBW07uB9mLWRf8V AzfMPFwJ7l3r5OSOe2FoSOOCe//DzfmZmeMgf90tDRh9jynzenWcEv2iVArE2khhRIvdwa9kLDc OF7wPgFWNaWbBzg== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 The bus frequency is unnecessarily converted between Hz and kHz in several places. This is probably an old legacy from the old times (pre-devicetrees) when the davinci_i2c_platform_data took the bus_freq in kHz. Stick to Hz. Reviewed-by: Bartosz Golaszewski Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index a773ba082321..761de5a814df 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -117,8 +117,6 @@ /* timeout for pm runtime autosuspend */ #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ =20 -#define DAVINCI_I2C_DEFAULT_BUS_FREQ 100 - struct davinci_i2c_dev { struct device *dev; void __iomem *base; @@ -134,8 +132,8 @@ struct davinci_i2c_dev { #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; #endif - /* standard bus frequency (kHz) */ - unsigned int bus_freq; + /* standard bus frequency */ + unsigned int bus_freq_hz; /* Chip has a ICPFUNC register */ bool has_pfunc; }; @@ -209,16 +207,16 @@ static void i2c_davinci_calc_clk_dividers(struct davi= nci_i2c_dev *dev) if (device_is_compatible(dev->dev, "ti,keystone-i2c")) d =3D 6; =20 - clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); + clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq_hz)); /* Avoid driving the bus too fast because of rounding errors above */ - if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) + if (input_clock / (psc + 1) / clk > dev->bus_freq_hz) clk++; /* * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at * least 1.3uS, which is not the case with 50% duty cycle. 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Acked-by: Bartosz Golaszewski Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index 761de5a814df..3daa823dcb9e 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -279,6 +279,27 @@ static int i2c_davinci_init(struct davinci_i2c_dev *de= v) return 0; } =20 +static int davinci_i2c_set_clk(struct i2c_adapter *adap, u32 clock_hz) +{ + struct davinci_i2c_dev *dev =3D i2c_get_adapdata(adap); + + if (dev->bus_freq_hz =3D=3D clock_hz) + return 0; + + dev->bus_freq_hz =3D clock_hz; + + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); + + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); + + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); + + return 0; +} + /* * This routine does i2c bus recovery by using i2c_generic_scl_recovery * which is provided by I2C Bus recovery infrastructure. @@ -809,6 +830,8 @@ static int davinci_i2c_probe(struct platform_device *pd= ev) adap->dev.parent =3D &pdev->dev; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-387068924c3sm13635831fa.1.2026.02.13.03.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 03:08:01 -0800 (PST) From: Marcus Folkesson Date: Fri, 13 Feb 2026 12:06:54 +0100 Subject: [PATCH v5 5/5] docs: i2c: i2c-topology: add section about bus speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-i2c-mux-v5-5-fb2cbf9979b3@gmail.com> References: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> In-Reply-To: <20260213-i2c-mux-v5-0-fb2cbf9979b3@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8159; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=G8r8z7mFndx6RhNUdA+WKfKocioUhRmN3d9RveqxuFs=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpjwYULntuXqppCKAp6MHQLjAs03e3JoMx/lAL1 tbwKPGiJwyJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaY8GFAAKCRCIgE5vWV1S MpsND/4kSp3FQNG2wRur+bl+h5XFJUP4SFef4onkUAsftA/Z4zisGI5ysGEOpwFB86rerq5Hc34 rjeoM6nfEDWOLlRvwraAl1NeeuN7Z1XbwEOWYpp+aF+QUC4y8F0xqAcgsdljehfBOKkpdLh8mpQ lVBwoUWN6dFozHJZk+Ry9qY3f47n6A7MDGrgWW57xuxnGz2/617YRfgmcllA2u8Af4Ln32V65JM wvBOgUm0lnUJWln2xjIycdxHLRGGCcKv97MzChmtPFjFKoX5sFjfkTuXKT1/Zxb2ejFExtChQH5 UxVppsMYDiOI8nQ+DxmYejfRcL9ACM2dQDlvx28WxHEZCv7PL33Ve33hXIfR+75eOIXLzFIYwMg z5LQLVQTeDlFSGpDGsRJ2yZNhurziRy/0u6LN3x2TKri3U2j6TUXjSLrOhVuS4aAIiwkzmq4uN7 SdGZwI4hpsKXvnCC+RNi3x8XkVoUP+DWe3wKK6ZUNhrqBEC5jO5fn2lyipL1pGM+IKacKBEd9eA N4NhOMgKHwPEDVnT3SLUDIdpYHPyaqL5ZLkBcttD0YNXgHXjymo9hRLwMFuNLDlt91kVr4cgQCP M2mGFO+g16ANe5RThYamHGhfFx3M9RMh0bJqcmy00jlZBo5yRKx/8mDzDmvIojkWIo7tr+7aKXr Nl2YZh8LYcPQb/Q== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Describe what needs to be consideraed and taken into account when using different bus speeds for different mux channels. Signed-off-by: Marcus Folkesson --- Documentation/i2c/i2c-topology.rst | 176 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 176 insertions(+) diff --git a/Documentation/i2c/i2c-topology.rst b/Documentation/i2c/i2c-top= ology.rst index 48fce0f7491b..2c4a1364ce82 100644 --- a/Documentation/i2c/i2c-topology.rst +++ b/Documentation/i2c/i2c-topology.rst @@ -367,6 +367,182 @@ When D1 or D2 are accessed, accesses to D3 and D4 are= locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out. =20 +Bus Speed and I2C Multiplexers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +I2C bus multiplexers allows multiple downstream channels to be exposed +as separate I2C adapters which also could set their own bus speed. + +The multiplexer itself cannot change the bus speed as it use the upstream +clock and data lines to communicate with the downstream devices. The speed +is therfor changed in the root adapter resulting in that the whole bus is +affected. + +This increases the complexity of the topology and some considerations must +be taken into. + +Bus speed +---------- + +Downstream channels of an I2C multiplexer can only operate at the same or +lower bus speed as the upstream bus. This is because the upstream bus may +have devices that cannot operate at higher speeds and those will be affect= ed +by the speed change. + +The example below illustrates the problem. +The root adapter is operating at 100kHz. D2 can only operate with 100kHz, +but D2 can operate at 400kHz. When D1 is selected, the bus speed of the +root adapter would have to be is set to 400kHz, a speed that D2 may not su= pport. + +This topology is therefor not allowed: :: + + .----------. 400kHz .--------. + .--------. 100kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 | + | '----------' + | .--------. + '--| dev D2 | + '--------' + + +This topology is allowed: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Preferred topology +------------------- + +The preferred topology when using different bus speeds is to have the mult= iplexer +connected directly to the root adapter without any devices as siblings. +By this arrangement, the bus speed can be changed without affecting any ot= her devices +and many of the caveats are avoided. + +Other multiplexers in parallell is still okay as those are locked out duri= ng transfers. + +This is the preferred topology: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' +Locking +-------- + +If the multiplexer is mux-locked, transfers to D3 may interleave between t= he +select-transfer-deselect to D1 or D2. +This results in a situation where the bus speed to D3 may be lower than it +is supposed to be. This is usually not a problem. + +This topology is allowed but some transfers to D3 may be at 100kHz: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +Multiple muxes in series +-------------------------- + +When multiple muxes are used in series the same rules applies. + +Transfers to D3 may interleave between select-transfer-deselect to D1, whi= ch +results that the bus speed to D2 or D3 will be at 100KHz. + +Transfers to D2 may interleave between select-transfer-deselect to D1, whi= ch +results in that the bus speed to D1 may be at 400kHz as the transfer to D2 +will set the bus speed to before the transfer to D1 starts. + +This is probably a bad topology :: + + .----------. 400kHz .----------. 100kHz .--------. + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | + | root |--+----| locked | 400kHz | locked | '--------' + '--------' | | mux M1 |--. | mux M2 | + | '----------' | '----------' + | .--------. | .--------. + '--| dev D3 | '--| dev D2 | + '--------' '--------' + +Multiple muxes in parallell +---------------------------- + +When multiple muxes are used in parallell all access to other muxes are lo= cked out +so this is not a problem. + +If the muxes are mux-locked, access to D3 may still interleave though. + +In the example below, D3 may not interleave between select-transfer-desele= ct for D1 +or D2 as both muxes are parent-locked: :: + + + .----------. 100kHz .--------. + | parent- |----------| dev D1 | + .--| locked | '--------' + | | mux M1 | + | '----------' + | .----------. 400KHz .--------. + .--------. 400kHz | parent- |---------| dev D2 | + | root |--+------| locked | '--------' + '--------' | | mux M2 | + | '----------' + | .--------. + '--| dev D3 | + '--------' + +Idle state +----------- + +Muxes have an idle state, which is the state the channels is put into when= no channel +is active. The state is typically one of the following: + +- All channels are disconnected +- The last selected channel is left as-is +- A predefined channel is selected + +Muxes that support an idle state where all channels are disconnected are p= referred when using +different bus speeds. Otherwise high bus speeds may "leak" through to devi= ces that +may not support that higher speed. + +Consider the following example: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +If the idle state of M1 is: +- All channels disconnected: No problem, D1 and D2 are not affected by com= munication + to D3. +- Last selected channel: Problem if D1 was the last selected channel. High= speed + communication to D3 will be "leaked" to D1. +- Predefined channel: Problem, if the predefined channel D1. Set predefine= d channel + to D2 as D2 may handle 400kHz. + +Supported controllers +----------------------- + +Not all I2C controllers support setting the bus speed dynamically. +At the time of writint, the following controllers has support: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +i2c-davinci Supports dynamic bus speed +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Mux type of existing device drivers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.52.0