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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cb2b0bda6fsm541156485a.9.2026.02.12.23.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Feb 2026 23:31:51 -0800 (PST) From: Yongxing Mou Date: Fri, 13 Feb 2026 15:31:42 +0800 Subject: [PATCH v2 1/2] phy: qcom: edp: Add eDP/DP mode switch support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260213-edp_phy-v2-1-43c40976435e@oss.qualcomm.com> References: <20260213-edp_phy-v2-0-43c40976435e@oss.qualcomm.com> In-Reply-To: <20260213-edp_phy-v2-0-43c40976435e@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Yongxing Mou , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770967906; l=8385; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=MMBXeitiZuY878Tcd7dZwXtn6YzjgtXAK6zo5LiGnbg=; b=qbTjOlraNg+3CjGW1D9kjHriy/TcD7Anng0ItMYgX6qqV0xIbxb5F3a2e6GNUYzm0SCuunh5p 2dLRHweALrtBjiKlr3EOrE2pU0+suCf7t8lvH8vk9aVzxNyNIezgtN3 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEzMDA1NyBTYWx0ZWRfX5Pz+58EJXDNN zjpDDhLUnnZ3BgKfGIblOZMURCgjTrBEBiv+dmEBtR1DnQIAacj8+NN5dTvsW93gEy6HQOEHjOC I7I8zzD70KcdhB+rdh1hmLxE2x/i2jVa3x0/v5W6e792o/flfc1NEHNh8h+dmrgNea3aVm8uQui W1ikYmgtx5DsPOIKkyx6cEZmBI8d2I7QQzelp+rC+QWqWDjbdNYUZffL6sG5CUx1xbUI+ILjxDw Z0y03Zpx0YZlEBZRyhKH5+i5GpzQOv/pzJP7N46cGol7PlXipKiBrDLrvO1Vm99TowXNe7y2MYZ uxUT1QWoHm3X8O4vXZJ8dMs0WAAjwBdKlT8PppFNET+zXsSBWekj03Upkxkm94E9qSsxXfpvikF PaSl77rntWlDw6Pik7hCLmkIt5keshNN0jOF9OumL+QBfh1WGDRV6nymp8S3m8quzTZ3d94erq/ CyfXyuqMVkQMa0nRUyg== X-Proofpoint-ORIG-GUID: OHNmKOAqVWu_pZ5dRRZjrbIddhcNlZwS X-Authority-Analysis: v=2.4 cv=asC/yCZV c=1 sm=1 tr=0 ts=698ed369 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fAMMRUVWeN1gI5VMqOgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: OHNmKOAqVWu_pZ5dRRZjrbIddhcNlZwS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-13_01,2026-02-12_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602130057 The eDP PHY supports both eDP&DP modes, each requires a different table. The current driver doesn't fully support every combo PHY mode and use either the eDP or DP table when enable the platform. In addition, some platforms mismatch between the mode and the table where DP mode uses the eDP table or eDP mode use the DP table. Clean up and correct the tables for currently supported platforms based on the HPG specification. Here lists the tables can be reused across current platforms. DP mode=EF=BC=9A -sa8775p/sc7280/sc8280xp/x1e80100 -glymur eDP mode(low vdiff): -glymur/sa8775p/sc8280xp/x1e80100 -sc7280 Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by: Yongxing Mou --- drivers/phy/qualcomm/phy-qcom-edp.c | 90 ++++++++++++++++++++++-----------= ---- 1 file changed, 53 insertions(+), 37 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 13feab99feec..ff14de41cb1c 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -87,7 +87,8 @@ struct qcom_edp_phy_cfg { bool is_edp; const u8 *aux_cfg; const u8 *vco_div_cfg; - const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; + const struct qcom_edp_swing_pre_emph_cfg *dp_swing_pre_emph_cfg; + const struct qcom_edp_swing_pre_emph_cfg *edp_swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; =20 @@ -116,17 +117,17 @@ struct qcom_edp { }; =20 static const u8 dp_swing_hbr_rbr[4][4] =3D { - { 0x08, 0x0f, 0x16, 0x1f }, + { 0x07, 0x0f, 0x16, 0x1f }, { 0x11, 0x1e, 0x1f, 0xff }, { 0x16, 0x1f, 0xff, 0xff }, { 0x1f, 0xff, 0xff, 0xff } }; =20 static const u8 dp_pre_emp_hbr_rbr[4][4] =3D { - { 0x00, 0x0d, 0x14, 0x1a }, + { 0x00, 0x0e, 0x15, 0x1a }, { 0x00, 0x0e, 0x15, 0xff }, { 0x00, 0x0e, 0xff, 0xff }, - { 0x03, 0xff, 0xff, 0xff } + { 0x04, 0xff, 0xff, 0xff } }; =20 static const u8 dp_swing_hbr2_hbr3[4][4] =3D { @@ -150,6 +151,20 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy= _swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, }; =20 +static const u8 dp_pre_emp_hbr_rbr_v8[4][4] =3D { + { 0x00, 0x0e, 0x15, 0x1a }, + { 0x00, 0x0e, 0x15, 0xff }, + { 0x00, 0x0e, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_= v8 =3D { + .swing_hbr_rbr =3D &dp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &dp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr =3D &dp_pre_emp_hbr_rbr_v8, + .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, +}; + static const u8 edp_swing_hbr_rbr[4][4] =3D { { 0x07, 0x0f, 0x16, 0x1f }, { 0x0d, 0x16, 0x1e, 0xff }, @@ -158,7 +173,7 @@ static const u8 edp_swing_hbr_rbr[4][4] =3D { }; =20 static const u8 edp_pre_emp_hbr_rbr[4][4] =3D { - { 0x05, 0x12, 0x17, 0x1d }, + { 0x05, 0x11, 0x17, 0x1d }, { 0x05, 0x11, 0x18, 0xff }, { 0x06, 0x11, 0xff, 0xff }, { 0x00, 0xff, 0xff, 0xff } @@ -172,10 +187,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] =3D { }; =20 static const u8 edp_pre_emp_hbr2_hbr3[4][4] =3D { - { 0x08, 0x11, 0x17, 0x1b }, - { 0x00, 0x0c, 0x13, 0xff }, - { 0x05, 0x10, 0xff, 0xff }, - { 0x00, 0xff, 0xff, 0xff } + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x0b, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } }; =20 static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= =3D { @@ -193,25 +208,25 @@ static const u8 edp_phy_vco_div_cfg_v4[4] =3D { 0x01, 0x01, 0x02, 0x00, }; =20 -static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { - { 0x05, 0x11, 0x17, 0x1d }, - { 0x05, 0x11, 0x18, 0xff }, - { 0x06, 0x11, 0xff, 0xff }, - { 0x00, 0xff, 0xff, 0xff } +static const u8 edp_swing_hbr2_hbr3_v3[4][4] =3D { + { 0x06, 0x11, 0x16, 0x1b }, + { 0x0b, 0x19, 0x1f, 0xff }, + { 0x18, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } }; =20 -static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] =3D { +static const u8 edp_pre_emp_hbr2_hbr3_v3[4][4] =3D { { 0x0c, 0x15, 0x19, 0x1e }, - { 0x0b, 0x15, 0x19, 0xff }, - { 0x0e, 0x14, 0xff, 0xff }, + { 0x09, 0x14, 0x19, 0xff }, + { 0x0f, 0x14, 0xff, 0xff }, { 0x0d, 0xff, 0xff, 0xff } }; =20 -static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v5 =3D { +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v3 =3D { .swing_hbr_rbr =3D &edp_swing_hbr_rbr, - .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, - .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr_v5, - .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v5, + .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3_v3, + .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v3, }; =20 static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] =3D { @@ -262,12 +277,7 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - /* - * TODO: Re-work the conditions around setting the cfg8 value - * when more information becomes available about why this is - * even needed. - */ - if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) + if (!edp->is_edp) aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); @@ -291,7 +301,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_co= nfigure_opts_dp *dp_opts) { - const struct qcom_edp_swing_pre_emph_cfg *cfg =3D edp->cfg->swing_pre_emp= h_cfg; + const struct qcom_edp_swing_pre_emph_cfg *cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; u8 ldo_config; @@ -299,11 +309,10 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp= , const struct phy_configur u8 emph; int i; =20 - if (!cfg) - return 0; - if (edp->is_edp) - cfg =3D &edp_phy_swing_pre_emph_cfg; + cfg =3D edp->cfg->edp_swing_pre_emph_cfg; + else + cfg =3D edp->cfg->dp_swing_pre_emph_cfg; =20 for (i =3D 0; i < dp_opts->lanes; i++) { v_level =3D max(v_level, dp_opts->voltage[i]); @@ -564,20 +573,24 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_c= fg =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v3, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -585,7 +598,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_c= fg =3D { .is_edp =3D true, .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -765,7 +779,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D= { static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; =20 @@ -944,7 +959,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D= { static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v8, .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg_v8, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v8, }; =20 --=20 2.43.0