From nobody Thu Apr 2 21:58:56 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4430C2F260E; Thu, 12 Feb 2026 23:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770939060; cv=none; b=IYHsSgQu0hutPpAJrB71AGPZmLLih50TxgjjNI34mwDJvIbSvz7dmRnRoIF1FSXCGVDZ6vf8VPzIw9aDTgDV1TQnwCrPFWWFGpTUDkJAE5OGw13MGdNbYy47n2f4OY3Naz3pQFAUzK/LoQkhayhxENIzXLvA+tLbob4+JMiWkDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770939060; c=relaxed/simple; bh=ICHQ3RgooLOUl9W7kvF4fjTrAsEJ2DDM+UnC77xozl8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HByyopco6BVNxcgb8G/x4E79AAGBX1S+EkOd5Q6wyY8ewADhP9SY/xASbY80X2riVxD2Mx1KBnKpqFq/T7pj0Taped02422/NwAy9bb7rvjx20gwVWghn0EAAQ5/Bl0yUdaGdU6NgpcdQPb3BSySnl2ahWifn0Rrrys9z+Ep77o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZL1AqXX1; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZL1AqXX1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770939053; x=1802475053; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ICHQ3RgooLOUl9W7kvF4fjTrAsEJ2DDM+UnC77xozl8=; b=ZL1AqXX1SJys4USghd/o4bcxyuVkEvMKe/4jS2EuyXOHWfOJdb4q2Dou mpF83gC7eoFzD6n8kWBS7Ke61vBE1ptsX6BY6WhxfB5kMI/D7G1FHPElE nJ/1cYsSX9jYpSndHgldeVHL4qQ1Hj3ZPj34lwnFS/5crQzigi72zs07O EsSBuM9Kbf0XMboXkw29Z48lrnpX6fJhyv/u+fD/5qEF0zGWJJXdKHExb b7BP2uCMPMtsBWRb0FqFX0+url6Q1vNkhm0mScYmhjHpQB5faDo0eM8Ws 8/Viml45/e71q86pISEcyoPbMWfCTiwdSRlz6r5kIlOobyZtehR0rZEpe Q==; X-CSE-ConnectionGUID: rsfiPgTOTj2i5t3hmBM9iw== X-CSE-MsgGUID: Aeq/iZetThG4meX0kT+OYw== X-IronPort-AV: E=McAfee;i="6800,10657,11699"; a="72017440" X-IronPort-AV: E=Sophos;i="6.21,287,1763452800"; d="scan'208";a="72017440" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2026 15:30:49 -0800 X-CSE-ConnectionGUID: wklTk432R96FTQMhZx1VdQ== X-CSE-MsgGUID: Yv8h9MOcQ0KBgnltG7HOig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,287,1763452800"; d="scan'208";a="211845402" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2026 15:30:46 -0800 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/12] powercap: intel_rapl: Use GENMASK() and BIT() macros Date: Thu, 12 Feb 2026 15:30:38 -0800 Message-ID: <20260212233044.329790-7-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260212233044.329790-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260212233044.329790-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace hardcoded bitmasks and bit shift operations with standard GENMASK(), GENMASK_ULL(), BIT(), and BIT_ULL() macros for better readability and to follow kernel coding conventions. No functional changes. Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 60 ++++++++++++++-------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 819eab3988da..aa505e2ebc94 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -31,62 +31,62 @@ #include =20 /* bitmasks for RAPL MSRs, used by primitive access functions */ -#define ENERGY_STATUS_MASK 0xffffffff +#define ENERGY_STATUS_MASK GENMASK(31, 0) =20 -#define POWER_LIMIT1_MASK 0x7FFF +#define POWER_LIMIT1_MASK GENMASK(14, 0) #define POWER_LIMIT1_ENABLE BIT(15) #define POWER_LIMIT1_CLAMP BIT(16) =20 -#define POWER_LIMIT2_MASK (0x7FFFULL<<32) +#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32) #define POWER_LIMIT2_ENABLE BIT_ULL(47) #define POWER_LIMIT2_CLAMP BIT_ULL(48) #define POWER_HIGH_LOCK BIT_ULL(63) #define POWER_LOW_LOCK BIT(31) =20 -#define POWER_LIMIT4_MASK 0x1FFF +#define POWER_LIMIT4_MASK GENMASK(12, 0) =20 -#define TIME_WINDOW1_MASK (0x7FULL<<17) -#define TIME_WINDOW2_MASK (0x7FULL<<49) +#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17) +#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49) =20 #define POWER_UNIT_OFFSET 0x00 -#define POWER_UNIT_MASK 0x0F +#define POWER_UNIT_MASK GENMASK(3, 0) =20 #define ENERGY_UNIT_OFFSET 0x08 -#define ENERGY_UNIT_MASK 0x1F00 +#define ENERGY_UNIT_MASK GENMASK(12, 8) =20 #define TIME_UNIT_OFFSET 0x10 -#define TIME_UNIT_MASK 0xF0000 +#define TIME_UNIT_MASK GENMASK(19, 16) =20 -#define POWER_INFO_MAX_MASK (0x7fffULL<<32) -#define POWER_INFO_MIN_MASK (0x7fffULL<<16) -#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) -#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff +#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) +#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) +#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) +#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) =20 -#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff -#define PP_POLICY_MASK 0x1F +#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) +#define PP_POLICY_MASK GENMASK(4, 0) =20 /* * SPR has different layout for Psys Domain PowerLimit registers. * There are 17 bits of PL1 and PL2 instead of 15 bits. * The Enable bits and TimeWindow bits are also shifted as a result. */ -#define PSYS_POWER_LIMIT1_MASK 0x1FFFF +#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0) #define PSYS_POWER_LIMIT1_ENABLE BIT(17) =20 -#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32) +#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32) #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) =20 -#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19) -#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51) +#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) +#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) =20 /* bitmasks for RAPL TPMI, used by primitive access functions */ -#define TPMI_POWER_LIMIT_MASK 0x3FFFF +#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0) #define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) -#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18) -#define TPMI_INFO_SPEC_MASK 0x3FFFF -#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18) -#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36) -#define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54) +#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18) +#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0) +#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18) +#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36) +#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) =20 /* Non HW constants */ #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ @@ -111,9 +111,9 @@ #define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET #define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK #define TPMI_ENERGY_UNIT_OFFSET 0x06 -#define TPMI_ENERGY_UNIT_MASK 0x7C0 +#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6) #define TPMI_TIME_UNIT_OFFSET 0x0C -#define TPMI_TIME_UNIT_MASK 0xF000 +#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12) =20 #define RAPL_EVENT_MASK GENMASK(7, 0) =20 @@ -1102,8 +1102,8 @@ static void set_floor_freq_atom(struct rapl_domain *r= d, bool enable) &power_ctrl_orig_val); mdata =3D power_ctrl_orig_val; if (enable) { - mdata &=3D ~(0x7f << 8); - mdata |=3D 1 << 8; + mdata &=3D ~GENMASK(14, 8); + mdata |=3D BIT(8); } iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, defaults->floor_freq_reg_addr, mdata); @@ -1136,7 +1136,7 @@ static u64 rapl_compute_time_window_core(struct rapl_= domain *rd, u64 value, if (y > 0x1f) return 0x7f; =20 - f =3D div64_u64(4 * (value - (1ULL << y)), 1ULL << y); + f =3D div64_u64(4 * (value - BIT_ULL(y)), BIT_ULL(y)); value =3D (y & 0x1f) | ((f & 0x3) << 5); } return value; --=20 2.43.0