From nobody Thu Apr 2 06:28:40 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AB3D28DB54; Thu, 12 Feb 2026 10:45:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893110; cv=none; b=qMFwrX0oq3aj0tgfh++CrJsF0keqzz+kK4jcP8hHheuebUUT+vZFLlgY3rDVrVcha6+rt2HB/rBVjJHdF0rGtw4clBrzc+tKRcpc2K2BgbiQ2LUaaOSWxKpj2W9Wbk5IlKaoXLfWVSKS2fNEipQmKG8SO/jtAlrofM8QzzbPui8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893110; c=relaxed/simple; bh=q9FkRkt9XTtnYFNQYulC4RjiWoYQrI+55cT2OIRD+ow=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BAAAv1xvksRI/fW/G3k7RukvzekM3h2ZqgDxpO4YtAnM38vLnYIHcn+2gYWzFLFzJatc/tZmobd/+GyOSa3USD6fDiJ/fEo+HeYJXEwLQ0xF9Z8C+y666BWhyGE1D7MXg8dgS+jmv0DOdB1vDX0p7ZpFWh/RJbnsPTrroRsnqmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ZYglXK1R; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ZYglXK1R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=Io 7wlVzfMw58uZVcDRMHjuLTKFMhqga3Ka5BB7KcPEU=; b=ZYglXK1RN0i2cTtoej pu05eYjndRabtlVxf4g19G/vcc0wzwNtieRMDvKBAsKrgaCode9RhtqpLe0Sj+By 8TXCw8mTMhg8XZ2vC0ptFChPLQI5opzpRq4k9S1q0pDxeQcJGzs6GD95Db69iVuR XGR/Wo+/Jsh1UcwGrQLPkO6Po= Received: from 163.com (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wA38f4Tr41pL2eqLA--.10527S3; Thu, 12 Feb 2026 18:44:39 +0800 (CST) From: Zhiquan Li To: seanjc@google.com, pbonzini@redhat.com, shuah@kernel.org Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, zhiquan_li@163.com Subject: [PATCH v2 1/4] KVM: x86: selftests: Add CPU vendor detection for Hygon Date: Thu, 12 Feb 2026 18:38:38 +0800 Message-ID: <20260212103841.171459-2-zhiquan_li@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260212103841.171459-1-zhiquan_li@163.com> References: <20260212103841.171459-1-zhiquan_li@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wA38f4Tr41pL2eqLA--.10527S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxWFW5Zw48Zr17KF17Cr17Wrg_yoW5Jw45pF ykAr1rKF10gFnrta4xXr4ktry8XrZ7Wa1Iq34DXry3Aa12yry7Xrs7Ka4jvrZI9FWrW3s8 Za4xtF4YgFsrZaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pi1rWUUUUUU= X-CM-SenderInfo: 52kl13xdqbzxi6rwjhhfrp/xtbC6Reul2mNrxfYOAAA37 Content-Type: text/plain; charset="utf-8" Currently some KVM selftests are failed on Hygon CPUs due to missing vendor detection and edge-case handling specific to Hygon's architecture. Add CPU vendor detection for Hygon and add a global variable "host_cpu_is_hygon" as the basic facility for the following fixes. Signed-off-by: Zhiquan Li --- tools/testing/selftests/kvm/include/x86/processor.h | 6 ++++++ tools/testing/selftests/kvm/lib/x86/processor.c | 3 +++ 2 files changed, 9 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 4ebae4269e68..1338de7111e7 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -21,6 +21,7 @@ =20 extern bool host_cpu_is_intel; extern bool host_cpu_is_amd; +extern bool host_cpu_is_hygon; extern uint64_t guest_tsc_khz; =20 #ifndef MAX_NR_CPUID_ENTRIES @@ -694,6 +695,11 @@ static inline bool this_cpu_is_amd(void) return this_cpu_vendor_string_is("AuthenticAMD"); } =20 +static inline bool this_cpu_is_hygon(void) +{ + return this_cpu_vendor_string_is("HygonGenuine"); +} + static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, uint8_t reg, uint8_t lo, uint8_t hi) { diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testin= g/selftests/kvm/lib/x86/processor.c index fab18e9be66c..f6b1c5324931 100644 --- a/tools/testing/selftests/kvm/lib/x86/processor.c +++ b/tools/testing/selftests/kvm/lib/x86/processor.c @@ -23,6 +23,7 @@ vm_vaddr_t exception_handlers; bool host_cpu_is_amd; bool host_cpu_is_intel; +bool host_cpu_is_hygon; bool is_forced_emulation_enabled; uint64_t guest_tsc_khz; =20 @@ -792,6 +793,7 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigne= d int nr_vcpus) =20 sync_global_to_guest(vm, host_cpu_is_intel); sync_global_to_guest(vm, host_cpu_is_amd); + sync_global_to_guest(vm, host_cpu_is_hygon); sync_global_to_guest(vm, is_forced_emulation_enabled); sync_global_to_guest(vm, pmu_errata_mask); =20 @@ -1424,6 +1426,7 @@ void kvm_selftest_arch_init(void) { host_cpu_is_intel =3D this_cpu_is_intel(); host_cpu_is_amd =3D this_cpu_is_amd(); + host_cpu_is_hygon =3D this_cpu_is_hygon(); is_forced_emulation_enabled =3D kvm_is_forced_emulation_enabled(); =20 kvm_init_pmu_errata(); --=20 2.43.0 From nobody Thu Apr 2 06:28:40 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B55927FD6D; Thu, 12 Feb 2026 10:45:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893114; cv=none; b=HPXDkEKbEpqqRQGlKxsmhndEXBmLMGTdnr1GVDJVNwrWKOs0WvxCoceHZjwbdYHmtwEhI0oPpmxNe722T+3dhIv36wCfwIF5dUwm9dEJ0zMD55zOv3W4jX1svClR1K5e52paYwWck/fCcRF5fTH6gCqNdW5uHtw5xslCu3js/CY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893114; c=relaxed/simple; bh=P5J39lKA/VzRth6H4G22jnjhoe/bSb3I9NEm33ls58w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H2k5x+ByECZgspXYy6GES+kgcNWkflvWB3/JrBI+3lhFpV3lZa7B1ioS0GZVAAN0odXqruVVnVmSzPqOL25aD+PwhE8wyDotR7bkUuauj4o9zJ1quoKuY/Q+eAfWbRgQX8H27ov+kxG3zrWwJO0Ux5FNUdu1Mgyg1IsPaqbngzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=QqpASybd; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="QqpASybd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=CQ PSHzYoMoCwOMGLgwIkUsfIfCnL7xVuvDZ2rAf7ONo=; b=QqpASybdHYPjhKM9fd Lzot8PBLUCpWcnU66FkFOQzoNI6U6quhNixKdXbbLQ9+WPrgc8QVRr0itUuwaSMc fiuxk46k6/Svi9733P+fyEyyI2gPUGZOaR0TtLZMi9n2/cpqlDN8zryLzAm6GK6k Reb4QWx4WaQes9xl+PyoKtPOk= Received: from 163.com (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wA38f4Tr41pL2eqLA--.10527S4; Thu, 12 Feb 2026 18:44:40 +0800 (CST) From: Zhiquan Li To: seanjc@google.com, pbonzini@redhat.com, shuah@kernel.org Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, zhiquan_li@163.com Subject: [PATCH v2 2/4] KVM: x86: selftests: Add a flag to identify AMD compatible test cases Date: Thu, 12 Feb 2026 18:38:39 +0800 Message-ID: <20260212103841.171459-3-zhiquan_li@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260212103841.171459-1-zhiquan_li@163.com> References: <20260212103841.171459-1-zhiquan_li@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wA38f4Tr41pL2eqLA--.10527S4 X-Coremail-Antispam: 1Uf129KBjvJXoW3WFWrKF1rZw4kJr18Jr1UKFg_yoWxGFyDpa 4kAr1F9F1xXFnIya4xJw4vqF18CFZ7ua18t34jvry3ZF18Ja4xXrs7K3WjyFZ3uFWrXw13 Aa4xKF4DCanrJwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRdhL8UUUUU= X-CM-SenderInfo: 52kl13xdqbzxi6rwjhhfrp/xtbC6hmvmGmNrxna0QAA3d Content-Type: text/plain; charset="utf-8" Most of KVM x86 selftests for AMD are compatible with Hygon architecture (but not all), add a flag "host_cpu_is_amd_compatible" to figure out these cases. Following test failures on Hygon platform can be fixed: * Fix hypercall test: Hygon architecture also uses VMMCALL as guest hypercall instruction. * Following test failures due to access reserved memory address regions: - access_tracking_perf_test - demand_paging_test - dirty_log_perf_test - dirty_log_test - kvm_page_table_test - memslot_modification_stress_test - pre_fault_memory_test - x86/dirty_log_page_splitting_test Hygon CSV also makes the "physical address space width reduction", the reduced physical address bits are reported by bits 11:6 of CPUID[0x8000001f].EBX as well, so the existed logic is totally applicable for Hygon processors. Mapping memory into these regions and accessing to them results in a #PF. Signed-off-by: Zhiquan Li --- tools/testing/selftests/kvm/include/x86/processor.h | 1 + tools/testing/selftests/kvm/lib/x86/processor.c | 12 ++++++++---- tools/testing/selftests/kvm/x86/fix_hypercall_test.c | 2 +- tools/testing/selftests/kvm/x86/msrs_test.c | 2 +- tools/testing/selftests/kvm/x86/xapic_state_test.c | 2 +- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 1338de7111e7..40e3deb64812 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -22,6 +22,7 @@ extern bool host_cpu_is_intel; extern bool host_cpu_is_amd; extern bool host_cpu_is_hygon; +extern bool host_cpu_is_amd_compatible; extern uint64_t guest_tsc_khz; =20 #ifndef MAX_NR_CPUID_ENTRIES diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testin= g/selftests/kvm/lib/x86/processor.c index f6b1c5324931..f4e8649071b6 100644 --- a/tools/testing/selftests/kvm/lib/x86/processor.c +++ b/tools/testing/selftests/kvm/lib/x86/processor.c @@ -24,6 +24,7 @@ vm_vaddr_t exception_handlers; bool host_cpu_is_amd; bool host_cpu_is_intel; bool host_cpu_is_hygon; +bool host_cpu_is_amd_compatible; bool is_forced_emulation_enabled; uint64_t guest_tsc_khz; =20 @@ -794,6 +795,7 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigne= d int nr_vcpus) sync_global_to_guest(vm, host_cpu_is_intel); sync_global_to_guest(vm, host_cpu_is_amd); sync_global_to_guest(vm, host_cpu_is_hygon); + sync_global_to_guest(vm, host_cpu_is_amd_compatible); sync_global_to_guest(vm, is_forced_emulation_enabled); sync_global_to_guest(vm, pmu_errata_mask); =20 @@ -1350,7 +1352,8 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const = struct kvm_cpuid2 *cpuid, "1: vmmcall\n\t" \ "2:" \ : "=3Da"(r) \ - : [use_vmmcall] "r" (host_cpu_is_amd), inputs); \ + : [use_vmmcall] "r" (host_cpu_is_amd_compatible), \ + inputs); \ \ r; \ }) @@ -1390,8 +1393,8 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm) =20 max_gfn =3D (1ULL << (guest_maxphyaddr - vm->page_shift)) - 1; =20 - /* Avoid reserved HyperTransport region on AMD processors. */ - if (!host_cpu_is_amd) + /* Avoid reserved HyperTransport region on AMD or Hygon processors. */ + if (!host_cpu_is_amd_compatible) return max_gfn; =20 /* On parts with <40 physical address bits, the area is fully hidden */ @@ -1405,7 +1408,7 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm) =20 /* * Otherwise it's at the top of the physical address space, possibly - * reduced due to SME by bits 11:6 of CPUID[0x8000001f].EBX. Use + * reduced due to SME or CSV by bits 11:6 of CPUID[0x8000001f].EBX. Use * the old conservative value if MAXPHYADDR is not enumerated. */ if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) @@ -1427,6 +1430,7 @@ void kvm_selftest_arch_init(void) host_cpu_is_intel =3D this_cpu_is_intel(); host_cpu_is_amd =3D this_cpu_is_amd(); host_cpu_is_hygon =3D this_cpu_is_hygon(); + host_cpu_is_amd_compatible =3D host_cpu_is_amd || host_cpu_is_hygon; is_forced_emulation_enabled =3D kvm_is_forced_emulation_enabled(); =20 kvm_init_pmu_errata(); diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/t= esting/selftests/kvm/x86/fix_hypercall_test.c index 762628f7d4ba..00b6e85735dd 100644 --- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c +++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c @@ -52,7 +52,7 @@ static void guest_main(void) if (host_cpu_is_intel) { native_hypercall_insn =3D vmx_vmcall; other_hypercall_insn =3D svm_vmmcall; - } else if (host_cpu_is_amd) { + } else if (host_cpu_is_amd_compatible) { native_hypercall_insn =3D svm_vmmcall; other_hypercall_insn =3D vmx_vmcall; } else { diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/se= lftests/kvm/x86/msrs_test.c index 40d918aedce6..4c97444fdefe 100644 --- a/tools/testing/selftests/kvm/x86/msrs_test.c +++ b/tools/testing/selftests/kvm/x86/msrs_test.c @@ -81,7 +81,7 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want) * is supposed to emulate that behavior based on guest vendor model * (which is the same as the host vendor model for this test). */ - if (!host_cpu_is_amd) + if (!host_cpu_is_amd_compatible) return want; =20 switch (msr) { diff --git a/tools/testing/selftests/kvm/x86/xapic_state_test.c b/tools/tes= ting/selftests/kvm/x86/xapic_state_test.c index 3b4814c55722..0c5e12f5f14e 100644 --- a/tools/testing/selftests/kvm/x86/xapic_state_test.c +++ b/tools/testing/selftests/kvm/x86/xapic_state_test.c @@ -248,7 +248,7 @@ int main(int argc, char *argv[]) * drops writes, AMD does not). Account for the errata when checking * that KVM reads back what was written. */ - x.has_xavic_errata =3D host_cpu_is_amd && + x.has_xavic_errata =3D host_cpu_is_amd_compatible && get_kvm_amd_param_bool("avic"); =20 vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC); --=20 2.43.0 From nobody Thu Apr 2 06:28:40 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 963C52DE711; Thu, 12 Feb 2026 10:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893136; cv=none; b=s0UtHcLME2JU6oSTSNNGSitdGca4cXAUt4XmYKtvvaO36M2HM0GVi6qOz2LYMEJqDZ3aGN1hfP9zukjcMhSGZf4Qg3a3NzK9zVXNkQZVVGatTNBtZ5izaImKNOVMu0yWYxY/AlOfdjLIYBcBCvD7XZWc1LZQZ1C1syXpYx81t1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893136; c=relaxed/simple; bh=+t7xMZd2bxyA6AXpZ3ZGbX/wqavwiOsDd51RPH8NXPI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W8UcG2smpjVf+3Z6wJ9FwUYVZTR99VYjNxanNJ2zdsbLyQ1IT1mDY6KchwOsGZOnDj0s4YqfEVA+fznD+bghHDVFavw4S/B9+oQ34SJ1nyWhPSgSywqAoHApcbNgfXdY1LFzJNgSCqJ8NvaOh/hqS3hye0eOxaMQ9ZLCt6XVVv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=QW7qvKj4; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="QW7qvKj4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=66 A7mfit9unPft68eNmo36DM2y3Z3VGpv2Yc+cf0gqI=; b=QW7qvKj4uL2rIWMlKQ Ikf2e2hWtR/hE1dyVAlSPatCttDK/png6/bYxKZ8A7OPmpDLph34hi5tRm9B8tGJ Urk9rX0PJikV72hbRr6XeHlngIW9U6C0IzgQvG4bWWQQXjuvoO9j8Xv5Lm0yXTzp evn894iMTaAeUliXVuIZ+oLlQ= Received: from 163.com (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wA38f4Tr41pL2eqLA--.10527S5; Thu, 12 Feb 2026 18:44:42 +0800 (CST) From: Zhiquan Li To: seanjc@google.com, pbonzini@redhat.com, shuah@kernel.org Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, zhiquan_li@163.com Subject: [PATCH v2 3/4] KVM: x86: selftests: Allow the PMU event filter test for Hygon Date: Thu, 12 Feb 2026 18:38:40 +0800 Message-ID: <20260212103841.171459-4-zhiquan_li@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260212103841.171459-1-zhiquan_li@163.com> References: <20260212103841.171459-1-zhiquan_li@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wA38f4Tr41pL2eqLA--.10527S5 X-Coremail-Antispam: 1Uf129KBjvdXoW7Jw1DKr13Kr1rGr47CF1fXrb_yoWDJFb_JF WxKF9rArs5AFy0yr48tw4YyFWIka1fJws0qr90qF17Jr4jyF45GF4v9r1qkryxurW3K342 vF4qkr1Yvr129jkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7IUUiL07UUUUU== X-CM-SenderInfo: 52kl13xdqbzxi6rwjhhfrp/xtbC6hqvmGmNrxra5gAA3q Content-Type: text/plain; charset="utf-8" At present, the PMU event filter test for AMD architecture is applicable for Hygon architecture as well. Since all known Hygon processors can re-use the test cases, so it isn't necessary to create a new wrapper. Signed-off-by: Zhiquan Li --- tools/testing/selftests/kvm/x86/pmu_event_filter_test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tool= s/testing/selftests/kvm/x86/pmu_event_filter_test.c index 1c5b7611db24..bbd1157ef28e 100644 --- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c @@ -361,7 +361,8 @@ static bool use_intel_pmu(void) */ static bool use_amd_pmu(void) { - return host_cpu_is_amd && kvm_cpu_family() >=3D 0x17; + return (host_cpu_is_amd && kvm_cpu_family() >=3D 0x17) || + host_cpu_is_hygon; } =20 /* --=20 2.43.0 From nobody Thu Apr 2 06:28:40 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E72C1DDA24; Thu, 12 Feb 2026 10:45:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893160; cv=none; b=QgRfAOqT8l6h88VFt64uP2pDWW5EwBIDdgpyVGecDAZiQwC3WMx9IM+GE+YzuJN6+Mq+4ifNQ9jNbrDzHYTvVIMwgQ4c3r3rlJShr9k4qFQj53SrohJkj8dxyBUPeGKN0jV44YCO8006Aj65kIh6oGrvkHxX1CLKEnMW2FtB9WI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893160; c=relaxed/simple; bh=Q9lBOtUg68sa9iMHgSNiQwBdqiC8tpa9sl++GN3qSZE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lhSbglCUu2uOqfxYfxOsE7CY6bxHdC/xQxHB8RiwEi9HaJso2vesMRFRiSPH2wsXindN5vwi6+YVSWjRfKTjC8rzUqeId0ktFvipxjzQ302VKbOT22n1kbkn+XHgEX1h2i5d3qbx8fjlgPSfvVMbkhodY4M416QIMII0723Di4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=g5BOpCOI; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="g5BOpCOI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=qe ccGjVLjUuQaSbBstJwiQOfIWq48EFo6VoO+Gt3HtY=; b=g5BOpCOIBd4ujm+v3L bACpaRc4XLiIdpWizPIMP45pgaMItayZldkEpD6iG3XzjnJ04WTtuiRftr7BWZMK yoRqefmKMad48OXCC6niAAiYBrr+24xej+NOxwcprMNKq34fl84Rkja9Jqx/JOrt EzXktG0bNSJgKBomI1Nnux+dE= Received: from 163.com (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wA38f4Tr41pL2eqLA--.10527S6; Thu, 12 Feb 2026 18:44:43 +0800 (CST) From: Zhiquan Li To: seanjc@google.com, pbonzini@redhat.com, shuah@kernel.org Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, zhiquan_li@163.com, stable@vger.kernel.org Subject: [PATCH v2 4/4] KVM: selftests: Fix reserved value WRMSR testcase for multi-feature MSRs Date: Thu, 12 Feb 2026 18:38:41 +0800 Message-ID: <20260212103841.171459-5-zhiquan_li@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260212103841.171459-1-zhiquan_li@163.com> References: <20260212103841.171459-1-zhiquan_li@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wA38f4Tr41pL2eqLA--.10527S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7Kw1ktFW8WF48KrWfXryrZwb_yoW8Ar1kpa n3Jr40kr93Ka4fAayxGF4xXF18ZFnrWr40gF1Fy3srZF15Ja4xZw1xKay5Aas3urWSq3y3 Zas2gw1j9a1DJaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEqg4hUUUUU= X-CM-SenderInfo: 52kl13xdqbzxi6rwjhhfrp/xtbCwhuvmGmNrxvmkQAA3J Content-Type: text/plain; charset="utf-8" From: Sean Christopherson When determining whether or not a WRMSR with reserved bits will #GP or succeed due to the WRMSR not existing per the guest virtual CPU model, expect failure if and only if _all_ features associated with the MSR are unsupported. Checking only the primary feature results in false failures when running on AMD and Hygon CPUs with only one of RDPID or RDTSCP, as AMD/Hygon CPUs ignore MSR_TSC_AUX[63:32], i.e. don't treat the bits as reserved, and so #GP only if the MSR is unsupported. Fixes: 9c38ddb3df94 ("KVM: selftests: Add an MSR test to exercise guest/hos= t and read/write") Reported-by: Zhiquan Li Closes: https://lore.kernel.org/all/20260209041305.64906-6-zhiquan_li@163.c= om Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/x86/msrs_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/se= lftests/kvm/x86/msrs_test.c index 4c97444fdefe..f7e39bf887ad 100644 --- a/tools/testing/selftests/kvm/x86/msrs_test.c +++ b/tools/testing/selftests/kvm/x86/msrs_test.c @@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr) * If the CPU will truncate the written value (e.g. SYSENTER on AMD), * expect success and a truncated value, not #GP. */ - if (!this_cpu_has(msr->feature) || + if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) || msr->rsvd_val =3D=3D fixup_rdmsr_val(msr->index, msr->rsvd_val)) { u8 vec =3D wrmsr_safe(msr->index, msr->rsvd_val); =20 --=20 2.43.0